treewide: Convert uses of struct resource to resource_size(ptr)

Several fixes as well where the +1 was missing.

Done via coccinelle scripts like:

@@
struct resource *ptr;
@@

- ptr->end - ptr->start + 1
+ resource_size(ptr)

and some grep and typing.

Mostly uncompiled, no cross-compilers.

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This commit is contained in:
Joe Perches
2011-06-09 09:13:32 -07:00
committed by Jiri Kosina
parent 140a1ef2f9
commit 28f65c11f2
168 changed files with 308 additions and 333 deletions

View File

@@ -203,7 +203,7 @@ static int axon_ram_probe(struct platform_device *device)
goto failed;
}
bank->size = resource.end - resource.start + 1;
bank->size = resource_size(&resource);
if (bank->size == 0) {
dev_err(&device->dev, "No DDR2 memory found for %s%d\n",

View File

@@ -148,7 +148,7 @@ unsigned int cpm_pic_init(void)
if (ret)
goto end;
cpic_reg = ioremap(res.start, res.end - res.start + 1);
cpic_reg = ioremap(res.start, resource_size(&res));
if (cpic_reg == NULL)
goto end;

View File

@@ -115,7 +115,7 @@ int cpm_muram_init(void)
max = r.end;
rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
r.end - r.start + 1);
resource_size(&r));
}
muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);

View File

@@ -239,7 +239,7 @@ static int __init dart_init(struct device_node *dart_node)
DARTMAP_RPNMASK);
/* Map in DART registers */
dart = ioremap(r.start, r.end - r.start + 1);
dart = ioremap(r.start, resource_size(&r));
if (dart == NULL)
panic("DART: Cannot map registers!");

View File

@@ -349,7 +349,7 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
goto error_out;
}
msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
msi->msi_regs = ioremap(res.start, resource_size(&res));
if (!msi->msi_regs) {
dev_err(&dev->dev, "ioremap problem failed\n");
goto error_out;

View File

@@ -64,7 +64,7 @@ static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
{
resource_size_t pci_addr = res->start - offset;
resource_size_t phys_addr = res->start;
resource_size_t size = res->end - res->start + 1;
resource_size_t size = resource_size(res);
u32 flags = 0x80044000; /* enable & mem R/W */
unsigned int i;
@@ -108,7 +108,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
char *name = hose->dn->full_name;
pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
(u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
(u64)rsrc->start, (u64)resource_size(rsrc));
if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
win_idx = 2;
@@ -116,7 +116,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
end_idx = 3;
}
pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
pci = ioremap(rsrc->start, resource_size(rsrc));
if (!pci) {
dev_err(hose->parent, "Unable to map ATMU registers\n");
return;
@@ -153,9 +153,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
} else {
pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
"phy base 0x%016llx.\n",
(u64)hose->io_resource.start,
(u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
(u64)hose->io_base_phys);
(u64)hose->io_resource.start,
(u64)resource_size(&hose->io_resource),
(u64)hose->io_base_phys);
out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
out_be32(&pci->pow[j].potear, 0);
out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));

View File

@@ -1523,7 +1523,7 @@ int fsl_rio_setup(struct platform_device *dev)
port->priv = priv;
port->phys_efptr = 0x100;
priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
priv->regs_win = ioremap(regs.start, resource_size(&regs));
rio_regs_win = priv->regs_win;
/* Probe the master port phy type */

View File

@@ -736,7 +736,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
return NULL;
}
ipic->regs = ioremap(res.start, res.end - res.start + 1);
ipic->regs = ioremap(res.start, resource_size(&res));
ipic->irqhost->host_data = ipic;

View File

@@ -129,7 +129,7 @@ int __init mmio_nvram_init(void)
goto out;
}
nvram_addr = r.start;
mmio_nvram_len = r.end - r.start + 1;
mmio_nvram_len = resource_size(&r);
if ( (!mmio_nvram_len) || (!nvram_addr) ) {
printk(KERN_WARNING "nvram: address or length is 0\n");
ret = -EIO;

View File

@@ -166,7 +166,7 @@ int mpc8xx_pic_init(void)
if (ret)
goto out;
siu_reg = ioremap(res.start, res.end - res.start + 1);
siu_reg = ioremap(res.start, resource_size(&res));
if (siu_reg == NULL) {
ret = -EINVAL;
goto out;

View File

@@ -125,11 +125,11 @@ static void mv64x60_udbg_init(void)
of_node_put(np);
mpsc_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
mpsc_base = ioremap(r[0].start, resource_size(&r[0]));
if (!mpsc_base)
return;
mpsc_intr_cause = ioremap(r[1].start, r[1].end - r[1].start + 1);
mpsc_intr_cause = ioremap(r[1].start, resource_size(&r[1]));
if (!mpsc_intr_cause) {
iounmap(mpsc_base);
return;

View File

@@ -265,7 +265,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
if (ppc4xx_setup_one_pci_PMM(hose, reg,
res->start,
res->start - hose->pci_mem_offset,
res->end + 1 - res->start,
resource_size(res),
res->flags,
j) == 0) {
j++;
@@ -290,7 +290,7 @@ static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
void __iomem *reg,
const struct resource *res)
{
resource_size_t size = res->end - res->start + 1;
resource_size_t size = resource_size(res);
u32 sa;
/* Calculate window size */
@@ -349,7 +349,7 @@ static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
bus_range = of_get_property(np, "bus-range", NULL);
/* Map registers */
reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
if (reg == NULL) {
printk(KERN_ERR "%s: Can't map registers !", np->full_name);
goto fail;
@@ -465,7 +465,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
if (ppc4xx_setup_one_pcix_POM(hose, reg,
res->start,
res->start - hose->pci_mem_offset,
res->end + 1 - res->start,
resource_size(res),
res->flags,
j) == 0) {
j++;
@@ -492,7 +492,7 @@ static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
int big_pim,
int enable_msi_hole)
{
resource_size_t size = res->end - res->start + 1;
resource_size_t size = resource_size(res);
u32 sa;
/* RAM is always at 0 */
@@ -555,7 +555,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
bus_range = of_get_property(np, "bus-range", NULL);
/* Map registers */
reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
if (reg == NULL) {
printk(KERN_ERR "%s: Can't map registers !", np->full_name);
goto fail;
@@ -1604,7 +1604,7 @@ static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
res->start,
res->start - hose->pci_mem_offset,
res->end + 1 - res->start,
resource_size(res),
res->flags,
j) == 0) {
j++;
@@ -1639,7 +1639,7 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
void __iomem *mbase,
struct resource *res)
{
resource_size_t size = res->end - res->start + 1;
resource_size_t size = resource_size(res);
u64 sa;
if (port->endpoint) {

View File

@@ -347,7 +347,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
return;
}
qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
qe_ic->regs = ioremap(res.start, resource_size(&res));
qe_ic->irqhost->host_data = qe_ic;
qe_ic->hc_irq = qe_ic_irq_chip;

View File

@@ -41,7 +41,7 @@ int par_io_init(struct device_node *np)
ret = of_address_to_resource(np, 0, &res);
if (ret)
return ret;
par_io = ioremap(res.start, res.end - res.start + 1);
par_io = ioremap(res.start, resource_size(&res));
num_ports = of_get_property(np, "num-ports", NULL);
if (num_ports)

View File

@@ -247,7 +247,7 @@ static int __init icp_native_init_one_node(struct device_node *np,
return -1;
}
if (icp_native_map_one_cpu(*indx, r.start, r.end - r.start))
if (icp_native_map_one_cpu(*indx, r.start, resource_size(&r)))
return -1;
(*indx)++;