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drm/i915: support 3 pipes on IVB+

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Well almost anyway.  IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs.  So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Jesse Barnes
2011-09-02 12:54:37 -07:00
committed by Keith Packard
parent 4c609cb890
commit 27f8227b1e
7 changed files with 20 additions and 9 deletions
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7
drivers/gpu/drm/i915/intel_display.c
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@@ -2092,6 +2092,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
switch (plane) {
case 0:
case 1:
case 2:
break;
default:
DRM_ERROR("Can't update plane %d in SAREA\n", plane);
@@ -2191,6 +2192,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
case 0:
case 1:
break;
case 2:
if (IS_IVYBRIDGE(dev))
break;
/* fall through otherwise */
default:
DRM_ERROR("no plane for crtc\n");
return -EINVAL;
@@ -2889,6 +2894,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
temp |= (TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
I915_WRITE(PCH_DPLL_SEL, temp);
}