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Merge branch 'next' into for-linus

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Prepare first set of updates for 3.11 merge window.
This commit is contained in:
Dmitry Torokhov
2013-07-02 09:01:31 -07:00
parent 5705b8aca5 67bf12ca50
commit 27eb2c4b3d
10477 changed files with 592020 additions and 322464 deletions
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27
include/linux/mfd/abx500.h
View File

@@ -89,6 +89,11 @@ struct abx500_fg;
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
* @pcut_enable: Enable power cut feature in ab8505
* @pcut_max_time: Max time threshold
* @pcut_flag_time: Flagtime threshold
* @pcut_max_restart: Max number of restarts
* @pcut_debounce_time: Sets battery debounce time
*/
struct abx500_fg_parameters {
int recovery_sleep_timer;
@@ -106,6 +111,11 @@ struct abx500_fg_parameters {
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
bool pcut_enable;
u8 pcut_max_time;
u8 pcut_flag_time;
u8 pcut_max_restart;
u8 pcut_debounce_time;
};
/**
@@ -173,11 +183,11 @@ struct abx500_battery_type {
int low_high_vol_lvl;
int battery_resistance;
int n_temp_tbl_elements;
struct abx500_res_to_temp *r_to_t_tbl;
const struct abx500_res_to_temp *r_to_t_tbl;
int n_v_cap_tbl_elements;
struct abx500_v_to_cap *v_to_cap_tbl;
const struct abx500_v_to_cap *v_to_cap_tbl;
int n_batres_tbl_elements;
struct batres_vs_temp *batres_tbl;
const struct batres_vs_temp *batres_tbl;
};
/**
@@ -236,7 +246,11 @@ struct abx500_bm_charger_parameters {
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @n_chg_out_curr number of elements in array chg_output_curr
* @n_chg_in_curr number of elements in array chg_input_curr
* @chg_output_curr charger output current level map
* @chg_input_curr charger input current level map
* @maxi maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
@@ -257,6 +271,7 @@ struct abx500_bm_data {
bool autopower_cfg;
bool ac_enabled;
bool usb_enabled;
bool usb_power_path;
bool no_maintenance;
bool capacity_scaling;
bool chg_unknown_bat;
@@ -270,6 +285,10 @@ struct abx500_bm_data {
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
int n_chg_out_curr;
int n_chg_in_curr;
int *chg_output_curr;
int *chg_input_curr;
const struct abx500_maxim_parameters *maxi;
const struct abx500_bm_capacity_levels *cap_levels;
struct abx500_battery_type *bat_type;

61
include/linux/mfd/abx500/ab8500-bm.h
View File

@@ -23,6 +23,7 @@
* Bank : 0x5
*/
#define AB8500_USB_LINE_STAT_REG 0x80
#define AB8500_USB_LINE_CTRL2_REG 0x82
#define AB8500_USB_LINK1_STAT_REG 0x94
/*
@@ -33,7 +34,7 @@
#define AB8500_CH_STATUS2_REG 0x01
#define AB8500_CH_USBCH_STAT1_REG 0x02
#define AB8500_CH_USBCH_STAT2_REG 0x03
#define AB8500_CH_FSM_STAT_REG 0x04
#define AB8540_CH_USBCH_STAT3_REG 0x04
#define AB8500_CH_STAT_REG 0x05
/*
@@ -69,6 +70,8 @@
#define AB8500_USBCH_CTRL1_REG 0xC0
#define AB8500_USBCH_CTRL2_REG 0xC1
#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2
#define AB8540_USB_PP_MODE_REG 0xC5
#define AB8540_USB_PP_CHR_REG 0xC6
/*
* Gas Gauge register offsets
@@ -105,6 +108,7 @@
#define AB8500_RTC_BACKUP_CHG_REG 0x0C
#define AB8500_RTC_CC_CONF_REG 0x01
#define AB8500_RTC_CTRL_REG 0x0B
#define AB8500_RTC_CTRL1_REG 0x11
/*
* OTP register offsets
@@ -154,6 +158,7 @@
#define CH_OP_CUR_LVL_1P4 0x0D
#define CH_OP_CUR_LVL_1P5 0x0E
#define CH_OP_CUR_LVL_1P6 0x0F
#define CH_OP_CUR_LVL_2P 0x3F
/* BTEMP High thermal limits */
#define BTEMP_HIGH_TH_57_0 0x00
@@ -179,10 +184,25 @@
#define BUP_ICH_SEL_300UA 0x08
#define BUP_ICH_SEL_700UA 0x0C
#define BUP_VCH_SEL_2P5V 0x00
#define BUP_VCH_SEL_2P6V 0x01
#define BUP_VCH_SEL_2P8V 0x02
#define BUP_VCH_SEL_3P1V 0x03
enum bup_vch_sel {
BUP_VCH_SEL_2P5V,
BUP_VCH_SEL_2P6V,
BUP_VCH_SEL_2P8V,
BUP_VCH_SEL_3P1V,
/*
* Note that the following 5 values 2.7v, 2.9v, 3.0v, 3.2v, 3.3v
* are only available on ab8540. You can't choose these 5
* voltage on ab8500/ab8505/ab9540.
*/
BUP_VCH_SEL_2P7V,
BUP_VCH_SEL_2P9V,
BUP_VCH_SEL_3P0V,
BUP_VCH_SEL_3P2V,
BUP_VCH_SEL_3P3V,
};
#define BUP_VCH_RANGE 0x02
#define VBUP33_VRTCN 0x01
/* Battery OVV constants */
#define BATT_OVV_ENA 0x02
@@ -228,6 +248,8 @@
#define BAT_CTRL_20U_ENA 0x02
#define BAT_CTRL_18U_ENA 0x01
#define BAT_CTRL_16U_ENA 0x02
#define BAT_CTRL_60U_ENA 0x01
#define BAT_CTRL_120U_ENA 0x02
#define BAT_CTRL_CMP_ENA 0x04
#define FORCE_BAT_CTRL_CMP_HIGH 0x08
#define BAT_CTRL_PULL_UP_ENA 0x10
@@ -235,6 +257,24 @@
/* Battery type */
#define BATTERY_UNKNOWN 00
/* Registers for pcut feature in ab8505 and ab9540 */
#define AB8505_RTC_PCUT_CTL_STATUS_REG 0x12
#define AB8505_RTC_PCUT_TIME_REG 0x13
#define AB8505_RTC_PCUT_MAX_TIME_REG 0x14
#define AB8505_RTC_PCUT_FLAG_TIME_REG 0x15
#define AB8505_RTC_PCUT_RESTART_REG 0x16
#define AB8505_RTC_PCUT_DEBOUNCE_REG 0x17
/* USB Power Path constants for ab8540 */
#define BUS_VSYS_VOL_SELECT_MASK 0x06
#define BUS_VSYS_VOL_SELECT_3P6V 0x00
#define BUS_VSYS_VOL_SELECT_3P325V 0x02
#define BUS_VSYS_VOL_SELECT_3P9V 0x04
#define BUS_VSYS_VOL_SELECT_4P3V 0x06
#define BUS_POWER_PATH_MODE_ENA 0x01
#define BUS_PP_PRECHG_CURRENT_MASK 0x0E
#define BUS_POWER_PATH_PRECHG_ENA 0x01
/**
* struct res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
@@ -283,6 +323,11 @@ struct ab8500_fg;
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
* @pcut_enable: Enable power cut feature in ab8505
* @pcut_max_time: Max time threshold
* @pcut_flag_time: Flagtime threshold
* @pcut_max_restart: Max number of restarts
* @pcut_debunce_time: Sets battery debounce time
*/
struct ab8500_fg_parameters {
int recovery_sleep_timer;
@@ -299,6 +344,11 @@ struct ab8500_fg_parameters {
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
bool pcut_enable;
u8 pcut_max_time;
u8 pcut_flag_time;
u8 pcut_max_restart;
u8 pcut_debunce_time;
};
/**
@@ -415,6 +465,7 @@ void ab8500_fg_reinit(void);
void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
struct ab8500_btemp *ab8500_btemp_get(void);
int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
int ab8500_btemp_get_temp(struct ab8500_btemp *btemp);
struct ab8500_fg *ab8500_fg_get(void);
int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
int ab8500_fg_inst_curr_start(struct ab8500_fg *di);

74
include/linux/mfd/abx500/ab8500-gpadc.h
View File

@@ -4,32 +4,72 @@
*
* Author: Arun R Murthy <arun.murthy@stericsson.com>
* Author: Daniel Willerud <daniel.willerud@stericsson.com>
* Author: M'boumba Cedric Madianga <cedric.madianga@stericsson.com>
*/
#ifndef _AB8500_GPADC_H
#define _AB8500_GPADC_H
/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
#define BAT_CTRL 0x01
#define BTEMP_BALL 0x02
#define MAIN_CHARGER_V 0x03
#define ACC_DETECT1 0x04
#define ACC_DETECT2 0x05
#define ADC_AUX1 0x06
#define ADC_AUX2 0x07
#define MAIN_BAT_V 0x08
#define VBUS_V 0x09
#define MAIN_CHARGER_C 0x0A
#define USB_CHARGER_C 0x0B
#define BK_BAT_V 0x0C
#define DIE_TEMP 0x0D
/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2
* and ADCHwSel[4:0] in GPADCCtrl3 ) */
#define BAT_CTRL 0x01
#define BTEMP_BALL 0x02
#define MAIN_CHARGER_V 0x03
#define ACC_DETECT1 0x04
#define ACC_DETECT2 0x05
#define ADC_AUX1 0x06
#define ADC_AUX2 0x07
#define MAIN_BAT_V 0x08
#define VBUS_V 0x09
#define MAIN_CHARGER_C 0x0A
#define USB_CHARGER_C 0x0B
#define BK_BAT_V 0x0C
#define DIE_TEMP 0x0D
#define USB_ID 0x0E
#define XTAL_TEMP 0x12
#define VBAT_TRUE_MEAS 0x13
#define BAT_CTRL_AND_IBAT 0x1C
#define VBAT_MEAS_AND_IBAT 0x1D
#define VBAT_TRUE_MEAS_AND_IBAT 0x1E
#define BAT_TEMP_AND_IBAT 0x1F
/* Virtual channel used only for ibat convertion to ampere
* Battery current conversion (ibat) cannot be requested as a single conversion
* but it is always in combination with other input requests
*/
#define IBAT_VIRTUAL_CHANNEL 0xFF
#define SAMPLE_1 1
#define SAMPLE_4 4
#define SAMPLE_8 8
#define SAMPLE_16 16
#define RISING_EDGE 0
#define FALLING_EDGE 1
/* Arbitrary ADC conversion type constants */
#define ADC_SW 0
#define ADC_HW 1
struct ab8500_gpadc;
struct ab8500_gpadc *ab8500_gpadc_get(char *name);
int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
static inline int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel)
{
return ab8500_gpadc_sw_hw_convert(gpadc, channel,
SAMPLE_16, 0, 0, ADC_SW);
}
int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type,
int *ibat);
int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
u8 channel, int ad_value);
u8 channel, int ad_value);
void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h,
u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h);
#endif /* _AB8500_GPADC_H */

6
include/linux/mfd/abx500/ab8500-sysctrl.h
View File

@@ -12,6 +12,7 @@
int ab8500_sysctrl_read(u16 reg, u8 *value);
int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
void ab8500_restart(char mode, const char *cmd);
#else
@@ -40,6 +41,7 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
struct ab8500_sysctrl_platform_data {
u8 initial_req_buf_config[8];
u16 (*reboot_reason_code)(const char *cmd);
};
/* Registers */
@@ -299,4 +301,8 @@ struct ab8500_sysctrl_platform_data {
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
#define AB8500_ENABLE_WD 0x1
#define AB8500_KICK_WD 0x2
#define AB8500_WD_RESTART_ON_EXPIRE 0x10
#endif /* __AB8500_SYSCTRL_H */

16
include/linux/mfd/abx500/ab8500.h
View File

@@ -362,10 +362,10 @@ struct ab8500 {
u8 *oldmask;
int mask_size;
const int *irq_reg_offset;
int it_latchhier_num;
};
struct regulator_reg_init;
struct regulator_init_data;
struct ab8500_regulator_platform_data;
struct ab8500_gpio_platform_data;
struct ab8500_codec_platform_data;
struct ab8500_sysctrl_platform_data;
@@ -373,21 +373,13 @@ struct ab8500_sysctrl_platform_data;
/**
* struct ab8500_platform_data - AB8500 platform data
* @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
* @pm_power_off: Should machine pm power off hook be registered or not
* @init: board-specific initialization after detection of ab8500
* @num_regulator_reg_init: number of regulator init registers
* @regulator_reg_init: regulator init registers
* @num_regulator: number of regulators
* @regulator: machine-specific constraints for regulators
*/
struct ab8500_platform_data {
int irq_base;
bool pm_power_off;
void (*init) (struct ab8500 *);
int num_regulator_reg_init;
struct ab8500_regulator_reg_init *regulator_reg_init;
int num_regulator;
struct regulator_init_data *regulator;
struct ab8500_regulator_platform_data *regulator;
struct abx500_gpio_platform_data *gpio;
struct ab8500_codec_platform_data *codec;
struct ab8500_sysctrl_platform_data *sysctrl;
@@ -512,6 +504,8 @@ static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
}
void ab8500_override_turn_on_stat(u8 mask, u8 set);
#ifdef CONFIG_AB8500_DEBUG
void ab8500_dump_all_banks(struct device *dev);
void ab8500_debug_register_interrupt(int line);

7
include/linux/mfd/abx500/ux500_chargalg.h
View File

@@ -17,8 +17,11 @@ struct ux500_charger;
struct ux500_charger_ops {
int (*enable) (struct ux500_charger *, int, int, int);
int (*check_enable) (struct ux500_charger *, int, int);
int (*kick_wd) (struct ux500_charger *);
int (*update_curr) (struct ux500_charger *, int);
int (*pp_enable) (struct ux500_charger *, bool);
int (*pre_chg_enable) (struct ux500_charger *, bool);
};
/**
@@ -29,6 +32,7 @@ struct ux500_charger_ops {
* @max_out_curr maximum output charger current in mA
* @enabled indicates if this charger is used or not
* @external external charger unit (pm2xxx)
* @power_path USB power path support
*/
struct ux500_charger {
struct power_supply psy;
@@ -38,6 +42,9 @@ struct ux500_charger {
int wdt_refresh;
bool enabled;
bool external;
bool power_path;
};
extern struct blocking_notifier_head charger_notifier_list;
#endif

3
include/linux/mfd/arizona/core.h
View File

@@ -100,6 +100,9 @@ struct arizona {
struct regmap_irq_chip_data *aod_irq_chip;
struct regmap_irq_chip_data *irq_chip;
bool hpdet_magic;
unsigned int hp_ena;
struct mutex clk_lock;
int clk32k_ref;

28
include/linux/mfd/arizona/pdata.h
View File

@@ -78,6 +78,7 @@ struct arizona_micbias {
unsigned int ext_cap:1; /** External capacitor fitted */
unsigned int discharge:1; /** Actively discharge */
unsigned int fast_start:1; /** Enable aggressive startup ramp rate */
unsigned int bypass:1; /** Use bypass mode */
};
struct arizona_micd_config {
@@ -86,6 +87,11 @@ struct arizona_micd_config {
bool gpio;
};
struct arizona_micd_range {
int max; /** Ohms */
int key; /** Key to report to input layer */
};
struct arizona_pdata {
int reset; /** GPIO controlling /RESET, if any */
int ldoena; /** GPIO controlling LODENA, if any */
@@ -99,7 +105,8 @@ struct arizona_pdata {
/** If a direct 32kHz clock is provided on an MCLK specify it here */
int clk32k_src;
bool irq_active_high; /** IRQ polarity */
/** Mode for primary IRQ (defaults to active low) */
unsigned int irq_flags;
/* Base GPIO */
int gpio_base;
@@ -117,12 +124,21 @@ struct arizona_pdata {
/** GPIO5 is used for jack detection */
bool jd_gpio5;
/** Internal pull on GPIO5 is disabled when used for jack detection */
bool jd_gpio5_nopull;
/** Use the headphone detect circuit to identify the accessory */
bool hpdet_acc_id;
/** Check for line output with HPDET method */
bool hpdet_acc_id_line;
/** GPIO used for mic isolation with HPDET */
int hpdet_id_gpio;
/** Extra debounce timeout used during initial mic detection (ms) */
int micd_detect_debounce;
/** GPIO for mic detection polarity */
int micd_pol_gpio;
@@ -135,9 +151,16 @@ struct arizona_pdata {
/** Mic detect debounce level */
int micd_dbtime;
/** Mic detect timeout (ms) */
int micd_timeout;
/** Force MICBIAS on for mic detect */
bool micd_force_micbias;
/** Mic detect level parameters */
const struct arizona_micd_range *micd_ranges;
int num_micd_ranges;
/** Headset polarity configurations */
struct arizona_micd_config *micd_configs;
int num_micd_configs;
@@ -162,6 +185,9 @@ struct arizona_pdata {
/** Haptic actuator type */
unsigned int hap_act;
/** GPIO for primary IRQ (used for edge triggered emulation) */
int irq_gpio;
};
#endif

46
include/linux/mfd/arizona/registers.h
View File

@@ -85,12 +85,14 @@
#define ARIZONA_FLL1_CONTROL_6 0x176
#define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
#define ARIZONA_FLL1_NCO_TEST_0 0x178
#define ARIZONA_FLL1_CONTROL_7 0x179
#define ARIZONA_FLL1_SYNCHRONISER_1 0x181
#define ARIZONA_FLL1_SYNCHRONISER_2 0x182
#define ARIZONA_FLL1_SYNCHRONISER_3 0x183
#define ARIZONA_FLL1_SYNCHRONISER_4 0x184
#define ARIZONA_FLL1_SYNCHRONISER_5 0x185
#define ARIZONA_FLL1_SYNCHRONISER_6 0x186
#define ARIZONA_FLL1_SYNCHRONISER_7 0x187
#define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
#define ARIZONA_FLL1_GPIO_CLOCK 0x18A
#define ARIZONA_FLL2_CONTROL_1 0x191
@@ -101,12 +103,14 @@
#define ARIZONA_FLL2_CONTROL_6 0x196
#define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
#define ARIZONA_FLL2_NCO_TEST_0 0x198
#define ARIZONA_FLL2_CONTROL_7 0x199
#define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
#define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
#define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
#define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
#define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
#define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
#define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7
#define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
#define ARIZONA_MIC_CHARGE_PUMP_1 0x200
@@ -124,6 +128,10 @@
#define ARIZONA_MIC_DETECT_1 0x2A3
#define ARIZONA_MIC_DETECT_2 0x2A4
#define ARIZONA_MIC_DETECT_3 0x2A5
#define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6
#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7
#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8
#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9
#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
#define ARIZONA_ISOLATION_CONTROL 0x2CB
#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
@@ -213,6 +221,8 @@
#define ARIZONA_PDM_SPK1_CTRL_2 0x491
#define ARIZONA_PDM_SPK2_CTRL_1 0x492
#define ARIZONA_PDM_SPK2_CTRL_2 0x493
#define ARIZONA_SPK_CTRL_2 0x4B5
#define ARIZONA_SPK_CTRL_3 0x4B6
#define ARIZONA_DAC_COMP_1 0x4DC
#define ARIZONA_DAC_COMP_2 0x4DD
#define ARIZONA_DAC_COMP_3 0x4DE
@@ -1677,6 +1687,13 @@
#define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */
#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
/*
* R377 (0x179) - FLL1 Control 7
*/
#define ARIZONA_FLL1_GAIN_MASK 0x003c /* FLL1_GAIN */
#define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */
#define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */
/*
* R385 (0x181) - FLL1 Synchroniser 1
*/
@@ -1723,6 +1740,17 @@
#define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */
#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
/*
* R391 (0x187) - FLL1 Synchroniser 7
*/
#define ARIZONA_FLL1_SYNC_GAIN_MASK 0x003c /* FLL1_SYNC_GAIN */
#define ARIZONA_FLL1_SYNC_GAIN_SHIFT 2 /* FLL1_SYNC_GAIN */
#define ARIZONA_FLL1_SYNC_GAIN_WIDTH 4 /* FLL1_SYNC_GAIN */
#define ARIZONA_FLL1_SYNC_BW 0x0001 /* FLL1_SYNC_BW */
#define ARIZONA_FLL1_SYNC_BW_MASK 0x0001 /* FLL1_SYNC_BW */
#define ARIZONA_FLL1_SYNC_BW_SHIFT 0 /* FLL1_SYNC_BW */
#define ARIZONA_FLL1_SYNC_BW_WIDTH 1 /* FLL1_SYNC_BW */
/*
* R393 (0x189) - FLL1 Spread Spectrum
*/
@@ -1815,6 +1843,13 @@
#define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */
#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
/*
* R409 (0x199) - FLL2 Control 7
*/
#define ARIZONA_FLL2_GAIN_MASK 0x003c /* FLL2_GAIN */
#define ARIZONA_FLL2_GAIN_SHIFT 2 /* FLL2_GAIN */
#define ARIZONA_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN */
/*
* R417 (0x1A1) - FLL2 Synchroniser 1
*/
@@ -1861,6 +1896,17 @@
#define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */
#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
/*
* R423 (0x1A7) - FLL2 Synchroniser 7
*/
#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */
/*
* R425 (0x1A9) - FLL2 Spread Spectrum
*/

170
include/linux/mfd/cros_ec.h Normal file
View File

@@ -0,0 +1,170 @@
/*
* ChromeOS EC multi-function device
*
* Copyright (C) 2012 Google, Inc
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_MFD_CROS_EC_H
#define __LINUX_MFD_CROS_EC_H
#include <linux/mfd/cros_ec_commands.h>
/*
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
*/
enum {
EC_MSG_TX_HEADER_BYTES = 3,
EC_MSG_TX_TRAILER_BYTES = 1,
EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES +
EC_MSG_TX_TRAILER_BYTES,
EC_MSG_RX_PROTO_BYTES = 3,
/* Max length of messages */
EC_MSG_BYTES = EC_HOST_PARAM_SIZE + EC_MSG_TX_PROTO_BYTES,
};
/**
* struct cros_ec_msg - A message sent to the EC, and its reply
*
* @version: Command version number (often 0)
* @cmd: Command to send (EC_CMD_...)
* @out_buf: Outgoing payload (to EC)
* @outlen: Outgoing length
* @in_buf: Incoming payload (from EC)
* @in_len: Incoming length
*/
struct cros_ec_msg {
u8 version;
u8 cmd;
uint8_t *out_buf;
int out_len;
uint8_t *in_buf;
int in_len;
};
/**
* struct cros_ec_device - Information about a ChromeOS EC device
*
* @name: Name of this EC interface
* @priv: Private data
* @irq: Interrupt to use
* @din: input buffer (from EC)
* @dout: output buffer (to EC)
* \note
* These two buffers will always be dword-aligned and include enough
* space for up to 7 word-alignment bytes also, so we can ensure that
* the body of the message is always dword-aligned (64-bit).
*
* We use this alignment to keep ARM and x86 happy. Probably word
* alignment would be OK, there might be a small performance advantage
* to using dword.
* @din_size: size of din buffer
* @dout_size: size of dout buffer
* @command_send: send a command
* @command_recv: receive a command
* @ec_name: name of EC device (e.g. 'chromeos-ec')
* @phys_name: name of physical comms layer (e.g. 'i2c-4')
* @parent: pointer to parent device (e.g. i2c or spi device)
* @dev: Device pointer
* dev_lock: Lock to prevent concurrent access
* @wake_enabled: true if this device can wake the system from sleep
* @was_wake_device: true if this device was set to wake the system from
* sleep at the last suspend
* @event_notifier: interrupt event notifier for transport devices
*/
struct cros_ec_device {
const char *name;
void *priv;
int irq;
uint8_t *din;
uint8_t *dout;
int din_size;
int dout_size;
int (*command_send)(struct cros_ec_device *ec,
uint16_t cmd, void *out_buf, int out_len);
int (*command_recv)(struct cros_ec_device *ec,
uint16_t cmd, void *in_buf, int in_len);
int (*command_sendrecv)(struct cros_ec_device *ec,
uint16_t cmd, void *out_buf, int out_len,
void *in_buf, int in_len);
int (*command_xfer)(struct cros_ec_device *ec,
struct cros_ec_msg *msg);
const char *ec_name;
const char *phys_name;
struct device *parent;
/* These are --private-- fields - do not assign */
struct device *dev;
struct mutex dev_lock;
bool wake_enabled;
bool was_wake_device;
struct blocking_notifier_head event_notifier;
};
/**
* cros_ec_suspend - Handle a suspend operation for the ChromeOS EC device
*
* This can be called by drivers to handle a suspend event.
*
* ec_dev: Device to suspend
* @return 0 if ok, -ve on error
*/
int cros_ec_suspend(struct cros_ec_device *ec_dev);
/**
* cros_ec_resume - Handle a resume operation for the ChromeOS EC device
*
* This can be called by drivers to handle a resume event.
*
* @ec_dev: Device to resume
* @return 0 if ok, -ve on error
*/
int cros_ec_resume(struct cros_ec_device *ec_dev);
/**
* cros_ec_prepare_tx - Prepare an outgoing message in the output buffer
*
* This is intended to be used by all ChromeOS EC drivers, but at present
* only SPI uses it. Once LPC uses the same protocol it can start using it.
* I2C could use it now, with a refactor of the existing code.
*
* @ec_dev: Device to register
* @msg: Message to write
*/
int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
struct cros_ec_msg *msg);
/**
* cros_ec_remove - Remove a ChromeOS EC
*
* Call this to deregister a ChromeOS EC. After this you should call
* cros_ec_free().
*
* @ec_dev: Device to register
* @return 0 if ok, -ve on error
*/
int cros_ec_remove(struct cros_ec_device *ec_dev);
/**
* cros_ec_register - Register a new ChromeOS EC, using the provided info
*
* Before calling this, allocate a pointer to a new device and then fill
* in all the fields up to the --private-- marker.
*
* @ec_dev: Device to register
* @return 0 if ok, -ve on error
*/
int cros_ec_register(struct cros_ec_device *ec_dev);
#endif /* __LINUX_MFD_CROS_EC_H */

1369
include/linux/mfd/cros_ec_commands.h Normal file
View File

File diff suppressed because it is too large Load Diff

10
include/linux/mfd/db8500-prcmu.h
View File

@@ -489,7 +489,7 @@ struct prcmu_auto_pm_config {
#ifdef CONFIG_MFD_DB8500_PRCMU
void db8500_prcmu_early_init(void);
void db8500_prcmu_early_init(u32 phy_base, u32 size);
int prcmu_set_rc_a2p(enum romcode_write);
enum romcode_read prcmu_get_rc_p2a(void);
enum ap_pwrst prcmu_get_xp70_current_state(void);
@@ -522,12 +522,6 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
int db8500_prcmu_gic_decouple(void);
int db8500_prcmu_gic_recouple(void);
int db8500_prcmu_copy_gic_settings(void);
bool db8500_prcmu_gic_pending_irq(void);
bool db8500_prcmu_pending_irq(void);
bool db8500_prcmu_is_cpu_in_wfi(int cpu);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
@@ -553,7 +547,7 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
#else /* !CONFIG_MFD_DB8500_PRCMU */
static inline void db8500_prcmu_early_init(void) {}
static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
static inline int prcmu_set_rc_a2p(enum romcode_write code)
{

38
include/linux/mfd/dbx500-prcmu.h
View File

@@ -237,6 +237,8 @@ struct prcmu_pdata
bool enable_set_ddr_opp;
bool enable_ape_opp_100_voltage;
struct ab8500_platform_data *ab_platdata;
int ab_irq;
int irq_base;
u32 version_offset;
u32 legacy_offset;
u32 adt_offset;
@@ -276,9 +278,9 @@ struct prcmu_fw_version {
#if defined(CONFIG_UX500_SOC_DB8500)
static inline void __init prcmu_early_init(void)
static inline void prcmu_early_init(u32 phy_base, u32 size)
{
return db8500_prcmu_early_init();
return db8500_prcmu_early_init(phy_base, size);
}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
@@ -293,36 +295,6 @@ static inline u8 prcmu_get_power_state_result(void)
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_gic_decouple(void)
{
return db8500_prcmu_gic_decouple();
}
static inline int prcmu_gic_recouple(void)
{
return db8500_prcmu_gic_recouple();
}
static inline bool prcmu_gic_pending_irq(void)
{
return db8500_prcmu_gic_pending_irq();
}
static inline bool prcmu_is_cpu_in_wfi(int cpu)
{
return db8500_prcmu_is_cpu_in_wfi(cpu);
}
static inline int prcmu_copy_gic_settings(void)
{
return db8500_prcmu_copy_gic_settings();
}
static inline bool prcmu_pending_irq(void)
{
return db8500_prcmu_pending_irq();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return db8500_prcmu_set_epod(epod_id, epod_state);
@@ -500,7 +472,7 @@ static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
}
#else
static inline void __init prcmu_early_init(void) {}
static inline void prcmu_early_init(u32 phy_base, u32 size) {}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)

23
include/linux/mfd/max77693-private.h
View File

@@ -106,6 +106,29 @@ enum max77693_muic_reg {
MAX77693_MUIC_REG_END,
};
/* MAX77693 INTMASK1~2 Register */
#define INTMASK1_ADC1K_SHIFT 3
#define INTMASK1_ADCERR_SHIFT 2
#define INTMASK1_ADCLOW_SHIFT 1
#define INTMASK1_ADC_SHIFT 0
#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
#define INTMASK2_VIDRM_SHIFT 5
#define INTMASK2_VBVOLT_SHIFT 4
#define INTMASK2_DXOVP_SHIFT 3
#define INTMASK2_DCDTMR_SHIFT 2
#define INTMASK2_CHGDETRUN_SHIFT 1
#define INTMASK2_CHGTYP_SHIFT 0
#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
/* MAX77693 MUIC - STATUS1~3 Register */
#define STATUS1_ADC_SHIFT (0)
#define STATUS1_ADCLOW_SHIFT (5)

36
include/linux/mfd/palmas.h
View File

@@ -1,9 +1,10 @@
/*
* TI Palmas
*
* Copyright 2011 Texas Instruments Inc.
* Copyright 2011-2013 Texas Instruments Inc.
*
* Author: Graeme Gregory <gg@slimlogic.co.uk>
* Author: Ian Lartey <ian@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -22,6 +23,15 @@
#define PALMAS_NUM_CLIENTS 3
/* The ID_REVISION NUMBERS */
#define PALMAS_CHIP_OLD_ID 0x0000
#define PALMAS_CHIP_ID 0xC035
#define PALMAS_CHIP_CHARGER_ID 0xC036
#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
((a) == PALMAS_CHIP_ID))
#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
@@ -109,19 +119,6 @@ struct palmas_reg_init {
*/
int mode_sleep;
/* tstep is the timestep loaded to the TSTEP register
*
* For SMPS
*
* 0: Jump (no slope control)
* 1: 10mV/us
* 2: 5mV/us
* 3: 2.5mV/us
*
* For LDO unused
*/
int tstep;
/* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
* register. Set this is the default voltage set in OTP needs
* to be overridden.
@@ -154,6 +151,12 @@ enum palmas_regulators {
PALMAS_REG_LDO9,
PALMAS_REG_LDOLN,
PALMAS_REG_LDOUSB,
/* External regulators */
PALMAS_REG_REGEN1,
PALMAS_REG_REGEN2,
PALMAS_REG_REGEN3,
PALMAS_REG_SYSEN1,
PALMAS_REG_SYSEN2,
/* Total number of regulators */
PALMAS_NUM_REGS,
};
@@ -171,6 +174,9 @@ struct palmas_pmic_platform_data {
/* use LDO6 for vibrator control */
int ldo6_vibrator;
/* Enable tracking mode of LDO8 */
bool enable_ldo8_tracking;
};
struct palmas_usb_platform_data {
@@ -331,6 +337,8 @@ struct palmas_pmic {
int smps457;
int range[PALMAS_REG_SMPS10];
unsigned int ramp_delay[PALMAS_REG_SMPS10];
unsigned int current_reg_mode[PALMAS_REG_SMPS10];
};
struct palmas_resource {

8
include/linux/mfd/retu.h
View File

@@ -1,5 +1,5 @@
/*
* Retu MFD driver interface
* Retu/Tahvo MFD driver interface
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
@@ -19,4 +19,10 @@ int retu_write(struct retu_dev *, u8, u16);
#define RETU_REG_CC1 0x0d /* Common control register 1 */
#define RETU_REG_STATUS 0x16 /* Status register */
/* Interrupt sources */
#define TAHVO_INT_VBUS 0 /* VBUS state */
/* Interrupt status */
#define TAHVO_STAT_VBUS (1 << TAHVO_INT_VBUS)
#endif /* __LINUX_MFD_RETU_H */

36
include/linux/mfd/rtsx_pci.h
View File

@@ -500,6 +500,8 @@
#define BPP_POWER_15_PERCENT_ON 0x08
#define BPP_POWER_ON 0x00
#define BPP_POWER_MASK 0x0F
#define SD_VCC_PARTIAL_POWER_ON 0x02
#define SD_VCC_POWER_ON 0x00
/* PWR_GATE_CTRL */
#define PWR_GATE_EN 0x01
@@ -689,6 +691,40 @@
#define IMAGE_FLAG_ADDR0 0xCE80
#define IMAGE_FLAG_ADDR1 0xCE81
/* Phy register */
#define PHY_PCR 0x00
#define PHY_RCR0 0x01
#define PHY_RCR1 0x02
#define PHY_RCR2 0x03
#define PHY_RTCR 0x04
#define PHY_RDR 0x05
#define PHY_TCR0 0x06
#define PHY_TCR1 0x07
#define PHY_TUNE 0x08
#define PHY_IMR 0x09
#define PHY_BPCR 0x0A
#define PHY_BIST 0x0B
#define PHY_RAW_L 0x0C
#define PHY_RAW_H 0x0D
#define PHY_RAW_DATA 0x0E
#define PHY_HOST_CLK_CTRL 0x0F
#define PHY_DMR 0x10
#define PHY_BACR 0x11
#define PHY_IER 0x12
#define PHY_BCSR 0x13
#define PHY_BPR 0x14
#define PHY_BPNR2 0x15
#define PHY_BPNR 0x16
#define PHY_BRNR2 0x17
#define PHY_BENR 0x18
#define PHY_REG_REV 0x19
#define PHY_FLD0 0x1A
#define PHY_FLD1 0x1B
#define PHY_FLD2 0x1C
#define PHY_FLD3 0x1D
#define PHY_FLD4 0x1E
#define PHY_DUM_REG 0x1F
#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
struct rtsx_pcr;

533
include/linux/mfd/si476x-core.h Normal file
View File

@@ -0,0 +1,533 @@
/*
* include/media/si476x-core.h -- Common definitions for si476x core
* device
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef SI476X_CORE_H
#define SI476X_CORE_H
#include <linux/kfifo.h>
#include <linux/atomic.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/videodev2.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/si476x-platform.h>
#include <linux/mfd/si476x-reports.h>
/* Command Timeouts */
#define SI476X_DEFAULT_TIMEOUT 100000
#define SI476X_TIMEOUT_TUNE 700000
#define SI476X_TIMEOUT_POWER_UP 330000
#define SI476X_STATUS_POLL_US 0
/* -------------------- si476x-i2c.c ----------------------- */
enum si476x_freq_supported_chips {
SI476X_CHIP_SI4761 = 1,
SI476X_CHIP_SI4764,
SI476X_CHIP_SI4768,
};
enum si476x_part_revisions {
SI476X_REVISION_A10 = 0,
SI476X_REVISION_A20 = 1,
SI476X_REVISION_A30 = 2,
};
enum si476x_mfd_cells {
SI476X_RADIO_CELL = 0,
SI476X_CODEC_CELL,
SI476X_MFD_CELLS,
};
/**
* enum si476x_power_state - possible power state of the si476x
* device.
*
* @SI476X_POWER_DOWN: In this state all regulators are turned off
* and the reset line is pulled low. The device is completely
* inactive.
* @SI476X_POWER_UP_FULL: In this state all the power regualtors are
* turned on, reset line pulled high, IRQ line is enabled(polling is
* active for polling use scenario) and device is turned on with
* POWER_UP command. The device is ready to be used.
* @SI476X_POWER_INCONSISTENT: This state indicates that previous
* power down was inconsistent, meaning some of the regulators were
* not turned down and thus use of the device, without power-cycling
* is impossible.
*/
enum si476x_power_state {
SI476X_POWER_DOWN = 0,
SI476X_POWER_UP_FULL = 1,
SI476X_POWER_INCONSISTENT = 2,
};
/**
* struct si476x_core - internal data structure representing the
* underlying "core" device which all the MFD cell-devices use.
*
* @client: Actual I2C client used to transfer commands to the chip.
* @chip_id: Last digit of the chip model(E.g. "1" for SI4761)
* @cells: MFD cell devices created by this driver.
* @cmd_lock: Mutex used to serialize all the requests to the core
* device. This filed should not be used directly. Instead
* si476x_core_lock()/si476x_core_unlock() should be used to get
* exclusive access to the "core" device.
* @users: Active users counter(Used by the radio cell)
* @rds_read_queue: Wait queue used to wait for RDS data.
* @rds_fifo: FIFO in which all the RDS data received from the chip is
* placed.
* @rds_fifo_drainer: Worker that drains on-chip RDS FIFO.
* @rds_drainer_is_working: Flag used for launching only one instance
* of the @rds_fifo_drainer.
* @rds_drainer_status_lock: Lock used to guard access to the
* @rds_drainer_is_working variable.
* @command: Wait queue for wainting on the command comapletion.
* @cts: Clear To Send flag set upon receiving first status with CTS
* set.
* @tuning: Wait queue used for wainting for tune/seek comand
* completion.
* @stc: Similar to @cts, but for the STC bit of the status value.
* @power_up_parameters: Parameters used as argument for POWER_UP
* command when the device is started.
* @state: Current power state of the device.
* @supplues: Structure containing handles to all power supplies used
* by the device (NULL ones are ignored).
* @gpio_reset: GPIO pin connectet to the RSTB pin of the chip.
* @pinmux: Chip's configurable pins configuration.
* @diversity_mode: Chips role when functioning in diversity mode.
* @status_monitor: Polling worker used in polling use case scenarion
* (when IRQ is not avalible).
* @revision: Chip's running firmware revision number(Used for correct
* command set support).
*/
struct si476x_core {
struct i2c_client *client;
struct regmap *regmap;
int chip_id;
struct mfd_cell cells[SI476X_MFD_CELLS];
struct mutex cmd_lock; /* for serializing fm radio operations */
atomic_t users;
wait_queue_head_t rds_read_queue;
struct kfifo rds_fifo;
struct work_struct rds_fifo_drainer;
bool rds_drainer_is_working;
struct mutex rds_drainer_status_lock;
wait_queue_head_t command;
atomic_t cts;
wait_queue_head_t tuning;
atomic_t stc;
struct si476x_power_up_args power_up_parameters;
enum si476x_power_state power_state;
struct regulator_bulk_data supplies[4];
int gpio_reset;
struct si476x_pinmux pinmux;
enum si476x_phase_diversity_mode diversity_mode;
atomic_t is_alive;
struct delayed_work status_monitor;
#define SI476X_WORK_TO_CORE(w) container_of(to_delayed_work(w), \
struct si476x_core, \
status_monitor)
int revision;
int rds_fifo_depth;
};
static inline struct si476x_core *i2c_mfd_cell_to_core(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev->parent);
return i2c_get_clientdata(client);
}
/**
* si476x_core_lock() - lock the core device to get an exclusive access
* to it.
*/
static inline void si476x_core_lock(struct si476x_core *core)
{
mutex_lock(&core->cmd_lock);
}
/**
* si476x_core_unlock() - unlock the core device to relinquish an
* exclusive access to it.
*/
static inline void si476x_core_unlock(struct si476x_core *core)
{
mutex_unlock(&core->cmd_lock);
}
/* *_TUNE_FREQ family of commands accept frequency in multiples of
10kHz */
static inline u16 hz_to_si476x(struct si476x_core *core, int freq)
{
u16 result;
switch (core->power_up_parameters.func) {
default:
case SI476X_FUNC_FM_RECEIVER:
result = freq / 10000;
break;
case SI476X_FUNC_AM_RECEIVER:
result = freq / 1000;
break;
}
return result;
}
static inline int si476x_to_hz(struct si476x_core *core, u16 freq)
{
int result;
switch (core->power_up_parameters.func) {
default:
case SI476X_FUNC_FM_RECEIVER:
result = freq * 10000;
break;
case SI476X_FUNC_AM_RECEIVER:
result = freq * 1000;
break;
}
return result;
}
/* Since the V4L2_TUNER_CAP_LOW flag is supplied, V4L2 subsystem
* mesures frequency in 62.5 Hz units */
static inline int hz_to_v4l2(int freq)
{
return (freq * 10) / 625;
}
static inline int v4l2_to_hz(int freq)
{
return (freq * 625) / 10;
}
static inline u16 v4l2_to_si476x(struct si476x_core *core, int freq)
{
return hz_to_si476x(core, v4l2_to_hz(freq));
}
static inline int si476x_to_v4l2(struct si476x_core *core, u16 freq)
{
return hz_to_v4l2(si476x_to_hz(core, freq));
}
/**
* struct si476x_func_info - structure containing result of the
* FUNC_INFO command.
*
* @firmware.major: Firmware major number.
* @firmware.minor[...]: Firmware minor numbers.
* @patch_id:
* @func: Mode tuner is working in.
*/
struct si476x_func_info {
struct {
u8 major, minor[2];
} firmware;
u16 patch_id;
enum si476x_func func;
};
/**
* struct si476x_power_down_args - structure used to pass parameters
* to POWER_DOWN command
*
* @xosc: true - Power down, but leav oscillator running.
* false - Full power down.
*/
struct si476x_power_down_args {
bool xosc;
};
/**
* enum si476x_tunemode - enum representing possible tune modes for
* the chip.
* @SI476X_TM_VALIDATED_NORMAL_TUNE: Unconditionally stay on the new
* channel after tune, tune status is valid.
* @SI476X_TM_INVALIDATED_FAST_TUNE: Unconditionally stay in the new
* channel after tune, tune status invalid.
* @SI476X_TM_VALIDATED_AF_TUNE: Jump back to previous channel if
* metric thresholds are not met.
* @SI476X_TM_VALIDATED_AF_CHECK: Unconditionally jump back to the
* previous channel.
*/
enum si476x_tunemode {
SI476X_TM_VALIDATED_NORMAL_TUNE = 0,
SI476X_TM_INVALIDATED_FAST_TUNE = 1,
SI476X_TM_VALIDATED_AF_TUNE = 2,
SI476X_TM_VALIDATED_AF_CHECK = 3,
};
/**
* enum si476x_smoothmetrics - enum containing the possible setting fo
* audio transitioning of the chip
* @SI476X_SM_INITIALIZE_AUDIO: Initialize audio state to match this
* new channel
* @SI476X_SM_TRANSITION_AUDIO: Transition audio state from previous
* channel values to the new values
*/
enum si476x_smoothmetrics {
SI476X_SM_INITIALIZE_AUDIO = 0,
SI476X_SM_TRANSITION_AUDIO = 1,
};
/**
* struct si476x_rds_status_report - the structure representing the
* response to 'FM_RD_STATUS' command
* @rdstpptyint: Traffic program flag(TP) and/or program type(PTY)
* code has changed.
* @rdspiint: Program indentifiaction(PI) code has changed.
* @rdssyncint: RDS synchronization has changed.
* @rdsfifoint: RDS was received and the RDS FIFO has at least
* 'FM_RDS_INTERRUPT_FIFO_COUNT' elements in it.
* @tpptyvalid: TP flag and PTY code are valid falg.
* @pivalid: PI code is valid flag.
* @rdssync: RDS is currently synchronized.
* @rdsfifolost: On or more RDS groups have been lost/discarded flag.
* @tp: Current channel's TP flag.
* @pty: Current channel's PTY code.
* @pi: Current channel's PI code.
* @rdsfifoused: Number of blocks remaining in the RDS FIFO (0 if
* empty).
*/
struct si476x_rds_status_report {
bool rdstpptyint, rdspiint, rdssyncint, rdsfifoint;
bool tpptyvalid, pivalid, rdssync, rdsfifolost;
bool tp;
u8 pty;
u16 pi;
u8 rdsfifoused;
u8 ble[4];
struct v4l2_rds_data rds[4];
};
struct si476x_rsq_status_args {
bool primary;
bool rsqack;
bool attune;
bool cancel;
bool stcack;
};
enum si476x_injside {
SI476X_INJSIDE_AUTO = 0,
SI476X_INJSIDE_LOW = 1,
SI476X_INJSIDE_HIGH = 2,
};
struct si476x_tune_freq_args {
bool zifsr;
bool hd;
enum si476x_injside injside;
int freq;
enum si476x_tunemode tunemode;
enum si476x_smoothmetrics smoothmetrics;
int antcap;
};
int si476x_core_stop(struct si476x_core *, bool);
int si476x_core_start(struct si476x_core *, bool);
int si476x_core_set_power_state(struct si476x_core *, enum si476x_power_state);
bool si476x_core_has_am(struct si476x_core *);
bool si476x_core_has_diversity(struct si476x_core *);
bool si476x_core_is_a_secondary_tuner(struct si476x_core *);
bool si476x_core_is_a_primary_tuner(struct si476x_core *);
bool si476x_core_is_in_am_receiver_mode(struct si476x_core *core);
bool si476x_core_is_powered_up(struct si476x_core *core);
enum si476x_i2c_type {
SI476X_I2C_SEND,
SI476X_I2C_RECV
};
int si476x_core_i2c_xfer(struct si476x_core *,
enum si476x_i2c_type,
char *, int);
/* -------------------- si476x-cmd.c ----------------------- */
int si476x_core_cmd_func_info(struct si476x_core *, struct si476x_func_info *);
int si476x_core_cmd_set_property(struct si476x_core *, u16, u16);
int si476x_core_cmd_get_property(struct si476x_core *, u16);
int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *,
enum si476x_dclk_config,
enum si476x_dfs_config,
enum si476x_dout_config,
enum si476x_xout_config);
int si476x_core_cmd_zif_pin_cfg(struct si476x_core *,
enum si476x_iqclk_config,
enum si476x_iqfs_config,
enum si476x_iout_config,
enum si476x_qout_config);
int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *,
enum si476x_icin_config,
enum si476x_icip_config,
enum si476x_icon_config,
enum si476x_icop_config);
int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *,
enum si476x_lrout_config);
int si476x_core_cmd_intb_pin_cfg(struct si476x_core *, enum si476x_intb_config,
enum si476x_a1_config);
int si476x_core_cmd_fm_seek_start(struct si476x_core *, bool, bool);
int si476x_core_cmd_am_seek_start(struct si476x_core *, bool, bool);
int si476x_core_cmd_fm_rds_status(struct si476x_core *, bool, bool, bool,
struct si476x_rds_status_report *);
int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *, bool,
struct si476x_rds_blockcount_report *);
int si476x_core_cmd_fm_tune_freq(struct si476x_core *,
struct si476x_tune_freq_args *);
int si476x_core_cmd_am_tune_freq(struct si476x_core *,
struct si476x_tune_freq_args *);
int si476x_core_cmd_am_rsq_status(struct si476x_core *,
struct si476x_rsq_status_args *,
struct si476x_rsq_status_report *);
int si476x_core_cmd_fm_rsq_status(struct si476x_core *,
struct si476x_rsq_status_args *,
struct si476x_rsq_status_report *);
int si476x_core_cmd_power_up(struct si476x_core *,
struct si476x_power_up_args *);
int si476x_core_cmd_power_down(struct si476x_core *,
struct si476x_power_down_args *);
int si476x_core_cmd_fm_phase_div_status(struct si476x_core *);
int si476x_core_cmd_fm_phase_diversity(struct si476x_core *,
enum si476x_phase_diversity_mode);
int si476x_core_cmd_fm_acf_status(struct si476x_core *,
struct si476x_acf_status_report *);
int si476x_core_cmd_am_acf_status(struct si476x_core *,
struct si476x_acf_status_report *);
int si476x_core_cmd_agc_status(struct si476x_core *,
struct si476x_agc_status_report *);
enum si476x_power_grid_type {
SI476X_POWER_GRID_50HZ = 0,
SI476X_POWER_GRID_60HZ,
};
/* Properties */
enum si476x_interrupt_flags {
SI476X_STCIEN = (1 << 0),
SI476X_ACFIEN = (1 << 1),
SI476X_RDSIEN = (1 << 2),
SI476X_RSQIEN = (1 << 3),
SI476X_ERRIEN = (1 << 6),
SI476X_CTSIEN = (1 << 7),
SI476X_STCREP = (1 << 8),
SI476X_ACFREP = (1 << 9),
SI476X_RDSREP = (1 << 10),
SI476X_RSQREP = (1 << 11),
};
enum si476x_rdsint_sources {
SI476X_RDSTPPTY = (1 << 4),
SI476X_RDSPI = (1 << 3),
SI476X_RDSSYNC = (1 << 1),
SI476X_RDSRECV = (1 << 0),
};
enum si476x_status_response_bits {
SI476X_CTS = (1 << 7),
SI476X_ERR = (1 << 6),
/* Status response for WB receiver */
SI476X_WB_ASQ_INT = (1 << 4),
SI476X_RSQ_INT = (1 << 3),
/* Status response for FM receiver */
SI476X_FM_RDS_INT = (1 << 2),
SI476X_ACF_INT = (1 << 1),
SI476X_STC_INT = (1 << 0),
};
/* -------------------- si476x-prop.c ----------------------- */
enum si476x_common_receiver_properties {
SI476X_PROP_INT_CTL_ENABLE = 0x0000,
SI476X_PROP_DIGITAL_IO_INPUT_SAMPLE_RATE = 0x0200,
SI476X_PROP_DIGITAL_IO_INPUT_FORMAT = 0x0201,
SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100,
SI476X_PROP_SEEK_BAND_TOP = 0x1101,
SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102,
SI476X_PROP_VALID_MAX_TUNE_ERROR = 0x2000,
SI476X_PROP_VALID_SNR_THRESHOLD = 0x2003,
SI476X_PROP_VALID_RSSI_THRESHOLD = 0x2004,
};
enum si476x_am_receiver_properties {
SI476X_PROP_AUDIO_PWR_LINE_FILTER = 0x0303,
};
enum si476x_fm_receiver_properties {
SI476X_PROP_AUDIO_DEEMPHASIS = 0x0302,
SI476X_PROP_FM_RDS_INTERRUPT_SOURCE = 0x4000,
SI476X_PROP_FM_RDS_INTERRUPT_FIFO_COUNT = 0x4001,
SI476X_PROP_FM_RDS_CONFIG = 0x4002,
};
enum si476x_prop_audio_pwr_line_filter_bits {
SI476X_PROP_PWR_HARMONICS_MASK = 0x001f,
SI476X_PROP_PWR_GRID_MASK = 0x0100,
SI476X_PROP_PWR_ENABLE_MASK = 0x0200,
SI476X_PROP_PWR_GRID_50HZ = 0x0000,
SI476X_PROP_PWR_GRID_60HZ = 0x0100,
};
enum si476x_prop_fm_rds_config_bits {
SI476X_PROP_RDSEN_MASK = 0x1,
SI476X_PROP_RDSEN = 0x1,
};
struct regmap *devm_regmap_init_si476x(struct si476x_core *);
#endif /* SI476X_CORE_H */

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/*
* include/media/si476x-platform.h -- Platform data specific definitions
*
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef __SI476X_PLATFORM_H__
#define __SI476X_PLATFORM_H__
/* It is possible to select one of the four adresses using pins A0
* and A1 on SI476x */
#define SI476X_I2C_ADDR_1 0x60
#define SI476X_I2C_ADDR_2 0x61
#define SI476X_I2C_ADDR_3 0x62
#define SI476X_I2C_ADDR_4 0x63
enum si476x_iqclk_config {
SI476X_IQCLK_NOOP = 0,
SI476X_IQCLK_TRISTATE = 1,
SI476X_IQCLK_IQ = 21,
};
enum si476x_iqfs_config {
SI476X_IQFS_NOOP = 0,
SI476X_IQFS_TRISTATE = 1,
SI476X_IQFS_IQ = 21,
};
enum si476x_iout_config {
SI476X_IOUT_NOOP = 0,
SI476X_IOUT_TRISTATE = 1,
SI476X_IOUT_OUTPUT = 22,
};
enum si476x_qout_config {
SI476X_QOUT_NOOP = 0,
SI476X_QOUT_TRISTATE = 1,
SI476X_QOUT_OUTPUT = 22,
};
enum si476x_dclk_config {
SI476X_DCLK_NOOP = 0,
SI476X_DCLK_TRISTATE = 1,
SI476X_DCLK_DAUDIO = 10,
};
enum si476x_dfs_config {
SI476X_DFS_NOOP = 0,
SI476X_DFS_TRISTATE = 1,
SI476X_DFS_DAUDIO = 10,
};
enum si476x_dout_config {
SI476X_DOUT_NOOP = 0,
SI476X_DOUT_TRISTATE = 1,
SI476X_DOUT_I2S_OUTPUT = 12,
SI476X_DOUT_I2S_INPUT = 13,
};
enum si476x_xout_config {
SI476X_XOUT_NOOP = 0,
SI476X_XOUT_TRISTATE = 1,
SI476X_XOUT_I2S_INPUT = 13,
SI476X_XOUT_MODE_SELECT = 23,
};
enum si476x_icin_config {
SI476X_ICIN_NOOP = 0,
SI476X_ICIN_TRISTATE = 1,
SI476X_ICIN_GPO1_HIGH = 2,
SI476X_ICIN_GPO1_LOW = 3,
SI476X_ICIN_IC_LINK = 30,
};
enum si476x_icip_config {
SI476X_ICIP_NOOP = 0,
SI476X_ICIP_TRISTATE = 1,
SI476X_ICIP_GPO2_HIGH = 2,
SI476X_ICIP_GPO2_LOW = 3,
SI476X_ICIP_IC_LINK = 30,
};
enum si476x_icon_config {
SI476X_ICON_NOOP = 0,
SI476X_ICON_TRISTATE = 1,
SI476X_ICON_I2S = 10,
SI476X_ICON_IC_LINK = 30,
};
enum si476x_icop_config {
SI476X_ICOP_NOOP = 0,
SI476X_ICOP_TRISTATE = 1,
SI476X_ICOP_I2S = 10,
SI476X_ICOP_IC_LINK = 30,
};
enum si476x_lrout_config {
SI476X_LROUT_NOOP = 0,
SI476X_LROUT_TRISTATE = 1,
SI476X_LROUT_AUDIO = 2,
SI476X_LROUT_MPX = 3,
};
enum si476x_intb_config {
SI476X_INTB_NOOP = 0,
SI476X_INTB_TRISTATE = 1,
SI476X_INTB_DAUDIO = 10,
SI476X_INTB_IRQ = 40,
};
enum si476x_a1_config {
SI476X_A1_NOOP = 0,
SI476X_A1_TRISTATE = 1,
SI476X_A1_IRQ = 40,
};
struct si476x_pinmux {
enum si476x_dclk_config dclk;
enum si476x_dfs_config dfs;
enum si476x_dout_config dout;
enum si476x_xout_config xout;
enum si476x_iqclk_config iqclk;
enum si476x_iqfs_config iqfs;
enum si476x_iout_config iout;
enum si476x_qout_config qout;
enum si476x_icin_config icin;
enum si476x_icip_config icip;
enum si476x_icon_config icon;
enum si476x_icop_config icop;
enum si476x_lrout_config lrout;
enum si476x_intb_config intb;
enum si476x_a1_config a1;
};
enum si476x_ibias6x {
SI476X_IBIAS6X_OTHER = 0,
SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK = 1,
};
enum si476x_xstart {
SI476X_XSTART_MULTIPLE_TUNER = 0x11,
SI476X_XSTART_NORMAL = 0x77,
};
enum si476x_freq {
SI476X_FREQ_4_MHZ = 0,
SI476X_FREQ_37P209375_MHZ = 1,
SI476X_FREQ_36P4_MHZ = 2,
SI476X_FREQ_37P8_MHZ = 3,
};
enum si476x_xmode {
SI476X_XMODE_CRYSTAL_RCVR1 = 1,
SI476X_XMODE_EXT_CLOCK = 2,
SI476X_XMODE_CRYSTAL_RCVR2_3 = 3,
};
enum si476x_xbiashc {
SI476X_XBIASHC_SINGLE_RECEIVER = 0,
SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
};
enum si476x_xbias {
SI476X_XBIAS_RCVR2_3 = 0,
SI476X_XBIAS_4MHZ_RCVR1 = 3,
SI476X_XBIAS_RCVR1 = 7,
};
enum si476x_func {
SI476X_FUNC_BOOTLOADER = 0,
SI476X_FUNC_FM_RECEIVER = 1,
SI476X_FUNC_AM_RECEIVER = 2,
SI476X_FUNC_WB_RECEIVER = 3,
};
/**
* @xcload: Selects the amount of additional on-chip capacitance to
* be connected between XTAL1 and gnd and between XTAL2 and
* GND. One half of the capacitance value shown here is the
* additional load capacitance presented to the xtal. The
* minimum step size is 0.277 pF. Recommended value is 0x28
* but it will be layout dependent. Range is 0–0x3F i.e.
* (0–16.33 pF)
* @ctsien: enable CTSINT(interrupt request when CTS condition
* arises) when set
* @intsel: when set A1 pin becomes the interrupt pin; otherwise,
* INTB is the interrupt pin
* @func: selects the boot function of the device. I.e.
* SI476X_BOOTLOADER - Boot loader
* SI476X_FM_RECEIVER - FM receiver
* SI476X_AM_RECEIVER - AM receiver
* SI476X_WB_RECEIVER - Weatherband receiver
* @freq: oscillator's crystal frequency:
* SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
* SI476X_XTAL_36P4_MHZ - 36.4 Mhz
* SI476X_XTAL_37P8_MHZ - 37.8 Mhz
*/
struct si476x_power_up_args {
enum si476x_ibias6x ibias6x;
enum si476x_xstart xstart;
u8 xcload;
bool fastboot;
enum si476x_xbiashc xbiashc;
enum si476x_xbias xbias;
enum si476x_func func;
enum si476x_freq freq;
enum si476x_xmode xmode;
};
/**
* enum si476x_phase_diversity_mode - possbile phase diversity modes
* for SI4764/5/6/7 chips.
*
* @SI476X_PHDIV_DISABLED: Phase diversity feature is
* disabled.
* @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
* in combination with a
* secondary one.
* @SI476X_PHDIV_PRIMARY_ANTENNA: Tuner works as a primary tuner
* using only its own antenna.
* @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
* usning seconary tuner's antenna.
* @SI476X_PHDIV_SECONDARY_COMBINING: Tuner works as a secondary
* tuner in combination with the
* primary one.
*/
enum si476x_phase_diversity_mode {
SI476X_PHDIV_DISABLED = 0,
SI476X_PHDIV_PRIMARY_COMBINING = 1,
SI476X_PHDIV_PRIMARY_ANTENNA = 2,
SI476X_PHDIV_SECONDARY_ANTENNA = 3,
SI476X_PHDIV_SECONDARY_COMBINING = 5,
};
/*
* Platform dependent definition
*/
struct si476x_platform_data {
int gpio_reset; /* < 0 if not used */
struct si476x_power_up_args power_up_parameters;
enum si476x_phase_diversity_mode diversity_mode;
struct si476x_pinmux pinmux;
};
#endif /* __SI476X_PLATFORM_H__ */

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/*
* include/media/si476x-platform.h -- Definitions of the data formats
* returned by debugfs hooks
*
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef __SI476X_REPORTS_H__
#define __SI476X_REPORTS_H__
/**
* struct si476x_rsq_status - structure containing received signal
* quality
* @multhint: Multipath Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_MULTIPATH_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_MULTIPATH_HIGH_THRESHOLD
* @multlint: Multipath Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_MULTIPATH_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_MULTIPATH_LOW_THRESHOLD
* @snrhint: SNR Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_SNR_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_SNR_HIGH_THRESHOLD
* @snrlint: SNR Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_SNR_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_SNR_LOW_THRESHOLD
* @rssihint: RSSI Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_RSSI_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_RSSI_HIGH_THRESHOLD
* @rssilint: RSSI Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_RSSI_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_RSSI_LOW_THRESHOLD
* @bltf: Band Limit.
* Set if seek command hits the band limit or wrapped to
* the original frequency.
* @snr_ready: SNR measurement in progress.
* @rssiready: RSSI measurement in progress.
* @afcrl: Set if FREQOFF >= MAX_TUNE_ERROR
* @valid: Set if the channel is valid
* rssi < FM_VALID_RSSI_THRESHOLD
* snr < FM_VALID_SNR_THRESHOLD
* tune_error < FM_VALID_MAX_TUNE_ERROR
* @readfreq: Current tuned frequency.
* @freqoff: Signed frequency offset.
* @rssi: Received Signal Strength Indicator(dBuV).
* @snr: RF SNR Indicator(dB).
* @lassi:
* @hassi: Low/High side Adjacent(100 kHz) Channel Strength Indicator
* @mult: Multipath indicator
* @dev: Who knows? But values may vary.
* @readantcap: Antenna tuning capacity value.
* @assi: Adjacent Channel(+/- 200kHz) Strength Indicator
* @usn: Ultrasonic Noise Inticator in -DBFS
*/
struct si476x_rsq_status_report {
__u8 multhint, multlint;
__u8 snrhint, snrlint;
__u8 rssihint, rssilint;
__u8 bltf;
__u8 snr_ready;
__u8 rssiready;
__u8 injside;
__u8 afcrl;
__u8 valid;
__u16 readfreq;
__s8 freqoff;
__s8 rssi;
__s8 snr;
__s8 issi;
__s8 lassi, hassi;
__s8 mult;
__u8 dev;
__u16 readantcap;
__s8 assi;
__s8 usn;
__u8 pilotdev;
__u8 rdsdev;
__u8 assidev;
__u8 strongdev;
__u16 rdspi;
} __packed;
/**
* si476x_acf_status_report - ACF report results
*
* @blend_int: If set, indicates that stereo separation has crossed
* below the blend threshold as set by FM_ACF_BLEND_THRESHOLD
* @hblend_int: If set, indicates that HiBlend cutoff frequency is
* lower than threshold as set by FM_ACF_HBLEND_THRESHOLD
* @hicut_int: If set, indicates that HiCut cutoff frequency is lower
* than the threshold set by ACF_
*/
struct si476x_acf_status_report {
__u8 blend_int;
__u8 hblend_int;
__u8 hicut_int;
__u8 chbw_int;
__u8 softmute_int;
__u8 smute;
__u8 smattn;
__u8 chbw;
__u8 hicut;
__u8 hiblend;
__u8 pilot;
__u8 stblend;
} __packed;
enum si476x_fmagc {
SI476X_FMAGC_10K_OHM = 0,
SI476X_FMAGC_800_OHM = 1,
SI476X_FMAGC_400_OHM = 2,
SI476X_FMAGC_200_OHM = 4,
SI476X_FMAGC_100_OHM = 8,
SI476X_FMAGC_50_OHM = 16,
SI476X_FMAGC_25_OHM = 32,
SI476X_FMAGC_12P5_OHM = 64,
SI476X_FMAGC_6P25_OHM = 128,
};
struct si476x_agc_status_report {
__u8 mxhi;
__u8 mxlo;
__u8 lnahi;
__u8 lnalo;
__u8 fmagc1;
__u8 fmagc2;
__u8 pgagain;
__u8 fmwblang;
} __packed;
struct si476x_rds_blockcount_report {
__u16 expected;
__u16 received;
__u16 uncorrectable;
} __packed;
#endif /* __SI476X_REPORTS_H__ */

3
include/linux/mfd/stmpe.h
View File

@@ -26,6 +26,7 @@ enum stmpe_partnum {
STMPE801,
STMPE811,
STMPE1601,
STMPE1801,
STMPE2401,
STMPE2403,
STMPE_NBR_PARTS
@@ -39,6 +40,7 @@ enum {
STMPE_IDX_CHIP_ID,
STMPE_IDX_ICR_LSB,
STMPE_IDX_IER_LSB,
STMPE_IDX_ISR_LSB,
STMPE_IDX_ISR_MSB,
STMPE_IDX_GPMR_LSB,
STMPE_IDX_GPSR_LSB,
@@ -49,6 +51,7 @@ enum {
STMPE_IDX_GPFER_LSB,
STMPE_IDX_GPAFR_U_MSB,
STMPE_IDX_IEGPIOR_LSB,
STMPE_IDX_ISGPIOR_LSB,
STMPE_IDX_ISGPIOR_MSB,
STMPE_IDX_MAX,
};

3
include/linux/mfd/syscon.h
View File

@@ -15,8 +15,11 @@
#ifndef __LINUX_MFD_SYSCON_H__
#define __LINUX_MFD_SYSCON_H__
struct device_node;
extern struct regmap *syscon_node_to_regmap(struct device_node *np);
extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s);
extern struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
const char *property);

6
include/linux/mfd/tps65090.h
View File

@@ -27,6 +27,7 @@
/* TPS65090 IRQs */
enum {
TPS65090_IRQ_INTERRUPT,
TPS65090_IRQ_VAC_STATUS_CHANGE,
TPS65090_IRQ_VSYS_STATUS_CHANGE,
TPS65090_IRQ_BAT_STATUS_CHANGE,
@@ -86,6 +87,11 @@ struct tps65090_regulator_plat_data {
struct tps65090_platform_data {
int irq_base;
char **supplied_to;
size_t num_supplicants;
int enable_low_current_chrg;
struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
};

1
include/linux/mfd/tps65217.h
View File

@@ -228,6 +228,7 @@ enum tps65217_bl_fdim {
struct tps65217_bl_pdata {
enum tps65217_bl_isel isel;
enum tps65217_bl_fdim fdim;
int dft_brightness;
};
/**

8
include/linux/mfd/wm8994/pdata.h
View File

@@ -17,6 +17,7 @@
#define WM8994_NUM_LDO 2
#define WM8994_NUM_GPIO 11
#define WM8994_NUM_AIF 3
struct wm8994_ldo_pdata {
/** GPIOs to enable regulator, 0 or less if not available */
@@ -215,6 +216,13 @@ struct wm8994_pdata {
* system.
*/
bool spkmode_pu;
/**
* Maximum number of channels clocks will be generated for,
* useful for systems where and I2S bus with multiple data
* lines is mastered.
*/
int max_channels_clocked[WM8994_NUM_AIF];
};
#endif