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SPEAr: clk: Add Fractional Synthesizer clock

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All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Viresh Kumar
2012-04-11 18:04:23 +05:30
committed by Arnd Bergmann
parent 5335a639ec
commit 270b9f421e
3 changed files with 182 additions and 1 deletions
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16
drivers/clk/spear/clk.h
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@@ -55,6 +55,19 @@ struct clk_aux {
spinlock_t *lock;
};
/* Fractional Synth clk */
struct frac_rate_tbl {
u32 div;
};
struct clk_frac {
struct clk_hw hw;
void __iomem *reg;
struct frac_rate_tbl *rtbl;
u8 rtbl_cnt;
spinlock_t *lock;
};
/* VCO-PLL clk */
struct pll_rate_tbl {
u8 mode;
@@ -87,6 +100,9 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
const char *parent_name, unsigned long flags, void __iomem *reg,
struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
struct clk *clk_register_frac(const char *name, const char *parent_name,
unsigned long flags, void __iomem *reg,
struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
const char *vco_gate_name, const char *parent_name,
unsigned long flags, void __iomem *mode_reg, void __iomem