Merge tag 'pci-v5.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Resource management:
- Improve resource assignment for hot-added nested bridges, e.g.,
Thunderbolt (Nicholas Johnson)
Power management:
- Optionally print config space of devices before suspend (Chen Yu)
- Increase D3 delay for AMD Ryzen5/7 XHCI controllers (Daniel Drake)
Virtualization:
- Generalize DMA alias quirks (James Sewart)
- Add DMA alias quirk for PLX PEX NTB (James Sewart)
- Fix IOV memory leak (Navid Emamdoost)
AER:
- Log which device prevents error recovery (Yicong Yang)
Peer-to-peer DMA:
- Whitelist Intel SkyLake-E (Armen Baloyan)
Broadcom iProc host bridge driver:
- Apply PAXC quirk whether driver is built-in or module (Wei Liu)
Broadcom STB host bridge driver:
- Add Broadcom STB PCIe host controller driver (Jim Quinlan)
Intel Gateway SoC host bridge driver:
- Add driver for Intel Gateway SoC (Dilip Kota)
Intel VMD host bridge driver:
- Add support for DMA aliases on other buses (Jon Derrick)
- Remove dma_map_ops overrides (Jon Derrick)
- Remove now-unused X86_DEV_DMA_OPS (Christoph Hellwig)
NVIDIA Tegra host bridge driver:
- Fix Tegra30 afi_pex2_ctrl register offset (Marcel Ziswiler)
Panasonic UniPhier host bridge driver:
- Remove module code since driver can't be built as a module
(Masahiro Yamada)
Qualcomm host bridge driver:
- Add support for SDM845 PCIe controller (Bjorn Andersson)
TI Keystone host bridge driver:
- Fix "num-viewport" DT property error handling (Kishon Vijay Abraham I)
- Fix link training retries initiation (Yurii Monakov)
- Fix outbound region mapping (Yurii Monakov)
Misc:
- Add Switchtec Gen4 support (Kelvin Cao)
- Add Switchtec Intercomm Notify and Upstream Error Containment
support (Logan Gunthorpe)
- Use dma_set_mask_and_coherent() since Switchtec supports 64-bit
addressing (Wesley Sheng)"
* tag 'pci-v5.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (60 commits)
PCI: Allow adjust_bridge_window() to shrink resource if necessary
PCI: Set resource size directly in adjust_bridge_window()
PCI: Rename extend_bridge_window() to adjust_bridge_window()
PCI: Rename extend_bridge_window() parameter
PCI: Consider alignment of hot-added bridges when assigning resources
PCI: Remove local variable usage in pci_bus_distribute_available_resources()
PCI: Pass size + alignment to pci_bus_distribute_available_resources()
PCI: Rename variables
PCI: vmd: Add two VMD Device IDs
PCI: Remove unnecessary braces
PCI: brcmstb: Add MSI support
PCI: brcmstb: Add Broadcom STB PCIe host controller driver
x86/PCI: Remove X86_DEV_DMA_OPS
PCI: vmd: Remove dma_map_ops overrides
iommu/vt-d: Remove VMD child device sanity check
iommu/vt-d: Use pci_real_dma_dev() for mapping
PCI: Introduce pci_real_dma_dev()
x86/PCI: Expose VMD's pci_dev in struct pci_sysdata
x86/PCI: Add to_pci_sysdata() helper
PCI/AER: Initialize aer_fifo
...
This commit is contained in:
Linus Torvalds
97
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
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97
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
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@@ -0,0 +1,97 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Brcmstb PCIe Host Controller Device Tree Bindings
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maintainers:
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- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: brcm,bcm2711-pcie # The Raspberry Pi 4
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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items:
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- description: PCIe host controller
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- description: builtin MSI controller
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interrupt-names:
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minItems: 1
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maxItems: 2
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items:
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- const: pcie
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- const: msi
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ranges:
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maxItems: 1
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dma-ranges:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: sw_pcie
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msi-controller:
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description: Identifies the node as an MSI controller.
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msi-parent:
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description: MSI controller the device is capable of using.
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brcm,enable-ssc:
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description: Indicates usage of spread-spectrum clocking.
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type: boolean
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required:
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- reg
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- dma-ranges
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- "#interrupt-cells"
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- interrupts
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- interrupt-names
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- interrupt-map-mask
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- interrupt-map
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- msi-controller
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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scb {
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#address-cells = <2>;
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#size-cells = <1>;
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pcie0: pcie@7d500000 {
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compatible = "brcm,bcm2711-pcie";
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reg = <0x0 0x7d500000 0x9310>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0>;
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msi-controller;
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ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
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dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
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brcm,enable-ssc;
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};
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};
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138
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
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138
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
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@@ -0,0 +1,138 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PCIe RC controller on Intel Gateway SoCs
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maintainers:
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- Dilip Kota <eswara.kota@linux.intel.com>
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properties:
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compatible:
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items:
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- const: intel,lgm-pcie
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- const: snps,dw-pcie
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device_type:
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const: pci
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"#address-cells":
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const: 3
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"#size-cells":
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const: 2
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reg:
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items:
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- description: Controller control and status registers.
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- description: PCIe configuration registers.
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- description: Controller application registers.
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: app
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ranges:
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maxItems: 1
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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reset-gpios:
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maxItems: 1
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linux,pci-domain: true
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num-lanes:
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maximum: 2
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description: Number of lanes to use for this port.
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'#interrupt-cells':
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const: 1
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interrupt-map-mask:
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description: Standard PCI IRQ mapping properties.
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interrupt-map:
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description: Standard PCI IRQ mapping properties.
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max-link-speed:
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description: Specify PCI Gen for link capability.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 1, 2, 3, 4 ]
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- default: 1
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bus-range:
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description: Range of bus numbers associated with this controller.
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reset-assert-ms:
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description: |
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Delay after asserting reset to the PCIe device.
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maximum: 500
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default: 100
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required:
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- compatible
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- device_type
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- "#address-cells"
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- "#size-cells"
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- reg
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- reg-names
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- ranges
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- resets
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- clocks
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- phys
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- phy-names
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- reset-gpios
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- '#interrupt-cells'
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- interrupt-map
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- interrupt-map-mask
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/intel,lgm-clk.h>
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pcie10: pcie@d0e00000 {
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compatible = "intel,lgm-pcie", "snps,dw-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0xd0e00000 0x1000>,
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<0xd2000000 0x800000>,
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<0xd0a41000 0x1000>;
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reg-names = "dbi", "config", "app";
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linux,pci-domain = <0>;
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max-link-speed = <4>;
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bus-range = <0x00 0x08>;
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interrupt-parent = <&ioapic1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &ioapic1 27 1>,
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<0 0 0 2 &ioapic1 28 1>,
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<0 0 0 3 &ioapic1 29 1>,
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<0 0 0 4 &ioapic1 30 1>;
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ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
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resets = <&rcu0 0x50 0>;
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clocks = <&cgu0 LGM_GCLK_PCIE10>;
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phys = <&cb0phy0>;
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phy-names = "pcie";
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reset-assert-ms = <500>;
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reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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@@ -11,6 +11,7 @@
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- "qcom,pcie-ipq4019" for ipq4019
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- "qcom,pcie-ipq8074" for ipq8074
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- "qcom,pcie-qcs404" for qcs404
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- "qcom,pcie-sdm845" for sdm845
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- reg:
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Usage: required
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@@ -126,6 +127,18 @@
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- "master_bus" AXI Master clock
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- "slave_bus" AXI Slave clock
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-clock-names:
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Usage: required for sdm845
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- "slave_q2a" Slave Q2A clock
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- "tbu" PCIe TBU clock
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- "pipe" PIPE clock
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- resets:
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Usage: required
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Value type: <prop-encoded-array>
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@@ -188,6 +201,12 @@
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- "pwr" PWR reset
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- "ahb" AHB reset
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- reset-names:
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Usage: required for sdm845
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pci" PCIe core reset
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- power-domains:
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Usage: required for apq8084 and msm8996/apq8096
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Value type: <prop-encoded-array>
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