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MIPS: Add support for interAptiv cores

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The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
This commit is contained in:
Leonid Yegoshin
2013-11-27 10:07:53 +00:00
committed by Ralf Baechle
parent 0ce7d58ee0
commit 26ab96dfa9
9 changed files with 12 additions and 1 deletions
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1
arch/mips/kernel/traps.c
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@@ -1337,6 +1337,7 @@ static inline void parity_protection_init(void)
case CPU_34K:
case CPU_74K:
case CPU_1004K:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
{
#define ERRCTL_PE 0x80000000