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MIPS: Add support for interAptiv cores

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The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
This commit is contained in:
Leonid Yegoshin
2013-11-27 10:07:53 +00:00
committed by Ralf Baechle
parent 0ce7d58ee0
commit 26ab96dfa9
9 changed files with 12 additions and 1 deletions
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1
arch/mips/include/asm/cpu-type.h
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@@ -44,6 +44,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_74K:
case CPU_M14KC:
case CPU_M14KEC:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
#endif

2
arch/mips/include/asm/cpu.h
View File

@@ -295,7 +295,7 @@ enum cpu_type_enum {
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
CPU_M14KEC, CPU_PROAPTIV,
CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
/*
* MIPS64 class processors