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ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly

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Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Jonathan Austin
2016-08-30 17:24:34 +01:00
committed by Russell King
parent 5a0e069114
commit 26150aa96d
2 changed files with 26 additions and 5 deletions
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7
arch/arm/kernel/setup.c
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@@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch)
/* arch specifies the register format */
switch (arch) {
case CPU_ARCH_ARMv7:
asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
: /* No output operands */
: "r" (1));
set_csselr(CSSELR_ICACHE | CSSELR_L1);
isb();
asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
: "=r" (id_reg));
id_reg = read_ccsidr();
line_size = 4 << ((id_reg & 0x7) + 2);
num_sets = ((id_reg >> 13) & 0x7fff) + 1;
aliasing_icache = (line_size * num_sets) > PAGE_SIZE;