Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2014-11-21: - infoframe tracking (for fastboot) from Jesse - start of the dri1/ums support removal - vlv forcewake timeout fixes (Imre) - bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom O'Rourke) - on-demand pinning for execlist contexts - vlv/chv backlight improvements (Ville) - gen8+ render ctx w/a work from various people - skl edp programming (Satheeshakrishna et al.) - psr docbook (Rodrigo) - piles of little fixes and improvements all over, as usual * tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits) drm/i915: Don't pin LRC in GGTT when dumping in debugfs drm/i915: Update DRIVER_DATE to 20141121 drm/i915/g4x: fix g4x infoframe readout drm/i915: Only call mod_timer() if not already pending drm/i915: Don't rely upon encoder->type for infoframe hw state readout drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave drm/i915: Use ggtt error obj capture helper for gen8 semaphores drm/i915: vlv: increase timeout when setting idle GPU freq drm/i915: vlv: fix cdclk setting during modeset while suspended drm/i915: Dump hdmi pipe_config state drm/i915: Gen9 shadowed registers drm/i915/skl: Gen9 multi-engine forcewake drm/i915: Read power well status before other registers for drpc info drm/i915: Pin tiled objects for L-shaped configs drm/i915: Update ring freq for full gpu freq range drm/i915: change initial rps frequency for gen8 drm/i915: Keep min freq above floor on HSW/BDW drm/i915: Use efficient frequency for HSW/BDW drm/i915: Can i915_gem_init_ioctl drm/i915: Sanitize ->lastclose ...
This commit is contained in:
Dave Airlie
@@ -227,8 +227,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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return MODE_OK;
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}
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static uint32_t
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pack_aux(const uint8_t *src, int src_bytes)
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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
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int i;
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uint32_t v = 0;
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@@ -240,8 +239,7 @@ pack_aux(const uint8_t *src, int src_bytes)
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return v;
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}
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static void
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unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
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int i;
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if (dst_bytes > 4)
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@@ -863,7 +861,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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/* Load the send data into the aux channel data registers */
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for (i = 0; i < send_bytes; i += 4)
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I915_WRITE(ch_data + i,
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pack_aux(send + i, send_bytes - i));
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intel_dp_pack_aux(send + i,
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send_bytes - i));
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/* Send the command and wait for it to complete */
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I915_WRITE(ch_ctl, send_ctl);
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@@ -917,8 +916,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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recv_bytes = recv_size;
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for (i = 0; i < recv_bytes; i += 4)
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unpack_aux(I915_READ(ch_data + i),
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recv + i, recv_bytes - i);
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intel_dp_unpack_aux(I915_READ(ch_data + i),
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recv + i, recv_bytes - i);
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ret = recv_bytes;
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out:
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@@ -1074,6 +1073,33 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
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intel_connector_unregister(intel_connector);
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}
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static void
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skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
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{
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u32 ctrl1;
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pipe_config->ddi_pll_sel = SKL_DPLL0;
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pipe_config->dpll_hw_state.cfgcr1 = 0;
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pipe_config->dpll_hw_state.cfgcr2 = 0;
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ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
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switch (link_bw) {
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case DP_LINK_BW_1_62:
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ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
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SKL_DPLL0);
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break;
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case DP_LINK_BW_2_7:
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ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
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SKL_DPLL0);
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break;
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case DP_LINK_BW_5_4:
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ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
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SKL_DPLL0);
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break;
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}
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pipe_config->dpll_hw_state.ctrl1 = ctrl1;
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}
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static void
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hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
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{
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@@ -1251,7 +1277,9 @@ found:
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&pipe_config->dp_m2_n2);
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}
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_SKYLAKE(dev) && is_edp(intel_dp))
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skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
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else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
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else
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intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
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@@ -2067,385 +2095,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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}
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}
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static bool is_edp_psr(struct intel_dp *intel_dp)
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{
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return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
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}
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static bool intel_edp_is_psr_enabled(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!HAS_PSR(dev))
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return false;
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return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
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}
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static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
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struct edp_vsc_psr *vsc_psr)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
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u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
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uint32_t *data = (uint32_t *) vsc_psr;
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unsigned int i;
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/* As per BSPec (Pipe Video Data Island Packet), we need to disable
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the video DIP being updated before program video DIP data buffer
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registers for DIP being updated. */
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I915_WRITE(ctl_reg, 0);
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POSTING_READ(ctl_reg);
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for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
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if (i < sizeof(struct edp_vsc_psr))
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I915_WRITE(data_reg + i, *data++);
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else
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I915_WRITE(data_reg + i, 0);
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}
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I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
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POSTING_READ(ctl_reg);
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}
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static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
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{
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struct edp_vsc_psr psr_vsc;
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/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
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memset(&psr_vsc, 0, sizeof(psr_vsc));
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psr_vsc.sdp_header.HB0 = 0;
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psr_vsc.sdp_header.HB1 = 0x7;
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psr_vsc.sdp_header.HB2 = 0x2;
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psr_vsc.sdp_header.HB3 = 0x8;
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intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
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}
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static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t aux_clock_divider;
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int precharge = 0x3;
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bool only_standby = false;
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static const uint8_t aux_msg[] = {
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[0] = DP_AUX_NATIVE_WRITE << 4,
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[1] = DP_SET_POWER >> 8,
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[2] = DP_SET_POWER & 0xff,
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[3] = 1 - 1,
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[4] = DP_SET_POWER_D0,
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};
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int i;
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BUILD_BUG_ON(sizeof(aux_msg) > 20);
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aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
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if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
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only_standby = true;
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/* Enable PSR in sink */
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if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
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DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
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else
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
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DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
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/* Setup AUX registers */
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for (i = 0; i < sizeof(aux_msg); i += 4)
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I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
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pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
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I915_WRITE(EDP_PSR_AUX_CTL(dev),
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DP_AUX_CH_CTL_TIME_OUT_400us |
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(sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
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}
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static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t max_sleep_time = 0x1f;
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uint32_t idle_frames = 1;
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uint32_t val = 0x0;
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const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
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bool only_standby = false;
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if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
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only_standby = true;
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if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
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val |= EDP_PSR_LINK_STANDBY;
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val |= EDP_PSR_TP2_TP3_TIME_0us;
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val |= EDP_PSR_TP1_TIME_0us;
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val |= EDP_PSR_SKIP_AUX_EXIT;
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val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
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} else
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val |= EDP_PSR_LINK_DISABLE;
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I915_WRITE(EDP_PSR_CTL(dev), val |
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(IS_BROADWELL(dev) ? 0 : link_entry_time) |
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max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
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idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
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EDP_PSR_ENABLE);
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}
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static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dig_port->base.base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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lockdep_assert_held(&dev_priv->psr.lock);
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WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
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WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
|
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||||
dev_priv->psr.source_ok = false;
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if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
|
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DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
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||||
return false;
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}
|
||||
|
||||
if (!i915.enable_psr) {
|
||||
DRM_DEBUG_KMS("PSR disable by flag\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Below limitations aren't valid for Broadwell */
|
||||
if (IS_BROADWELL(dev))
|
||||
goto out;
|
||||
|
||||
if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
|
||||
S3D_ENABLE) {
|
||||
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
out:
|
||||
dev_priv->psr.source_ok = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_device *dev = intel_dig_port->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
|
||||
WARN_ON(dev_priv->psr.active);
|
||||
lockdep_assert_held(&dev_priv->psr.lock);
|
||||
|
||||
/* Enable/Re-enable PSR on the host */
|
||||
intel_edp_psr_enable_source(intel_dp);
|
||||
|
||||
dev_priv->psr.active = true;
|
||||
}
|
||||
|
||||
void intel_edp_psr_enable(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (!HAS_PSR(dev)) {
|
||||
DRM_DEBUG_KMS("PSR not supported on this platform\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!is_edp_psr(intel_dp)) {
|
||||
DRM_DEBUG_KMS("PSR not supported by this panel\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mutex_lock(&dev_priv->psr.lock);
|
||||
if (dev_priv->psr.enabled) {
|
||||
DRM_DEBUG_KMS("PSR already in use\n");
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
if (!intel_edp_psr_match_conditions(intel_dp))
|
||||
goto unlock;
|
||||
|
||||
dev_priv->psr.busy_frontbuffer_bits = 0;
|
||||
|
||||
intel_edp_psr_setup_vsc(intel_dp);
|
||||
|
||||
/* Avoid continuous PSR exit by masking memup and hpd */
|
||||
I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
|
||||
EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
|
||||
|
||||
/* Enable PSR on the panel */
|
||||
intel_edp_psr_enable_sink(intel_dp);
|
||||
|
||||
dev_priv->psr.enabled = intel_dp;
|
||||
unlock:
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
}
|
||||
|
||||
void intel_edp_psr_disable(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
mutex_lock(&dev_priv->psr.lock);
|
||||
if (!dev_priv->psr.enabled) {
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev_priv->psr.active) {
|
||||
I915_WRITE(EDP_PSR_CTL(dev),
|
||||
I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
|
||||
|
||||
/* Wait till PSR is idle */
|
||||
if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
|
||||
EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
|
||||
DRM_ERROR("Timed out waiting for PSR Idle State\n");
|
||||
|
||||
dev_priv->psr.active = false;
|
||||
} else {
|
||||
WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
|
||||
}
|
||||
|
||||
dev_priv->psr.enabled = NULL;
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
|
||||
cancel_delayed_work_sync(&dev_priv->psr.work);
|
||||
}
|
||||
|
||||
static void intel_edp_psr_work(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv), psr.work.work);
|
||||
struct intel_dp *intel_dp = dev_priv->psr.enabled;
|
||||
|
||||
/* We have to make sure PSR is ready for re-enable
|
||||
* otherwise it keeps disabled until next full enable/disable cycle.
|
||||
* PSR might take some time to get fully disabled
|
||||
* and be ready for re-enable.
|
||||
*/
|
||||
if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
|
||||
EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
|
||||
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mutex_lock(&dev_priv->psr.lock);
|
||||
intel_dp = dev_priv->psr.enabled;
|
||||
|
||||
if (!intel_dp)
|
||||
goto unlock;
|
||||
|
||||
/*
|
||||
* The delayed work can race with an invalidate hence we need to
|
||||
* recheck. Since psr_flush first clears this and then reschedules we
|
||||
* won't ever miss a flush when bailing out here.
|
||||
*/
|
||||
if (dev_priv->psr.busy_frontbuffer_bits)
|
||||
goto unlock;
|
||||
|
||||
intel_edp_psr_do_enable(intel_dp);
|
||||
unlock:
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
}
|
||||
|
||||
static void intel_edp_psr_do_exit(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->psr.active) {
|
||||
u32 val = I915_READ(EDP_PSR_CTL(dev));
|
||||
|
||||
WARN_ON(!(val & EDP_PSR_ENABLE));
|
||||
|
||||
I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
|
||||
|
||||
dev_priv->psr.active = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void intel_edp_psr_invalidate(struct drm_device *dev,
|
||||
unsigned frontbuffer_bits)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc;
|
||||
enum pipe pipe;
|
||||
|
||||
mutex_lock(&dev_priv->psr.lock);
|
||||
if (!dev_priv->psr.enabled) {
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
return;
|
||||
}
|
||||
|
||||
crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
|
||||
pipe = to_intel_crtc(crtc)->pipe;
|
||||
|
||||
intel_edp_psr_do_exit(dev);
|
||||
|
||||
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
|
||||
|
||||
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
}
|
||||
|
||||
void intel_edp_psr_flush(struct drm_device *dev,
|
||||
unsigned frontbuffer_bits)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc;
|
||||
enum pipe pipe;
|
||||
|
||||
mutex_lock(&dev_priv->psr.lock);
|
||||
if (!dev_priv->psr.enabled) {
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
return;
|
||||
}
|
||||
|
||||
crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
|
||||
pipe = to_intel_crtc(crtc)->pipe;
|
||||
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
|
||||
|
||||
/*
|
||||
* On Haswell sprite plane updates don't result in a psr invalidating
|
||||
* signal in the hardware. Which means we need to manually fake this in
|
||||
* software for all flushes, not just when we've seen a preceding
|
||||
* invalidation through frontbuffer rendering.
|
||||
*/
|
||||
if (IS_HASWELL(dev) &&
|
||||
(frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
|
||||
intel_edp_psr_do_exit(dev);
|
||||
|
||||
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
|
||||
schedule_delayed_work(&dev_priv->psr.work,
|
||||
msecs_to_jiffies(100));
|
||||
mutex_unlock(&dev_priv->psr.lock);
|
||||
}
|
||||
|
||||
void intel_edp_psr_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
|
||||
mutex_init(&dev_priv->psr.lock);
|
||||
}
|
||||
|
||||
static void intel_disable_dp(struct intel_encoder *encoder)
|
||||
{
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||
@@ -4052,8 +3701,8 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
|
||||
} while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
|
||||
|
||||
if (attempts == 0) {
|
||||
DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
|
||||
return -EIO;
|
||||
DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
|
||||
@@ -5117,7 +4766,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
|
||||
* hard to tell without seeing the user of this function of this code.
|
||||
* Check locking and ordering once that lands.
|
||||
*/
|
||||
if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
|
||||
if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
|
||||
DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
|
||||
return;
|
||||
}
|
||||
@@ -5233,6 +4882,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
|
||||
bool has_dpcd;
|
||||
struct drm_display_mode *scan;
|
||||
struct edid *edid;
|
||||
enum pipe pipe = INVALID_PIPE;
|
||||
|
||||
intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
|
||||
|
||||
@@ -5301,11 +4951,30 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
|
||||
if (IS_VALLEYVIEW(dev)) {
|
||||
intel_dp->edp_notifier.notifier_call = edp_notify_handler;
|
||||
register_reboot_notifier(&intel_dp->edp_notifier);
|
||||
|
||||
/*
|
||||
* Figure out the current pipe for the initial backlight setup.
|
||||
* If the current pipe isn't valid, try the PPS pipe, and if that
|
||||
* fails just assume pipe A.
|
||||
*/
|
||||
if (IS_CHERRYVIEW(dev))
|
||||
pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
|
||||
else
|
||||
pipe = PORT_TO_PIPE(intel_dp->DP);
|
||||
|
||||
if (pipe != PIPE_A && pipe != PIPE_B)
|
||||
pipe = intel_dp->pps_pipe;
|
||||
|
||||
if (pipe != PIPE_A && pipe != PIPE_B)
|
||||
pipe = PIPE_A;
|
||||
|
||||
DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
|
||||
pipe_name(pipe));
|
||||
}
|
||||
|
||||
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
|
||||
intel_connector->panel.backlight_power = intel_edp_backlight_power;
|
||||
intel_panel_setup_backlight(connector);
|
||||
intel_panel_setup_backlight(connector, pipe);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user