Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2014-11-21: - infoframe tracking (for fastboot) from Jesse - start of the dri1/ums support removal - vlv forcewake timeout fixes (Imre) - bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom O'Rourke) - on-demand pinning for execlist contexts - vlv/chv backlight improvements (Ville) - gen8+ render ctx w/a work from various people - skl edp programming (Satheeshakrishna et al.) - psr docbook (Rodrigo) - piles of little fixes and improvements all over, as usual * tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits) drm/i915: Don't pin LRC in GGTT when dumping in debugfs drm/i915: Update DRIVER_DATE to 20141121 drm/i915/g4x: fix g4x infoframe readout drm/i915: Only call mod_timer() if not already pending drm/i915: Don't rely upon encoder->type for infoframe hw state readout drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave drm/i915: Use ggtt error obj capture helper for gen8 semaphores drm/i915: vlv: increase timeout when setting idle GPU freq drm/i915: vlv: fix cdclk setting during modeset while suspended drm/i915: Dump hdmi pipe_config state drm/i915: Gen9 shadowed registers drm/i915/skl: Gen9 multi-engine forcewake drm/i915: Read power well status before other registers for drpc info drm/i915: Pin tiled objects for L-shaped configs drm/i915: Update ring freq for full gpu freq range drm/i915: change initial rps frequency for gen8 drm/i915: Keep min freq above floor on HSW/BDW drm/i915: Use efficient frequency for HSW/BDW drm/i915: Can i915_gem_init_ioctl drm/i915: Sanitize ->lastclose ...
This commit is contained in:
Dave Airlie
@@ -159,33 +159,6 @@ i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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return i915_gem_obj_bound_any(obj) && !obj->active;
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}
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int
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i915_gem_init_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_init *args = data;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return -ENODEV;
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if (args->gtt_start >= args->gtt_end ||
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(args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
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return -EINVAL;
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/* GEM with user mode setting was never supported on ilk and later. */
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if (INTEL_INFO(dev)->gen >= 5)
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return -ENODEV;
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mutex_lock(&dev->struct_mutex);
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i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
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args->gtt_end);
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dev_priv->gtt.mappable_end = args->gtt_end;
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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int
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i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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@@ -208,40 +181,137 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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return 0;
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}
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static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
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static int
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i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
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{
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drm_dma_handle_t *phys = obj->phys_handle;
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struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
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char *vaddr = obj->phys_handle->vaddr;
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struct sg_table *st;
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struct scatterlist *sg;
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int i;
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if (!phys)
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return;
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if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
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return -EINVAL;
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if (obj->madv == I915_MADV_WILLNEED) {
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for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
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struct page *page;
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char *src;
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page = shmem_read_mapping_page(mapping, i);
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if (IS_ERR(page))
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return PTR_ERR(page);
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src = kmap_atomic(page);
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memcpy(vaddr, src, PAGE_SIZE);
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drm_clflush_virt_range(vaddr, PAGE_SIZE);
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kunmap_atomic(src);
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page_cache_release(page);
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vaddr += PAGE_SIZE;
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}
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i915_gem_chipset_flush(obj->base.dev);
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st = kmalloc(sizeof(*st), GFP_KERNEL);
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if (st == NULL)
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return -ENOMEM;
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if (sg_alloc_table(st, 1, GFP_KERNEL)) {
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kfree(st);
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return -ENOMEM;
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}
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sg = st->sgl;
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sg->offset = 0;
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sg->length = obj->base.size;
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sg_dma_address(sg) = obj->phys_handle->busaddr;
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sg_dma_len(sg) = obj->base.size;
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obj->pages = st;
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obj->has_dma_mapping = true;
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return 0;
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}
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static void
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i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
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{
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int ret;
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BUG_ON(obj->madv == __I915_MADV_PURGED);
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ret = i915_gem_object_set_to_cpu_domain(obj, true);
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if (ret) {
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/* In the event of a disaster, abandon all caches and
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* hope for the best.
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*/
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WARN_ON(ret != -EIO);
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obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
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}
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if (obj->madv == I915_MADV_DONTNEED)
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obj->dirty = 0;
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if (obj->dirty) {
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struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
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char *vaddr = phys->vaddr;
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char *vaddr = obj->phys_handle->vaddr;
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int i;
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for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
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struct page *page = shmem_read_mapping_page(mapping, i);
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if (!IS_ERR(page)) {
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char *dst = kmap_atomic(page);
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memcpy(dst, vaddr, PAGE_SIZE);
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drm_clflush_virt_range(dst, PAGE_SIZE);
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kunmap_atomic(dst);
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struct page *page;
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char *dst;
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set_page_dirty(page);
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page = shmem_read_mapping_page(mapping, i);
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if (IS_ERR(page))
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continue;
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dst = kmap_atomic(page);
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drm_clflush_virt_range(vaddr, PAGE_SIZE);
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memcpy(dst, vaddr, PAGE_SIZE);
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kunmap_atomic(dst);
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set_page_dirty(page);
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if (obj->madv == I915_MADV_WILLNEED)
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mark_page_accessed(page);
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page_cache_release(page);
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}
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page_cache_release(page);
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vaddr += PAGE_SIZE;
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}
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i915_gem_chipset_flush(obj->base.dev);
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obj->dirty = 0;
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}
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#ifdef CONFIG_X86
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set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
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#endif
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drm_pci_free(obj->base.dev, phys);
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obj->phys_handle = NULL;
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sg_free_table(obj->pages);
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kfree(obj->pages);
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obj->has_dma_mapping = false;
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}
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static void
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i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
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{
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drm_pci_free(obj->base.dev, obj->phys_handle);
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}
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static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
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.get_pages = i915_gem_object_get_pages_phys,
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.put_pages = i915_gem_object_put_pages_phys,
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.release = i915_gem_object_release_phys,
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};
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static int
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drop_pages(struct drm_i915_gem_object *obj)
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{
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struct i915_vma *vma, *next;
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int ret;
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drm_gem_object_reference(&obj->base);
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list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
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if (i915_vma_unbind(vma))
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break;
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ret = i915_gem_object_put_pages(obj);
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drm_gem_object_unreference(&obj->base);
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return ret;
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}
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int
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@@ -249,9 +319,7 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
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int align)
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{
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drm_dma_handle_t *phys;
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struct address_space *mapping;
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char *vaddr;
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int i;
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int ret;
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if (obj->phys_handle) {
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if ((unsigned long)obj->phys_handle->vaddr & (align -1))
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@@ -266,41 +334,19 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
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if (obj->base.filp == NULL)
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return -EINVAL;
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ret = drop_pages(obj);
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if (ret)
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return ret;
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/* create a new object */
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phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
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if (!phys)
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return -ENOMEM;
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vaddr = phys->vaddr;
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#ifdef CONFIG_X86
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set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
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#endif
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mapping = file_inode(obj->base.filp)->i_mapping;
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for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
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struct page *page;
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char *src;
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page = shmem_read_mapping_page(mapping, i);
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if (IS_ERR(page)) {
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#ifdef CONFIG_X86
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set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
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#endif
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drm_pci_free(obj->base.dev, phys);
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return PTR_ERR(page);
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}
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src = kmap_atomic(page);
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memcpy(vaddr, src, PAGE_SIZE);
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kunmap_atomic(src);
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mark_page_accessed(page);
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page_cache_release(page);
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vaddr += PAGE_SIZE;
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}
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obj->phys_handle = phys;
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return 0;
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obj->ops = &i915_gem_phys_ops;
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return i915_gem_object_get_pages(obj);
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}
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static int
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@@ -311,6 +357,14 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
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struct drm_device *dev = obj->base.dev;
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void *vaddr = obj->phys_handle->vaddr + args->offset;
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char __user *user_data = to_user_ptr(args->data_ptr);
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int ret;
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/* We manually control the domain here and pretend that it
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* remains coherent i.e. in the GTT domain, like shmem_pwrite.
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*/
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ret = i915_gem_object_wait_rendering(obj, false);
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if (ret)
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return ret;
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if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
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unsigned long unwritten;
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@@ -326,6 +380,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
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return -EFAULT;
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}
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drm_clflush_virt_range(vaddr, args->size);
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i915_gem_chipset_flush(dev);
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return 0;
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}
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@@ -1048,11 +1103,6 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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* pread/pwrite currently are reading and writing from the CPU
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* perspective, requiring manual detiling by the client.
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*/
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if (obj->phys_handle) {
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ret = i915_gem_phys_pwrite(obj, args, file);
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goto out;
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}
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if (obj->tiling_mode == I915_TILING_NONE &&
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obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
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cpu_write_needs_clflush(obj)) {
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@@ -1062,8 +1112,12 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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* textures). Fallback to the shmem path in that case. */
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}
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if (ret == -EFAULT || ret == -ENOSPC)
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ret = i915_gem_shmem_pwrite(dev, obj, args, file);
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if (ret == -EFAULT || ret == -ENOSPC) {
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if (obj->phys_handle)
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ret = i915_gem_phys_pwrite(obj, args, file);
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else
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ret = i915_gem_shmem_pwrite(dev, obj, args, file);
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}
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out:
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drm_gem_object_unreference(&obj->base);
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@@ -2140,6 +2194,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
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if (i915_gem_object_needs_bit17_swizzle(obj))
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i915_gem_object_do_bit_17_swizzle(obj);
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if (obj->tiling_mode != I915_TILING_NONE &&
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dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
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i915_gem_object_pin_pages(obj);
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return 0;
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err_pages:
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@@ -2438,15 +2496,13 @@ int __i915_add_request(struct intel_engine_cs *ring,
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ring->outstanding_lazy_seqno = 0;
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ring->preallocated_lazy_request = NULL;
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if (!dev_priv->ums.mm_suspended) {
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i915_queue_hangcheck(ring->dev);
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i915_queue_hangcheck(ring->dev);
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cancel_delayed_work_sync(&dev_priv->mm.idle_work);
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queue_delayed_work(dev_priv->wq,
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&dev_priv->mm.retire_work,
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round_jiffies_up_relative(HZ));
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intel_mark_busy(dev_priv->dev);
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}
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cancel_delayed_work_sync(&dev_priv->mm.idle_work);
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queue_delayed_work(dev_priv->wq,
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&dev_priv->mm.retire_work,
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round_jiffies_up_relative(HZ));
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intel_mark_busy(dev_priv->dev);
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||||
if (out_seqno)
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*out_seqno = request->seqno;
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||||
@@ -2513,12 +2569,18 @@ static void i915_set_reset_status(struct drm_i915_private *dev_priv,
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static void i915_gem_free_request(struct drm_i915_gem_request *request)
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{
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struct intel_context *ctx = request->ctx;
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list_del(&request->list);
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||||
i915_gem_request_remove_from_client(request);
|
||||
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||||
if (request->ctx)
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||||
i915_gem_context_unreference(request->ctx);
|
||||
if (i915.enable_execlists && ctx) {
|
||||
struct intel_engine_cs *ring = request->ring;
|
||||
|
||||
if (ctx != ring->default_context)
|
||||
intel_lr_context_unpin(ring, ctx);
|
||||
i915_gem_context_unreference(ctx);
|
||||
}
|
||||
kfree(request);
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||||
}
|
||||
|
||||
@@ -2572,6 +2634,23 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
||||
i915_gem_object_move_to_inactive(obj);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear the execlists queue up before freeing the requests, as those
|
||||
* are the ones that keep the context and ringbuffer backing objects
|
||||
* pinned in place.
|
||||
*/
|
||||
while (!list_empty(&ring->execlist_queue)) {
|
||||
struct intel_ctx_submit_request *submit_req;
|
||||
|
||||
submit_req = list_first_entry(&ring->execlist_queue,
|
||||
struct intel_ctx_submit_request,
|
||||
execlist_link);
|
||||
list_del(&submit_req->execlist_link);
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
i915_gem_context_unreference(submit_req->ctx);
|
||||
kfree(submit_req);
|
||||
}
|
||||
|
||||
/*
|
||||
* We must free the requests after all the corresponding objects have
|
||||
* been moved off active lists. Which is the same order as the normal
|
||||
@@ -2589,18 +2668,6 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
||||
i915_gem_free_request(request);
|
||||
}
|
||||
|
||||
while (!list_empty(&ring->execlist_queue)) {
|
||||
struct intel_ctx_submit_request *submit_req;
|
||||
|
||||
submit_req = list_first_entry(&ring->execlist_queue,
|
||||
struct intel_ctx_submit_request,
|
||||
execlist_link);
|
||||
list_del(&submit_req->execlist_link);
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
i915_gem_context_unreference(submit_req->ctx);
|
||||
kfree(submit_req);
|
||||
}
|
||||
|
||||
/* These may not have been flush before the reset, do so now */
|
||||
kfree(ring->preallocated_lazy_request);
|
||||
ring->preallocated_lazy_request = NULL;
|
||||
@@ -2737,6 +2804,15 @@ i915_gem_retire_requests(struct drm_device *dev)
|
||||
for_each_ring(ring, dev_priv, i) {
|
||||
i915_gem_retire_requests_ring(ring);
|
||||
idle &= list_empty(&ring->request_list);
|
||||
if (i915.enable_execlists) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ring->execlist_lock, flags);
|
||||
idle &= list_empty(&ring->execlist_queue);
|
||||
spin_unlock_irqrestore(&ring->execlist_lock, flags);
|
||||
|
||||
intel_execlists_retire_requests(ring);
|
||||
}
|
||||
}
|
||||
|
||||
if (idle)
|
||||
@@ -3527,7 +3603,7 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj,
|
||||
* Stolen memory is always coherent with the GPU as it is explicitly
|
||||
* marked as wc by the system, or the system is cache-coherent.
|
||||
*/
|
||||
if (obj->stolen)
|
||||
if (obj->stolen || obj->phys_handle)
|
||||
return false;
|
||||
|
||||
/* If the GPU is snooping the contents of the CPU cache,
|
||||
@@ -4320,6 +4396,7 @@ int
|
||||
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_i915_gem_madvise *args = data;
|
||||
struct drm_i915_gem_object *obj;
|
||||
int ret;
|
||||
@@ -4347,6 +4424,15 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (obj->pages &&
|
||||
obj->tiling_mode != I915_TILING_NONE &&
|
||||
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
|
||||
if (obj->madv == I915_MADV_WILLNEED)
|
||||
i915_gem_object_unpin_pages(obj);
|
||||
if (args->madv == I915_MADV_WILLNEED)
|
||||
i915_gem_object_pin_pages(obj);
|
||||
}
|
||||
|
||||
if (obj->madv != __I915_MADV_PURGED)
|
||||
obj->madv = args->madv;
|
||||
|
||||
@@ -4489,8 +4575,6 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
|
||||
}
|
||||
}
|
||||
|
||||
i915_gem_object_detach_phys(obj);
|
||||
|
||||
/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
|
||||
* before progressing. */
|
||||
if (obj->stolen)
|
||||
@@ -4498,6 +4582,11 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
|
||||
|
||||
WARN_ON(obj->frontbuffer_bits);
|
||||
|
||||
if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
|
||||
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
|
||||
obj->tiling_mode != I915_TILING_NONE)
|
||||
i915_gem_object_unpin_pages(obj);
|
||||
|
||||
if (WARN_ON(obj->pages_pin_count))
|
||||
obj->pages_pin_count = 0;
|
||||
if (discard_backing_storage(obj))
|
||||
@@ -4570,9 +4659,6 @@ i915_gem_suspend(struct drm_device *dev)
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
if (dev_priv->ums.mm_suspended)
|
||||
goto err;
|
||||
|
||||
ret = i915_gpu_idle(dev);
|
||||
if (ret)
|
||||
goto err;
|
||||
@@ -4583,15 +4669,7 @@ i915_gem_suspend(struct drm_device *dev)
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
i915_gem_evict_everything(dev);
|
||||
|
||||
i915_kernel_lost_context(dev);
|
||||
i915_gem_stop_ringbuffers(dev);
|
||||
|
||||
/* Hack! Don't let anybody do execbuf while we don't control the chip.
|
||||
* We need to replace this with a semaphore, or something.
|
||||
* And not confound ums.mm_suspended!
|
||||
*/
|
||||
dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
|
||||
DRIVER_MODESET);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
|
||||
@@ -4882,9 +4960,6 @@ int i915_gem_init(struct drm_device *dev)
|
||||
}
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
/* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
dev_priv->dri1.allow_batchbuffer = 1;
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -4899,74 +4974,6 @@ i915_gem_cleanup_ringbuffer(struct drm_device *dev)
|
||||
dev_priv->gt.cleanup_ring(ring);
|
||||
}
|
||||
|
||||
int
|
||||
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
return 0;
|
||||
|
||||
if (i915_reset_in_progress(&dev_priv->gpu_error)) {
|
||||
DRM_ERROR("Reenabling wedged hardware, good luck\n");
|
||||
atomic_set(&dev_priv->gpu_error.reset_counter, 0);
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
dev_priv->ums.mm_suspended = 0;
|
||||
|
||||
ret = i915_gem_init_hw(dev);
|
||||
if (ret != 0) {
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
|
||||
|
||||
ret = drm_irq_install(dev, dev->pdev->irq);
|
||||
if (ret)
|
||||
goto cleanup_ringbuffer;
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup_ringbuffer:
|
||||
i915_gem_cleanup_ringbuffer(dev);
|
||||
dev_priv->ums.mm_suspended = 1;
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
drm_irq_uninstall(dev);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
return i915_gem_suspend(dev);
|
||||
}
|
||||
|
||||
void
|
||||
i915_gem_lastclose(struct drm_device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
return;
|
||||
|
||||
ret = i915_gem_suspend(dev);
|
||||
if (ret)
|
||||
DRM_ERROR("failed to idle hardware: %d\n", ret);
|
||||
}
|
||||
|
||||
static void
|
||||
init_ring_lists(struct intel_engine_cs *ring)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user