ARM: tegra: Add speedo-based process identification
Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren

parent
1f851a262b
commit
25cd5a3914
@@ -35,9 +35,11 @@ int tegra_sku_id;
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int tegra_cpu_process_id;
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int tegra_core_process_id;
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int tegra_chip_id;
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int tegra_soc_speedo_id;
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enum tegra_revision tegra_revision;
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static int tegra_fuse_spare_bit;
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static void (*tegra_init_speedo_data)(void);
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/* The BCT to use at boot is specified by board straps that can be read
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* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
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@@ -91,6 +93,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
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}
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}
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static void tegra_get_process_id(void)
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{
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u32 reg;
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_cpu_process_id = (reg >> 6) & 3;
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_core_process_id = (reg >> 12) & 3;
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}
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void tegra_init_fuse(void)
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{
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u32 id;
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@@ -102,21 +114,24 @@ void tegra_init_fuse(void)
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reg = tegra_fuse_readl(FUSE_SKU_INFO);
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tegra_sku_id = reg & 0xFF;
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tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_cpu_process_id = (reg >> 6) & 3;
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_core_process_id = (reg >> 12) & 3;
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reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
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tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
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id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
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tegra_chip_id = (id >> 8) & 0xff;
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tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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switch (tegra_chip_id) {
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case TEGRA20:
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tegra_init_speedo_data = &tegra20_init_speedo_data;
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break;
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default:
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tegra_init_speedo_data = &tegra_get_process_id;
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}
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tegra_revision = tegra_get_revision(id);
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tegra_init_speedo_data();
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
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tegra_revision_name[tegra_revision],
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