b43: flush some writes on Broadcom MIPS SoCs
Access to PHY and radio registers is indirect on Broadcom hardware and it seems that addressing on some MIPS SoCs may require flushing. So far this problem was noticed on 0x4716 SoC only (marketing names: BCM4717, BCM4718). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville

parent
d342b95dd7
commit
25c1556663
@@ -813,7 +813,7 @@ static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
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static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
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u16 set)
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{
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b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
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b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
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b43_write16(dev, B43_MMIO_PHY_DATA,
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(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
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}
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@@ -823,14 +823,14 @@ static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
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/* LCN-PHY needs 0x200 for read access */
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reg |= 0x200;
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b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
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b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
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return b43_read16(dev, B43_MMIO_RADIO24_DATA);
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}
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static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
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u16 value)
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{
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b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
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b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
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b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
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}
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