rtlwifi: Move common routines to core
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Larry Finger
committed by
John W. Linville
John W. Linville
parent
f3355dd9f7
commit
25b13dbc38
@@ -30,6 +30,7 @@
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#include "../wifi.h"
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#include "../pci.h"
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#include "../ps.h"
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#include "../core.h"
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#include "reg.h"
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#include "def.h"
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#include "phy.h"
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@@ -242,7 +243,7 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
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else if (rtlhal->during_mac0init_radiob)
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/* mac0 use phy1 write radio_b. */
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dbi_direct = BIT(3) | BIT(2);
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if (bitmask != BMASKDWORD) {
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if (bitmask != MASKDWORD) {
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if (rtlhal->during_mac1init_radioa ||
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rtlhal->during_mac0init_radiob)
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originalvalue = rtl92de_read_dword_dbi(hw,
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@@ -275,20 +276,20 @@ static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
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u32 retvalue;
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newoffset = offset;
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tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
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tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
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if (rfpath == RF90_PATH_A)
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tmplong2 = tmplong;
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else
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tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
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tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
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tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
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(newoffset << 23) | BLSSIREADEDGE;
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
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tmplong & (~BLSSIREADEDGE));
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udelay(10);
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
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rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
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udelay(50);
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udelay(50);
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
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rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
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tmplong | BLSSIREADEDGE);
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udelay(10);
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if (rfpath == RF90_PATH_A)
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@@ -321,7 +322,7 @@ static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
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newoffset = offset;
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/* T65 RF */
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data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
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rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
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rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
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rfpath, pphyreg->rf3wire_offset, data_and_addr);
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}
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@@ -362,7 +363,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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return;
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spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
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if (rtlphy->rf_mode != RF_OP_BY_FW) {
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if (bitmask != BRFREGOFFSETMASK) {
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if (bitmask != RFREG_OFFSET_MASK) {
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original_value = _rtl92d_phy_rf_serial_read(hw,
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rfpath, regaddr);
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bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
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@@ -567,19 +568,8 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
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" ===> phy:Rtl819XPHY_REG_Array_PG\n");
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if (configtype == BASEBAND_CONFIG_PHY_REG) {
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for (i = 0; i < phy_reg_arraylen; i = i + 2) {
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if (phy_regarray_table[i] == 0xfe)
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mdelay(50);
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else if (phy_regarray_table[i] == 0xfd)
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mdelay(5);
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else if (phy_regarray_table[i] == 0xfc)
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mdelay(1);
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else if (phy_regarray_table[i] == 0xfb)
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udelay(50);
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else if (phy_regarray_table[i] == 0xfa)
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udelay(5);
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else if (phy_regarray_table[i] == 0xf9)
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udelay(1);
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rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
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rtl_addr_delay(phy_regarray_table[i]);
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rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
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phy_regarray_table[i + 1]);
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udelay(1);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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@@ -591,7 +581,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
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if (rtlhal->interfaceindex == 0) {
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for (i = 0; i < agctab_arraylen; i = i + 2) {
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rtl_set_bbreg(hw, agctab_array_table[i],
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BMASKDWORD,
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MASKDWORD,
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agctab_array_table[i + 1]);
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/* Add 1us delay between BB/RF register
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* setting. */
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@@ -607,7 +597,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
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if (rtlhal->current_bandtype == BAND_ON_2_4G) {
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for (i = 0; i < agctab_arraylen; i = i + 2) {
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rtl_set_bbreg(hw, agctab_array_table[i],
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BMASKDWORD,
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MASKDWORD,
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agctab_array_table[i + 1]);
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/* Add 1us delay between BB/RF register
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* setting. */
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@@ -623,7 +613,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
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for (i = 0; i < agctab_5garraylen; i = i + 2) {
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rtl_set_bbreg(hw,
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agctab_5garray_table[i],
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BMASKDWORD,
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MASKDWORD,
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agctab_5garray_table[i + 1]);
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/* Add 1us delay between BB/RF registeri
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* setting. */
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@@ -705,18 +695,7 @@ static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
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phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
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if (configtype == BASEBAND_CONFIG_PHY_REG) {
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for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
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if (phy_regarray_table_pg[i] == 0xfe)
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mdelay(50);
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else if (phy_regarray_table_pg[i] == 0xfd)
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mdelay(5);
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else if (phy_regarray_table_pg[i] == 0xfc)
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mdelay(1);
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else if (phy_regarray_table_pg[i] == 0xfb)
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udelay(50);
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else if (phy_regarray_table_pg[i] == 0xfa)
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udelay(5);
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else if (phy_regarray_table_pg[i] == 0xf9)
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udelay(1);
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rtl_addr_delay(phy_regarray_table_pg[i]);
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_rtl92d_store_pwrindex_diffrate_offset(hw,
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phy_regarray_table_pg[i],
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phy_regarray_table_pg[i + 1],
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@@ -843,54 +822,16 @@ bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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switch (rfpath) {
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case RF90_PATH_A:
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for (i = 0; i < radioa_arraylen; i = i + 2) {
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if (radioa_array_table[i] == 0xfe) {
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mdelay(50);
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} else if (radioa_array_table[i] == 0xfd) {
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/* delay_ms(5); */
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mdelay(5);
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} else if (radioa_array_table[i] == 0xfc) {
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/* delay_ms(1); */
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mdelay(1);
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} else if (radioa_array_table[i] == 0xfb) {
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udelay(50);
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} else if (radioa_array_table[i] == 0xfa) {
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udelay(5);
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} else if (radioa_array_table[i] == 0xf9) {
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udelay(1);
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} else {
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rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
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BRFREGOFFSETMASK,
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radioa_array_table[i + 1]);
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/* Add 1us delay between BB/RF register set. */
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udelay(1);
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}
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rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
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RFREG_OFFSET_MASK,
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radioa_array_table[i + 1]);
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}
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break;
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case RF90_PATH_B:
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for (i = 0; i < radiob_arraylen; i = i + 2) {
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if (radiob_array_table[i] == 0xfe) {
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/* Delay specific ms. Only RF configuration
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* requires delay. */
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mdelay(50);
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} else if (radiob_array_table[i] == 0xfd) {
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/* delay_ms(5); */
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mdelay(5);
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} else if (radiob_array_table[i] == 0xfc) {
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/* delay_ms(1); */
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mdelay(1);
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} else if (radiob_array_table[i] == 0xfb) {
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udelay(50);
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} else if (radiob_array_table[i] == 0xfa) {
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udelay(5);
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} else if (radiob_array_table[i] == 0xf9) {
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udelay(1);
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} else {
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rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
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BRFREGOFFSETMASK,
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radiob_array_table[i + 1]);
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/* Add 1us delay between BB/RF register set. */
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udelay(1);
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}
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rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
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RFREG_OFFSET_MASK,
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radiob_array_table[i + 1]);
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}
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break;
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case RF90_PATH_C:
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@@ -911,13 +852,13 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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rtlphy->default_initialgain[0] =
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(u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
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(u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
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rtlphy->default_initialgain[1] =
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(u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
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(u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
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rtlphy->default_initialgain[2] =
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(u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
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(u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
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rtlphy->default_initialgain[3] =
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(u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
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(u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
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rtlphy->default_initialgain[0],
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@@ -925,9 +866,9 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
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rtlphy->default_initialgain[2],
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rtlphy->default_initialgain[3]);
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rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
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BMASKBYTE0);
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MASKBYTE0);
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rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
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BMASKDWORD);
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MASKDWORD);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Default framesync (0x%x) = 0x%x\n",
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ROFDM0_RXDETECTOR3, rtlphy->framesync);
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@@ -1106,7 +1047,7 @@ static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
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{
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rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
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rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
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rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
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rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
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rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
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}
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@@ -1168,7 +1109,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 imr_num = MAX_RF_IMR_INDEX;
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u32 rfmask = BRFREGOFFSETMASK;
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u32 rfmask = RFREG_OFFSET_MASK;
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u8 group, i;
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unsigned long flag = 0;
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@@ -1211,7 +1152,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
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for (i = 0; i < imr_num; i++) {
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rtl_set_rfreg(hw, (enum radio_path)rfpath,
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rf_reg_for_5g_swchnl_normal[i],
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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rf_imr_param_normal[0][0][i]);
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}
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rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
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@@ -1329,7 +1270,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
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rtl_set_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_5g[i],
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BRFREGOFFSETMASK, 0xE439D);
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RFREG_OFFSET_MASK, 0xE439D);
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} else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
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u4tmp2 = (rf_reg_pram_c_5g[index][i] &
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0x7FF) | (u4tmp << 11);
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@@ -1337,11 +1278,11 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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u4tmp2 &= ~(BIT(7) | BIT(6));
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rtl_set_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_5g[i],
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BRFREGOFFSETMASK, u4tmp2);
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RFREG_OFFSET_MASK, u4tmp2);
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} else {
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rtl_set_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_5g[i],
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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rf_reg_pram_c_5g[index][i]);
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}
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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@@ -1351,7 +1292,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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path, index,
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rtl_get_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_5g[i],
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BRFREGOFFSETMASK));
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RFREG_OFFSET_MASK));
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}
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if (need_pwr_down)
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_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
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@@ -1381,7 +1322,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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i++) {
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rtl_set_rfreg(hw, rfpath,
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rf_for_c_cut_5g_internal_pa[i],
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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rf_pram_c_5g_int_pa[index][i]);
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RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
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"offset 0x%x value 0x%x path %d index %d\n",
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@@ -1422,13 +1363,13 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
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rtl_set_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_2g[i],
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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(rf_reg_param_for_c_cut_2g[index][i] |
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BIT(17)));
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else
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rtl_set_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_2g[i],
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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rf_reg_param_for_c_cut_2g
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[index][i]);
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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@@ -1438,14 +1379,14 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
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rf_reg_mask_for_c_cut_2g[i], path, index,
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rtl_get_rfreg(hw, (enum radio_path)path,
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rf_reg_for_c_cut_2g[i],
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BRFREGOFFSETMASK));
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RFREG_OFFSET_MASK));
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}
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RTPRINT(rtlpriv, FINIT, INIT_IQK,
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"cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
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rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
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rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
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BRFREGOFFSETMASK,
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RFREG_OFFSET_MASK,
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rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
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if (need_pwr_down)
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_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
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@@ -1493,41 +1434,41 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
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/* path-A IQK setting */
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RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
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if (rtlhal->interfaceindex == 0) {
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rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
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rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
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rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
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rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
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} else {
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rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
|
||||
}
|
||||
rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
|
||||
rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
|
||||
rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
|
||||
rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
|
||||
/* path-B IQK setting */
|
||||
if (configpathb) {
|
||||
rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
|
||||
rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
|
||||
rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
|
||||
rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
|
||||
rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
|
||||
}
|
||||
/* LO calibration setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
|
||||
rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
|
||||
/* One shot, path A LOK & IQK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
|
||||
/* delay x ms */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Delay %d ms for One shot, path A LOK & IQK\n",
|
||||
IQK_DELAY_TIME);
|
||||
mdelay(IQK_DELAY_TIME);
|
||||
/* Check failed */
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
|
||||
rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
|
||||
rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
|
||||
rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
|
||||
rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
|
||||
regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
|
||||
regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
|
||||
if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
|
||||
(((rege9c & 0x03FF0000) >> 16) != 0x42))
|
||||
@@ -1563,42 +1504,42 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
|
||||
/* path-A IQK setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
|
||||
rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
|
||||
rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
|
||||
rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
|
||||
/* path-B IQK setting */
|
||||
if (configpathb) {
|
||||
rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
|
||||
rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
|
||||
rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
|
||||
rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
|
||||
}
|
||||
/* LO calibration setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
|
||||
rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
|
||||
/* path-A PA on */
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
|
||||
for (i = 0; i < retrycount; i++) {
|
||||
/* One shot, path A LOK & IQK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"One shot, path A LOK & IQK!\n");
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
|
||||
/* delay x ms */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Delay %d ms for One shot, path A LOK & IQK.\n",
|
||||
IQK_DELAY_TIME);
|
||||
mdelay(IQK_DELAY_TIME * 10);
|
||||
/* Check failed */
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
|
||||
rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
|
||||
rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
|
||||
rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
|
||||
rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
|
||||
regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
|
||||
regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
|
||||
if (!(regeac & TxOKBit) &&
|
||||
(((rege94 & 0x03FF0000) >> 16) != 0x142)) {
|
||||
@@ -1620,9 +1561,9 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
|
||||
}
|
||||
}
|
||||
/* path A PA off */
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
|
||||
rtlphy->iqk_bb_backup[0]);
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
|
||||
rtlphy->iqk_bb_backup[1]);
|
||||
return result;
|
||||
}
|
||||
@@ -1637,22 +1578,22 @@ static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
|
||||
/* One shot, path B LOK & IQK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
|
||||
rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
|
||||
rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
|
||||
rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
|
||||
rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
|
||||
/* delay x ms */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
|
||||
mdelay(IQK_DELAY_TIME);
|
||||
/* Check failed */
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
|
||||
regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
|
||||
regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
|
||||
regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
|
||||
regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
|
||||
regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
|
||||
regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
|
||||
regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
|
||||
regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
|
||||
if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
|
||||
(((regebc & 0x03FF0000) >> 16) != 0x42))
|
||||
@@ -1680,31 +1621,31 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
|
||||
/* path-A IQK setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
|
||||
rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
|
||||
rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
|
||||
rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
|
||||
rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
|
||||
|
||||
/* path-B IQK setting */
|
||||
rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
|
||||
rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
|
||||
rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
|
||||
rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
|
||||
rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
|
||||
|
||||
/* LO calibration setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
|
||||
rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
|
||||
|
||||
/* path-B PA on */
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
|
||||
|
||||
for (i = 0; i < retrycount; i++) {
|
||||
/* One shot, path B LOK & IQK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"One shot, path A LOK & IQK!\n");
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
|
||||
rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
|
||||
rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
|
||||
|
||||
/* delay x ms */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
@@ -1712,15 +1653,15 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
|
||||
mdelay(IQK_DELAY_TIME * 10);
|
||||
|
||||
/* Check failed */
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
|
||||
regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
|
||||
regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
|
||||
regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
|
||||
regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
|
||||
regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
|
||||
regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
|
||||
regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
|
||||
regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
|
||||
regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
|
||||
if (!(regeac & BIT(31)) &&
|
||||
(((regeb4 & 0x03FF0000) >> 16) != 0x142))
|
||||
@@ -1738,9 +1679,9 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
|
||||
}
|
||||
|
||||
/* path B PA off */
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
|
||||
rtlphy->iqk_bb_backup[0]);
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
|
||||
rtlphy->iqk_bb_backup[2]);
|
||||
return result;
|
||||
}
|
||||
@@ -1754,7 +1695,7 @@ static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
|
||||
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
|
||||
for (i = 0; i < regnum; i++)
|
||||
adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
|
||||
adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
|
||||
}
|
||||
|
||||
static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
|
||||
@@ -1779,7 +1720,7 @@ static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Reload ADDA power saving parameters !\n");
|
||||
for (i = 0; i < regnum; i++)
|
||||
rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
|
||||
rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
|
||||
}
|
||||
|
||||
static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
|
||||
@@ -1807,7 +1748,7 @@ static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
|
||||
pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
|
||||
0x04db25a4 : 0x0b1b25a4;
|
||||
for (i = 0; i < IQK_ADDA_REG_NUM; i++)
|
||||
rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
|
||||
rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
|
||||
}
|
||||
|
||||
static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
|
||||
@@ -1830,9 +1771,9 @@ static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
|
||||
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
|
||||
}
|
||||
|
||||
static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
|
||||
@@ -1843,8 +1784,8 @@ static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
|
||||
mode = pi_mode ? 0x01000100 : 0x01000000;
|
||||
rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
|
||||
rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
|
||||
rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
|
||||
rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
|
||||
}
|
||||
|
||||
static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
@@ -1875,7 +1816,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
|
||||
if (t == 0) {
|
||||
bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
|
||||
bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
|
||||
is2t ? "2T2R" : "1T1R");
|
||||
@@ -1898,40 +1839,40 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
_rtl92d_phy_pimode_switch(hw, true);
|
||||
|
||||
rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
|
||||
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
|
||||
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
|
||||
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
|
||||
if (is2t) {
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
|
||||
0x00010000);
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
|
||||
0x00010000);
|
||||
}
|
||||
/* MAC settings */
|
||||
_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
|
||||
rtlphy->iqk_mac_backup);
|
||||
/* Page B init */
|
||||
rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
|
||||
rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
|
||||
if (is2t)
|
||||
rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
|
||||
rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
|
||||
/* IQ calibration setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
|
||||
rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
|
||||
rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
|
||||
rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
|
||||
rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
|
||||
for (i = 0; i < retrycount; i++) {
|
||||
patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
|
||||
if (patha_ok == 0x03) {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path A IQK Success!!\n");
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
|
||||
result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
|
||||
result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
break;
|
||||
} else if (i == (retrycount - 1) && patha_ok == 0x01) {
|
||||
@@ -1939,9 +1880,9 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path A IQK Only Tx Success!!\n");
|
||||
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
}
|
||||
}
|
||||
@@ -1957,22 +1898,22 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path B IQK Success!!\n");
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
result[t][6] = (rtl_get_bbreg(hw, 0xec4,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
result[t][7] = (rtl_get_bbreg(hw, 0xecc,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
break;
|
||||
} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
|
||||
/* Tx IQK OK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path B Only Tx IQK Success!!\n");
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc,
|
||||
BMASKDWORD) & 0x3FF0000) >> 16;
|
||||
MASKDWORD) & 0x3FF0000) >> 16;
|
||||
}
|
||||
}
|
||||
if (0x00 == pathb_ok)
|
||||
@@ -1984,7 +1925,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"IQK:Back to BB mode, load original value!\n");
|
||||
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
|
||||
if (t != 0) {
|
||||
/* Switch back BB to SI mode after finish IQ Calibration. */
|
||||
if (!rtlphy->rfpi_enable)
|
||||
@@ -2004,8 +1945,8 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
|
||||
rtlphy->iqk_bb_backup,
|
||||
IQK_BB_REG_NUM - 1);
|
||||
/* load 0xe30 IQC default value */
|
||||
rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
|
||||
rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
|
||||
rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
|
||||
rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
|
||||
}
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
|
||||
}
|
||||
@@ -2042,7 +1983,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
|
||||
mdelay(IQK_DELAY_TIME * 20);
|
||||
if (t == 0) {
|
||||
bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
|
||||
bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
|
||||
is2t ? "2T2R" : "1T1R");
|
||||
@@ -2072,38 +2013,38 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
|
||||
if (!rtlphy->rfpi_enable)
|
||||
_rtl92d_phy_pimode_switch(hw, true);
|
||||
rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
|
||||
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
|
||||
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
|
||||
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
|
||||
|
||||
/* Page B init */
|
||||
rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
|
||||
rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
|
||||
if (is2t)
|
||||
rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
|
||||
rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
|
||||
/* IQ calibration setting */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
|
||||
rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
|
||||
rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
|
||||
rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
|
||||
rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
|
||||
patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
|
||||
if (patha_ok == 0x03) {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
|
||||
result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
|
||||
result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
} else if (patha_ok == 0x01) { /* Tx IQK OK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path A IQK Only Tx Success!!\n");
|
||||
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
|
||||
result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
|
||||
result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
} else {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
|
||||
@@ -2116,20 +2057,20 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
|
||||
if (pathb_ok == 0x03) {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path B IQK Success!!\n");
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
|
||||
result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
|
||||
result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
} else if (pathb_ok == 0x01) { /* Tx IQK OK */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"Path B Only Tx IQK Success!!\n");
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
|
||||
result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
|
||||
result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
|
||||
0x3FF0000) >> 16;
|
||||
} else {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
@@ -2140,7 +2081,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
|
||||
/* Back to BB mode, load original value */
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"IQK:Back to BB mode, load original value!\n");
|
||||
rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
|
||||
rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
|
||||
if (t != 0) {
|
||||
if (is2t)
|
||||
_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
|
||||
@@ -2240,7 +2181,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
|
||||
return;
|
||||
} else if (iqk_ok) {
|
||||
oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
|
||||
BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
|
||||
MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
|
||||
val_x = result[final_candidate][0];
|
||||
if ((val_x & 0x00000200) != 0)
|
||||
val_x = val_x | 0xFFFFFC00;
|
||||
@@ -2271,7 +2212,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
|
||||
((val_y * oldval_0 >> 7) & 0x1));
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
|
||||
rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
|
||||
BMASKDWORD));
|
||||
MASKDWORD));
|
||||
if (txonly) {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
|
||||
return;
|
||||
@@ -2299,7 +2240,7 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
|
||||
return;
|
||||
} else if (iqk_ok) {
|
||||
oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
|
||||
BMASKDWORD) >> 22) & 0x3FF;
|
||||
MASKDWORD) >> 22) & 0x3FF;
|
||||
val_x = result[final_candidate][4];
|
||||
if ((val_x & 0x00000200) != 0)
|
||||
val_x = val_x | 0xFFFFFC00;
|
||||
@@ -2657,7 +2598,7 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
|
||||
rf_mode[index] = rtl_read_byte(rtlpriv, offset);
|
||||
/* 2. Set RF mode = standby mode */
|
||||
rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
|
||||
BRFREGOFFSETMASK, 0x010000);
|
||||
RFREG_OFFSET_MASK, 0x010000);
|
||||
if (rtlpci->init_ready) {
|
||||
/* switch CV-curve control by LC-calibration */
|
||||
rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
|
||||
@@ -2667,16 +2608,16 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
|
||||
0x08000, 0x01);
|
||||
}
|
||||
u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
|
||||
BRFREGOFFSETMASK);
|
||||
RFREG_OFFSET_MASK);
|
||||
while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
|
||||
mdelay(50);
|
||||
timecount += 50;
|
||||
u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
|
||||
RF_SYN_G6, BRFREGOFFSETMASK);
|
||||
RF_SYN_G6, RFREG_OFFSET_MASK);
|
||||
}
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"PHY_LCK finish delay for %d ms=2\n", timecount);
|
||||
u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
|
||||
u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
|
||||
if (index == 0 && rtlhal->interfaceindex == 0) {
|
||||
RTPRINT(rtlpriv, FINIT, INIT_IQK,
|
||||
"path-A / 5G LCK\n");
|
||||
@@ -2696,9 +2637,9 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
|
||||
0x7f, i);
|
||||
|
||||
rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
|
||||
BRFREGOFFSETMASK, 0x0);
|
||||
RFREG_OFFSET_MASK, 0x0);
|
||||
readval = rtl_get_rfreg(hw, (enum radio_path)index,
|
||||
0x4F, BRFREGOFFSETMASK);
|
||||
0x4F, RFREG_OFFSET_MASK);
|
||||
curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
|
||||
/* reg 0x4f [4:0] */
|
||||
/* reg 0x50 [19:10] */
|
||||
@@ -2912,7 +2853,7 @@ static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
|
||||
}
|
||||
rtl_set_rfreg(hw, (enum radio_path)rfpath,
|
||||
currentcmd->para1,
|
||||
BRFREGOFFSETMASK,
|
||||
RFREG_OFFSET_MASK,
|
||||
rtlphy->rfreg_chnlval[rfpath]);
|
||||
_rtl92d_phy_reload_imr_setting(hw, channel,
|
||||
rfpath);
|
||||
@@ -2960,7 +2901,7 @@ u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
|
||||
if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
|
||||
rtlhal->bandset == BAND_ON_BOTH) {
|
||||
ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
|
||||
BMASKDWORD);
|
||||
MASKDWORD);
|
||||
if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
|
||||
rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
|
||||
else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
|
||||
@@ -3112,7 +3053,7 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
|
||||
/* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
|
||||
rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
|
||||
/* b. RF path 0 offset 0x00 = 0x00 disable RF */
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
|
||||
/* c. APSD_CTRL 0x600[7:0] = 0x40 */
|
||||
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
|
||||
/* d. APSD_CTRL 0x600[7:0] = 0x00
|
||||
@@ -3120,12 +3061,12 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
|
||||
* RF path 0 offset 0x00 = 0x00
|
||||
* APSD_CTRL 0x600[7:0] = 0x40
|
||||
* */
|
||||
u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
|
||||
u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
|
||||
while (u4btmp != 0 && delay > 0) {
|
||||
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
|
||||
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
|
||||
u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
|
||||
u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
|
||||
delay--;
|
||||
}
|
||||
if (delay == 0) {
|
||||
@@ -3468,9 +3409,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
/* 5G LAN ON */
|
||||
rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
|
||||
/* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
|
||||
0x40000100);
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
|
||||
0x40000100);
|
||||
if (rtlhal->macphymode == DUALMAC_DUALPHY) {
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
|
||||
@@ -3524,16 +3465,16 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
|
||||
/* TX BB gain shift,Just for testchip,0xc80,0xc88 */
|
||||
if (rtlefuse->internal_pa_5g[0])
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
|
||||
0x2d4000b5);
|
||||
else
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
|
||||
0x20000080);
|
||||
if (rtlefuse->internal_pa_5g[1])
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
|
||||
0x2d4000b5);
|
||||
else
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
|
||||
rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
|
||||
0x20000080);
|
||||
if (rtlhal->macphymode == DUALMAC_DUALPHY) {
|
||||
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
|
||||
@@ -3560,8 +3501,8 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
}
|
||||
}
|
||||
/* update IQK related settings */
|
||||
rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
|
||||
rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
|
||||
rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
|
||||
rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
|
||||
rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
|
||||
rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
|
||||
BIT(26) | BIT(24), 0x00);
|
||||
@@ -3590,7 +3531,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
/* DMDP */
|
||||
if (rtlphy->rf_type == RF_1T1R) {
|
||||
/* Use antenna 0,0xc04,0xd04 */
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
|
||||
rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
|
||||
|
||||
/* enable ad/da clock1 for dual-phy reg0x888 */
|
||||
@@ -3612,7 +3553,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
} else {
|
||||
/* Single PHY */
|
||||
/* Use antenna 0 & 1,0xc04,0xd04 */
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
|
||||
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
|
||||
rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
|
||||
/* disable ad/da clock1,0x888 */
|
||||
rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
|
||||
@@ -3620,9 +3561,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
|
||||
for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
|
||||
rfpath++) {
|
||||
rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
|
||||
RF_CHNLBW, BRFREGOFFSETMASK);
|
||||
RF_CHNLBW, RFREG_OFFSET_MASK);
|
||||
rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
|
||||
BRFREGOFFSETMASK);
|
||||
RFREG_OFFSET_MASK);
|
||||
}
|
||||
for (i = 0; i < 2; i++)
|
||||
RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
|
||||
|
||||
Reference in New Issue
Block a user