drm/radeon/kms: add support for interrupts on SI
This is mostly identical to evergreen/ni, however there are some additional fields in the IV vector for RINGID and VMID. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
committed by
Dave Airlie
Dave Airlie
parent
347e7592be
commit
25a857fbe9
@@ -55,6 +55,8 @@ MODULE_FIRMWARE("radeon/VERDE_ce.bin");
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MODULE_FIRMWARE("radeon/VERDE_mc.bin");
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MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
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extern int r600_ih_ring_alloc(struct radeon_device *rdev);
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extern void r600_ih_ring_fini(struct radeon_device *rdev);
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extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
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extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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@@ -3072,3 +3074,722 @@ static int si_rlc_resume(struct radeon_device *rdev)
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return 0;
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}
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static void si_enable_interrupts(struct radeon_device *rdev)
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{
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u32 ih_cntl = RREG32(IH_CNTL);
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u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
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ih_cntl |= ENABLE_INTR;
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ih_rb_cntl |= IH_RB_ENABLE;
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WREG32(IH_CNTL, ih_cntl);
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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rdev->ih.enabled = true;
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}
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static void si_disable_interrupts(struct radeon_device *rdev)
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{
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u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
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u32 ih_cntl = RREG32(IH_CNTL);
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ih_rb_cntl &= ~IH_RB_ENABLE;
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ih_cntl &= ~ENABLE_INTR;
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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WREG32(IH_CNTL, ih_cntl);
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/* set rptr, wptr to 0 */
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WREG32(IH_RB_RPTR, 0);
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WREG32(IH_RB_WPTR, 0);
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rdev->ih.enabled = false;
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rdev->ih.wptr = 0;
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rdev->ih.rptr = 0;
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}
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static void si_disable_interrupt_state(struct radeon_device *rdev)
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{
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u32 tmp;
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WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING1, 0);
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WREG32(CP_INT_CNTL_RING2, 0);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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if (rdev->num_crtc >= 4) {
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WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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if (rdev->num_crtc >= 4) {
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
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tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD1_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD2_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD3_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD4_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD5_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD6_INT_CONTROL, tmp);
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}
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static int si_irq_init(struct radeon_device *rdev)
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{
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int ret = 0;
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int rb_bufsz;
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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/* allocate ring */
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ret = r600_ih_ring_alloc(rdev);
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if (ret)
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return ret;
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/* disable irqs */
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si_disable_interrupts(rdev);
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/* init rlc */
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ret = si_rlc_resume(rdev);
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if (ret) {
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r600_ih_ring_fini(rdev);
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return ret;
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}
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/* setup interrupt control */
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/* set dummy read address to ring address */
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WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
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interrupt_cntl = RREG32(INTERRUPT_CNTL);
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/* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
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* IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
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/* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
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WREG32(INTERRUPT_CNTL, interrupt_cntl);
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WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
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rb_bufsz = drm_order(rdev->ih.ring_size / 4);
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ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
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IH_WPTR_OVERFLOW_CLEAR |
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(rb_bufsz << 1));
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if (rdev->wb.enabled)
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ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
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/* set the writeback address whether it's enabled or not */
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WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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/* set rptr, wptr to 0 */
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WREG32(IH_RB_RPTR, 0);
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WREG32(IH_RB_WPTR, 0);
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/* Default settings for IH_CNTL (disabled at first) */
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ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
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/* RPTR_REARM only works if msi's are enabled */
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if (rdev->msi_enabled)
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ih_cntl |= RPTR_REARM;
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WREG32(IH_CNTL, ih_cntl);
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/* force the active interrupt state to all disabled */
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si_disable_interrupt_state(rdev);
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/* enable irqs */
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si_enable_interrupts(rdev);
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return ret;
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}
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int si_irq_set(struct radeon_device *rdev)
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{
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u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
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u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
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u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
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u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
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u32 grbm_int_cntl = 0;
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u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
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if (!rdev->irq.installed) {
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WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
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return -EINVAL;
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}
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/* don't enable anything if the ih is disabled */
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if (!rdev->ih.enabled) {
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si_disable_interrupts(rdev);
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/* force the active interrupt state to all disabled */
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si_disable_interrupt_state(rdev);
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return 0;
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}
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hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
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/* enable CP interrupts on all rings */
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if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
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DRM_DEBUG("si_irq_set: sw int gfx\n");
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cp_int_cntl |= TIME_STAMP_INT_ENABLE;
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}
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if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
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DRM_DEBUG("si_irq_set: sw int cp1\n");
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cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
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}
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if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
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DRM_DEBUG("si_irq_set: sw int cp2\n");
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cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
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}
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if (rdev->irq.crtc_vblank_int[0] ||
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rdev->irq.pflip[0]) {
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DRM_DEBUG("si_irq_set: vblank 0\n");
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crtc1 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[1] ||
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rdev->irq.pflip[1]) {
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DRM_DEBUG("si_irq_set: vblank 1\n");
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crtc2 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[2] ||
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rdev->irq.pflip[2]) {
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DRM_DEBUG("si_irq_set: vblank 2\n");
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crtc3 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[3] ||
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rdev->irq.pflip[3]) {
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DRM_DEBUG("si_irq_set: vblank 3\n");
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crtc4 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[4] ||
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rdev->irq.pflip[4]) {
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DRM_DEBUG("si_irq_set: vblank 4\n");
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crtc5 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[5] ||
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rdev->irq.pflip[5]) {
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DRM_DEBUG("si_irq_set: vblank 5\n");
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crtc6 |= VBLANK_INT_MASK;
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}
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if (rdev->irq.hpd[0]) {
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DRM_DEBUG("si_irq_set: hpd 1\n");
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hpd1 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[1]) {
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DRM_DEBUG("si_irq_set: hpd 2\n");
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hpd2 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[2]) {
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DRM_DEBUG("si_irq_set: hpd 3\n");
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hpd3 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[3]) {
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DRM_DEBUG("si_irq_set: hpd 4\n");
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hpd4 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[4]) {
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DRM_DEBUG("si_irq_set: hpd 5\n");
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hpd5 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[5]) {
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DRM_DEBUG("si_irq_set: hpd 6\n");
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hpd6 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.gui_idle) {
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DRM_DEBUG("gui idle\n");
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grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
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}
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WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
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WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
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WREG32(GRBM_INT_CNTL, grbm_int_cntl);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
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WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
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if (rdev->num_crtc >= 4) {
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WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
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WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
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WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
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}
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
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if (rdev->num_crtc >= 4) {
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
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}
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WREG32(DC_HPD1_INT_CONTROL, hpd1);
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WREG32(DC_HPD2_INT_CONTROL, hpd2);
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WREG32(DC_HPD3_INT_CONTROL, hpd3);
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WREG32(DC_HPD4_INT_CONTROL, hpd4);
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WREG32(DC_HPD5_INT_CONTROL, hpd5);
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WREG32(DC_HPD6_INT_CONTROL, hpd6);
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return 0;
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}
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static inline void si_irq_ack(struct radeon_device *rdev)
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{
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u32 tmp;
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rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
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rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
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rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
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rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
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rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
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rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
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rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
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rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
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if (rdev->num_crtc >= 4) {
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rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
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rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
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}
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if (rdev->num_crtc >= 6) {
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rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
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rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
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}
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if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
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WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
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if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
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WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
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if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
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WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
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if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
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WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
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if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
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WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
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if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
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WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
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if (rdev->num_crtc >= 4) {
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if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
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WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
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if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
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WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
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if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
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WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
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if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
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||||
WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
|
||||
WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
|
||||
WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
|
||||
}
|
||||
|
||||
if (rdev->num_crtc >= 6) {
|
||||
if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
|
||||
WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
|
||||
WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
|
||||
WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
|
||||
WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
|
||||
}
|
||||
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD1_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD1_INT_CONTROL, tmp);
|
||||
}
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD2_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD2_INT_CONTROL, tmp);
|
||||
}
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD3_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD3_INT_CONTROL, tmp);
|
||||
}
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD4_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD4_INT_CONTROL, tmp);
|
||||
}
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD5_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD5_INT_CONTROL, tmp);
|
||||
}
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD5_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD6_INT_CONTROL, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
static void si_irq_disable(struct radeon_device *rdev)
|
||||
{
|
||||
si_disable_interrupts(rdev);
|
||||
/* Wait and acknowledge irq */
|
||||
mdelay(1);
|
||||
si_irq_ack(rdev);
|
||||
si_disable_interrupt_state(rdev);
|
||||
}
|
||||
|
||||
static void si_irq_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
si_irq_disable(rdev);
|
||||
si_rlc_stop(rdev);
|
||||
}
|
||||
|
||||
static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
|
||||
{
|
||||
u32 wptr, tmp;
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
|
||||
else
|
||||
wptr = RREG32(IH_RB_WPTR);
|
||||
|
||||
if (wptr & RB_OVERFLOW) {
|
||||
/* When a ring buffer overflow happen start parsing interrupt
|
||||
* from the last not overwritten vector (wptr + 16). Hopefully
|
||||
* this should allow us to catchup.
|
||||
*/
|
||||
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
|
||||
wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
|
||||
rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
|
||||
tmp = RREG32(IH_RB_CNTL);
|
||||
tmp |= IH_WPTR_OVERFLOW_CLEAR;
|
||||
WREG32(IH_RB_CNTL, tmp);
|
||||
}
|
||||
return (wptr & rdev->ih.ptr_mask);
|
||||
}
|
||||
|
||||
/* SI IV Ring
|
||||
* Each IV ring entry is 128 bits:
|
||||
* [7:0] - interrupt source id
|
||||
* [31:8] - reserved
|
||||
* [59:32] - interrupt source data
|
||||
* [63:60] - reserved
|
||||
* [71:64] - RINGID
|
||||
* [79:72] - VMID
|
||||
* [127:80] - reserved
|
||||
*/
|
||||
int si_irq_process(struct radeon_device *rdev)
|
||||
{
|
||||
u32 wptr;
|
||||
u32 rptr;
|
||||
u32 src_id, src_data, ring_id;
|
||||
u32 ring_index;
|
||||
unsigned long flags;
|
||||
bool queue_hotplug = false;
|
||||
|
||||
if (!rdev->ih.enabled || rdev->shutdown)
|
||||
return IRQ_NONE;
|
||||
|
||||
wptr = si_get_ih_wptr(rdev);
|
||||
rptr = rdev->ih.rptr;
|
||||
DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
|
||||
|
||||
spin_lock_irqsave(&rdev->ih.lock, flags);
|
||||
if (rptr == wptr) {
|
||||
spin_unlock_irqrestore(&rdev->ih.lock, flags);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
restart_ih:
|
||||
/* Order reading of wptr vs. reading of IH ring data */
|
||||
rmb();
|
||||
|
||||
/* display interrupts */
|
||||
si_irq_ack(rdev);
|
||||
|
||||
rdev->ih.wptr = wptr;
|
||||
while (rptr != wptr) {
|
||||
/* wptr/rptr are in bytes! */
|
||||
ring_index = rptr / 4;
|
||||
src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
|
||||
src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
|
||||
ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
|
||||
|
||||
switch (src_id) {
|
||||
case 1: /* D1 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D1 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[0]) {
|
||||
drm_handle_vblank(rdev->ddev, 0);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[0])
|
||||
radeon_crtc_handle_flip(rdev, 0);
|
||||
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D1 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D1 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D1 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* D2 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D2 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[1]) {
|
||||
drm_handle_vblank(rdev->ddev, 1);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[1])
|
||||
radeon_crtc_handle_flip(rdev, 1);
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D2 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D2 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D2 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 3: /* D3 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D3 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[2]) {
|
||||
drm_handle_vblank(rdev->ddev, 2);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[2])
|
||||
radeon_crtc_handle_flip(rdev, 2);
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D3 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D3 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D3 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 4: /* D4 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D4 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[3]) {
|
||||
drm_handle_vblank(rdev->ddev, 3);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[3])
|
||||
radeon_crtc_handle_flip(rdev, 3);
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D4 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D4 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D4 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 5: /* D5 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D5 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[4]) {
|
||||
drm_handle_vblank(rdev->ddev, 4);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[4])
|
||||
radeon_crtc_handle_flip(rdev, 4);
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D5 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D5 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D5 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 6: /* D6 vblank/vline */
|
||||
switch (src_data) {
|
||||
case 0: /* D6 vblank */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
|
||||
if (rdev->irq.crtc_vblank_int[5]) {
|
||||
drm_handle_vblank(rdev->ddev, 5);
|
||||
rdev->pm.vblank_sync = true;
|
||||
wake_up(&rdev->irq.vblank_queue);
|
||||
}
|
||||
if (rdev->irq.pflip[5])
|
||||
radeon_crtc_handle_flip(rdev, 5);
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
|
||||
DRM_DEBUG("IH: D6 vblank\n");
|
||||
}
|
||||
break;
|
||||
case 1: /* D6 vline */
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
|
||||
DRM_DEBUG("IH: D6 vline\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 42: /* HPD hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD1\n");
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD2\n");
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD3\n");
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD4\n");
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD5\n");
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
|
||||
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
|
||||
queue_hotplug = true;
|
||||
DRM_DEBUG("IH: HPD6\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 176: /* RINGID0 CP_INT */
|
||||
radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
||||
break;
|
||||
case 177: /* RINGID1 CP_INT */
|
||||
radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
|
||||
break;
|
||||
case 178: /* RINGID2 CP_INT */
|
||||
radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
|
||||
break;
|
||||
case 181: /* CP EOP event */
|
||||
DRM_DEBUG("IH: CP EOP\n");
|
||||
switch (ring_id) {
|
||||
case 0:
|
||||
radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
||||
break;
|
||||
case 1:
|
||||
radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
|
||||
break;
|
||||
case 2:
|
||||
radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 233: /* GUI IDLE */
|
||||
DRM_DEBUG("IH: GUI idle\n");
|
||||
rdev->pm.gui_idle = true;
|
||||
wake_up(&rdev->irq.idle_queue);
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
|
||||
/* wptr/rptr are in bytes! */
|
||||
rptr += 16;
|
||||
rptr &= rdev->ih.ptr_mask;
|
||||
}
|
||||
/* make sure wptr hasn't changed while processing */
|
||||
wptr = si_get_ih_wptr(rdev);
|
||||
if (wptr != rdev->ih.wptr)
|
||||
goto restart_ih;
|
||||
if (queue_hotplug)
|
||||
schedule_work(&rdev->hotplug_work);
|
||||
rdev->ih.rptr = rptr;
|
||||
WREG32(IH_RB_RPTR, rdev->ih.rptr);
|
||||
spin_unlock_irqrestore(&rdev->ih.lock, flags);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user