sh: clkfwk: Rework legacy CPG clock handling.
This moves out the old legacy CPG clocks to their own file, and converts over the existing users. With these clocks going away and each CPU dealing with them on their own, CPUs can gradually move over to the new interface. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
@@ -17,5 +17,6 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
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obj-$(CONFIG_UBC_WAKEUP) += ubc.o
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obj-$(CONFIG_SH_ADC) += adc.o
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obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
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obj-y += irq/ init.o clock.o
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60
arch/sh/kernel/cpu/clock-cpg.c
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60
arch/sh/kernel/cpu/clock-cpg.c
Normal file
@@ -0,0 +1,60 @@
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <asm/clock.h>
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static struct clk master_clk = {
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.name = "master_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.rate = CONFIG_SH_PCLK_FREQ,
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};
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static struct clk peripheral_clk = {
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.name = "peripheral_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk bus_clk = {
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.name = "bus_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk cpu_clk = {
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.name = "cpu_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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/*
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* The ordering of these clocks matters, do not change it.
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*/
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static struct clk *onchip_clocks[] = {
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&master_clk,
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&peripheral_clk,
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&bus_clk,
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&cpu_clk,
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};
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int __init __deprecated cpg_clk_init(void)
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{
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
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struct clk *clk = onchip_clocks[i];
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arch_init_clk_ops(&clk->ops, i);
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if (clk->ops)
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ret |= clk_register(clk);
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}
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return ret;
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}
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/*
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* Placeholder for compatability, until the lazy CPUs do this
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* on their own.
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*/
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int __init __weak arch_clk_init(void)
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{
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return cpg_clk_init();
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}
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@@ -30,54 +30,12 @@
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#include <linux/platform_device.h>
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#include <linux/proc_fs.h>
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#include <asm/clock.h>
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#include <asm/machvec.h>
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static LIST_HEAD(clock_list);
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static DEFINE_SPINLOCK(clock_lock);
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static DEFINE_MUTEX(clock_list_sem);
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/*
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* Each subtype is expected to define the init routines for these clocks,
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* as each subtype (or processor family) will have these clocks at the
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* very least. These are all provided through the CPG, which even some of
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* the more quirky parts (such as ST40, SH4-202, etc.) still have.
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*
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* The processor-specific code is expected to register any additional
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* clock sources that are of interest.
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*/
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static struct clk master_clk = {
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.name = "master_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.rate = CONFIG_SH_PCLK_FREQ,
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};
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static struct clk peripheral_clk = {
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.name = "peripheral_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk bus_clk = {
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.name = "bus_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk cpu_clk = {
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.name = "cpu_clk",
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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/*
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* The ordering of these clocks matters, do not change it.
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*/
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static struct clk *onchip_clocks[] = {
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&master_clk,
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&peripheral_clk,
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&bus_clk,
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&cpu_clk,
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};
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/* Used for clocks that always have same value as the parent clock */
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unsigned long followparent_recalc(struct clk *clk)
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{
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@@ -443,10 +401,6 @@ void clk_put(struct clk *clk)
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}
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EXPORT_SYMBOL_GPL(clk_put);
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int __init __weak arch_clk_init(void)
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{
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return 0;
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}
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static int show_clocks(char *buf, char **start, off_t off,
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int len, int *eof, void *data)
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@@ -533,18 +487,22 @@ subsys_initcall(clk_sysdev_init);
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int __init clk_init(void)
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{
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int i, ret = 0;
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int ret;
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BUG_ON(!master_clk.rate);
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for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
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struct clk *clk = onchip_clocks[i];
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arch_init_clk_ops(&clk->ops, i);
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ret |= clk_register(clk);
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ret = arch_clk_init();
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if (unlikely(ret)) {
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pr_err("%s: CPU clock registration failed.\n", __func__);
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return ret;
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}
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ret |= arch_clk_init();
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if (sh_mv.mv_clk_init) {
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ret = sh_mv.mv_clk_init();
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if (unlikely(ret)) {
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pr_err("%s: machvec clock initialization failed.\n",
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__func__);
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return ret;
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}
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}
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/* Kick the child clocks.. */
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recalculate_root_clocks();
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@@ -152,9 +152,12 @@ static struct clk *sh4202_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
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struct clk *clkp = sh4202_onchip_clocks[i];
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@@ -892,6 +892,8 @@ int __init arch_clk_init(void)
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struct clk *clk;
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int i;
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clk_cpg_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
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pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
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@@ -92,9 +92,12 @@ static struct clk *sh7763_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
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struct clk *clkp = sh7763_onchip_clocks[i];
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@@ -98,9 +98,12 @@ static struct clk *sh7780_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
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struct clk *clkp = sh7780_onchip_clocks[i];
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@@ -136,9 +136,12 @@ static struct clk *sh7785_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
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struct clk *clkp = sh7785_onchip_clocks[i];
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@@ -122,9 +122,12 @@ static struct clk *sh7786_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
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struct clk *clkp = sh7786_onchip_clocks[i];
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@@ -109,9 +109,12 @@ static struct clk *shx3_onchip_clocks[] = {
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int __init arch_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
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struct clk *clkp = shx3_onchip_clocks[i];
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