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Merge ../linux-2.6

Forráskód böngészése
This commit is contained in:
Paul Mackerras
2005-11-08 11:14:20 +11:00
szülő c613523455 3f00d3e8fb
commit 24bfb00123
1265 fájl változott, egészen pontosan 41019 új sor hozzáadva és 20203 régi sor törölve
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4
arch/ppc/syslib/Makefile
Fájl megtekintése

@@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common.o
obj-$(CONFIG_440GP) += ibm440gp_common.o
obj-$(CONFIG_440GX) += ibm440gx_common.o
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
ifeq ($(CONFIG_4xx),y)
ifeq ($(CONFIG_VIRTEX_II_PRO),y)
obj-$(CONFIG_40x) += xilinx_pic.o
@@ -32,6 +33,7 @@ obj-$(CONFIG_PPC4xx_DMA) += ppc4xx_dma.o
obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o
ifeq ($(CONFIG_40x),y)
obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o
obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
endif
endif
obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
@@ -46,12 +48,14 @@ obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
obj-$(CONFIG_EV64360) += todc_time.o
obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o
obj-$(CONFIG_GEMINI) += open_pic.o
obj-$(CONFIG_GT64260) += gt64260_pic.o
obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o
obj-$(CONFIG_HDPU) += pci_auto.o
obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o
obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o
obj-$(CONFIG_KATANA) += pci_auto.o
obj-$(CONFIG_MV64360) += mv64360_pic.o
obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o

4
arch/ppc/syslib/ibm440sp_common.c
Fájl megtekintése

@@ -1,7 +1,7 @@
/*
* arch/ppc/syslib/ibm440sp_common.c
*
* PPC440SP system library
* PPC440SP/PPC440SPe system library
*
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
@@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_of_memory(void)
u32 mem_size = 0;
/* Read two bank sizes and sum */
for (i=0; i<2; i++)
for (i=0; i< MQ0_NUM_BANKS; i++)
switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) {
case MQ0_CONFIG_SIZE_8M:
mem_size += PPC44x_MEM_SIZE_8M;

12
arch/ppc/syslib/ibm44x_common.c
Fájl megtekintése

@@ -20,6 +20,7 @@
#include <linux/types.h>
#include <linux/serial.h>
#include <linux/module.h>
#include <linux/initrd.h>
#include <asm/ibm44x.h>
#include <asm/mmu.h>
@@ -214,9 +215,20 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo
/* Called from machine_check_exception */
void platform_machine_check(struct pt_regs *regs)
{
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
mfdcr(DCRN_PLB0_BESRL));
printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
mfdcr(DCRN_PLB1_BESRL));
#else
printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
#endif
printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));

7
arch/ppc/syslib/ppc405_pci.c
Fájl megtekintése

@@ -89,13 +89,6 @@ ppc4xx_find_bridges(void)
isa_mem_base = 0;
pci_dram_offset = 0;
#if (PSR_PCI_ARBIT_EN > 1)
/* Check if running in slave mode */
if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
printk("Running as PCI slave, kernel PCI disabled !\n");
return;
}
#endif
/* Setup PCI32 hose */
hose_a = pcibios_alloc_controller();
if (!hose_a)

442
arch/ppc/syslib/ppc440spe_pcie.c Normal file
Fájl megtekintése

@@ -0,0 +1,442 @@
/*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/reg.h>
#include <asm/io.h>
#include <asm/ibm44x.h>
#include "ppc440spe_pcie.h"
static int
pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
struct pci_controller *hose = bus->sysdata;
if (PCI_SLOT(devfn) != 1)
return PCIBIOS_DEVICE_NOT_FOUND;
offset += devfn << 12;
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
break;
case 2:
*val = in_le16(hose->cfg_data + offset);
break;
default:
*val = in_le32(hose->cfg_data + offset);
break;
}
if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
return PCIBIOS_SUCCESSFUL;
}
static int
pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
struct pci_controller *hose = bus->sysdata;
if (PCI_SLOT(devfn) != 1)
return PCIBIOS_DEVICE_NOT_FOUND;
offset += devfn << 12;
switch (len) {
case 1:
out_8(hose->cfg_data + offset, val);
break;
case 2:
out_le16(hose->cfg_data + offset, val);
break;
default:
out_le32(hose->cfg_data + offset, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pcie_pci_ops =
{
.read = pcie_read_config,
.write = pcie_write_config
};
enum {
PTYPE_ENDPOINT = 0x0,
PTYPE_LEGACY_ENDPOINT = 0x1,
PTYPE_ROOT_PORT = 0x4,
LNKW_X1 = 0x1,
LNKW_X4 = 0x4,
LNKW_X8 = 0x8
};
static void check_error(void)
{
u32 valPE0, valPE1, valPE2;
/* SDR0_PEGPLLLCT1 reset */
if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0);
}
valPE0 = SDR_READ(PESDR0_RCSSET);
valPE1 = SDR_READ(PESDR1_RCSSET);
valPE2 = SDR_READ(PESDR2_RCSSET);
/* SDR0_PExRCSSET rstgu */
if ( !(valPE0 & 0x01000000) ||
!(valPE1 & 0x01000000) ||
!(valPE2 & 0x01000000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
}
/* SDR0_PExRCSSET rstdl */
if ( !(valPE0 & 0x00010000) ||
!(valPE1 & 0x00010000) ||
!(valPE2 & 0x00010000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
}
/* SDR0_PExRCSSET rstpyn */
if ( (valPE0 & 0x00001000) ||
(valPE1 & 0x00001000) ||
(valPE2 & 0x00001000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
}
/* SDR0_PExRCSSET hldplb */
if ( (valPE0 & 0x10000000) ||
(valPE1 & 0x10000000) ||
(valPE2 & 0x10000000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
}
/* SDR0_PExRCSSET rdy */
if ( (valPE0 & 0x00100000) ||
(valPE1 & 0x00100000) ||
(valPE2 & 0x00100000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
}
/* SDR0_PExRCSSET shutdown */
if ( (valPE0 & 0x00000100) ||
(valPE1 & 0x00000100) ||
(valPE2 & 0x00000100)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
}
}
/*
* Initialize PCI Express core as described in User Manual section 27.12.1
*/
int ppc440spe_init_pcie(void)
{
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
check_error();
printk(KERN_INFO "PCIE initialization OK\n");
if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
SDR_READ(PESDR0_PLLLCT2));
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
return 0;
}
int ppc440spe_init_pcie_rootport(int port)
{
static int core_init;
void __iomem *utl_base;
u32 val = 0;
int i;
if (!core_init) {
++core_init;
i = ppc440spe_init_pcie();
if (i)
return i;
}
/*
* Initialize various parts of the PCI Express core for our port:
*
* - Set as a root port and enable max width
* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
* - Set up UTL configuration.
* - Increase SERDES drive strength to levels suggested by AMCC.
* - De-assert RSTPYN, RSTDL and RSTGU.
*/
switch (port) {
case 0:
SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
SDR_WRITE(PESDR0_RCSSET,
(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 1:
SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR1_RCSSET,
(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 2:
SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR2_RCSSET,
(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
}
mdelay(1000);
switch (port) {
case 0: val = SDR_READ(PESDR0_RCSSTS); break;
case 1: val = SDR_READ(PESDR1_RCSSTS); break;
case 2: val = SDR_READ(PESDR2_RCSSTS); break;
}
if (!(val & (1 << 20)))
printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
else
printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
switch (port) {
case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
}
/*
* Map UTL registers at 0xc_1000_0n00
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
break;
case 2:
mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
}
utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
/*
* Set buffer allocations and then assert VRB and TXE.
*/
out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
out_be32(utl_base + PEUTL_INTR, 0x02000000);
out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
out_be32(utl_base + PEUTL_PCTL, 0x80800066);
iounmap(utl_base);
/*
* We map PCI Express configuration access into the 512MB regions
* PCIE0: 0xc_4000_0000
* PCIE1: 0xc_8000_0000
* PCIE2: 0xc_c000_0000
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
break;
case 1:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
case 2:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
break;
}
/*
* Check for VC0 active and assert RDY.
*/
switch (port) {
case 0:
if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
break;
case 1:
if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
break;
case 2:
if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
break;
}
#if 0
/* Dump all config regs */
for (i = 0x300; i <= 0x320; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x340; i <= 0x353; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x370; i <= 0x383; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x3a0; i <= 0x3a2; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x3c0; i <= 0x3c3; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
#endif
mdelay(100);
return 0;
}
void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
{
void __iomem *mbase;
/*
* Map 16MB, which is enough for 4 bits of bus #
*/
hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000,
1 << 24);
hose->ops = &pcie_pci_ops;
/*
* Set bus numbers on our root port
*/
mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096);
out_8(mbase + PCI_PRIMARY_BUS, 0);
out_8(mbase + PCI_SECONDARY_BUS, 0);
/*
* Set up outbound translation to hose->mem_space from PLB
* addresses at an offset of 0xd_0000_0000. We set the low
* bits of the mask to 11 to turn off splitting into 8
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0);
out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start);
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(hose->mem_space.end - hose->mem_space.start) | 3);
break;
case 1:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(hose->mem_space.end - hose->mem_space.start) | 3);
break;
case 2:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(hose->mem_space.end - hose->mem_space.start) | 3);
break;
}
/* Set up 16GB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0LMPA, 0);
out_le32(mbase + PECFG_PIM0LAL, 0);
out_le32(mbase + PECFG_PIM0LAH, 0);
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16(mbase + PCI_COMMAND,
in_le16(mbase + PCI_COMMAND) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
iounmap(mbase);
}

149
arch/ppc/syslib/ppc440spe_pcie.h Normal file
Fájl megtekintése

@@ -0,0 +1,149 @@
/*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H
#define __PPC_SYSLIB_PPC440SPE_PCIE_H
#define DCRN_SDR0_CFGADDR 0x00e
#define DCRN_SDR0_CFGDATA 0x00f
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define DCRN_PCIE2_BASE 0x140
#define PCIE0 DCRN_PCIE0_BASE
#define PCIE1 DCRN_PCIE1_BASE
#define PCIE2 DCRN_PCIE2_BASE
#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
/*
* System DCRs (SDRs)
*/
#define PESDR0_PLLLCT1 0x03a0
#define PESDR0_PLLLCT2 0x03a1
#define PESDR0_PLLLCT3 0x03a2
#define PESDR0_UTLSET1 0x0300
#define PESDR0_UTLSET2 0x0301
#define PESDR0_DLPSET 0x0302
#define PESDR0_LOOP 0x0303
#define PESDR0_RCSSET 0x0304
#define PESDR0_RCSSTS 0x0305
#define PESDR0_HSSL0SET1 0x0306
#define PESDR0_HSSL0SET2 0x0307
#define PESDR0_HSSL0STS 0x0308
#define PESDR0_HSSL1SET1 0x0309
#define PESDR0_HSSL1SET2 0x030a
#define PESDR0_HSSL1STS 0x030b
#define PESDR0_HSSL2SET1 0x030c
#define PESDR0_HSSL2SET2 0x030d
#define PESDR0_HSSL2STS 0x030e
#define PESDR0_HSSL3SET1 0x030f
#define PESDR0_HSSL3SET2 0x0310
#define PESDR0_HSSL3STS 0x0311
#define PESDR0_HSSL4SET1 0x0312
#define PESDR0_HSSL4SET2 0x0313
#define PESDR0_HSSL4STS 0x0314
#define PESDR0_HSSL5SET1 0x0315
#define PESDR0_HSSL5SET2 0x0316
#define PESDR0_HSSL5STS 0x0317
#define PESDR0_HSSL6SET1 0x0318
#define PESDR0_HSSL6SET2 0x0319
#define PESDR0_HSSL6STS 0x031a
#define PESDR0_HSSL7SET1 0x031b
#define PESDR0_HSSL7SET2 0x031c
#define PESDR0_HSSL7STS 0x031d
#define PESDR0_HSSCTLSET 0x031e
#define PESDR0_LANE_ABCD 0x031f
#define PESDR0_LANE_EFGH 0x0320
#define PESDR1_UTLSET1 0x0340
#define PESDR1_UTLSET2 0x0341
#define PESDR1_DLPSET 0x0342
#define PESDR1_LOOP 0x0343
#define PESDR1_RCSSET 0x0344
#define PESDR1_RCSSTS 0x0345
#define PESDR1_HSSL0SET1 0x0346
#define PESDR1_HSSL0SET2 0x0347
#define PESDR1_HSSL0STS 0x0348
#define PESDR1_HSSL1SET1 0x0349
#define PESDR1_HSSL1SET2 0x034a
#define PESDR1_HSSL1STS 0x034b
#define PESDR1_HSSL2SET1 0x034c
#define PESDR1_HSSL2SET2 0x034d
#define PESDR1_HSSL2STS 0x034e
#define PESDR1_HSSL3SET1 0x034f
#define PESDR1_HSSL3SET2 0x0350
#define PESDR1_HSSL3STS 0x0351
#define PESDR1_HSSCTLSET 0x0352
#define PESDR1_LANE_ABCD 0x0353
#define PESDR2_UTLSET1 0x0370
#define PESDR2_UTLSET2 0x0371
#define PESDR2_DLPSET 0x0372
#define PESDR2_LOOP 0x0373
#define PESDR2_RCSSET 0x0374
#define PESDR2_RCSSTS 0x0375
#define PESDR2_HSSL0SET1 0x0376
#define PESDR2_HSSL0SET2 0x0377
#define PESDR2_HSSL0STS 0x0378
#define PESDR2_HSSL1SET1 0x0379
#define PESDR2_HSSL1SET2 0x037a
#define PESDR2_HSSL1STS 0x037b
#define PESDR2_HSSL2SET1 0x037c
#define PESDR2_HSSL2SET2 0x037d
#define PESDR2_HSSL2STS 0x037e
#define PESDR2_HSSL3SET1 0x037f
#define PESDR2_HSSL3SET2 0x0380
#define PESDR2_HSSL3STS 0x0381
#define PESDR2_HSSCTLSET 0x0382
#define PESDR2_LANE_ABCD 0x0383
/*
* UTL register offsets
*/
#define PEUTL_PBBSZ 0x20
#define PEUTL_OPDBSZ 0x68
#define PEUTL_IPHBSZ 0x70
#define PEUTL_IPDBSZ 0x78
#define PEUTL_OUTTR 0x90
#define PEUTL_INTR 0x98
#define PEUTL_PCTL 0xa0
#define PEUTL_RCIRQEN 0xb8
/*
* Config space register offsets
*/
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
#define PECFG_POM0LAL 0x380
#define PECFG_POM0LAH 0x384
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */

37
arch/ppc/syslib/ppc4xx_pic.c
Fájl megtekintése

@@ -38,6 +38,7 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq)
#define UIC_HANDLERS(n) \
static void ppc4xx_uic##n##_enable(unsigned int irq) \
@@ -88,7 +89,38 @@ static void ppc4xx_uic##n##_end(unsigned int irq) \
.end = ppc4xx_uic##n##_end, \
} \
#if NR_UICS == 3
#if NR_UICS == 4
#define ACK_UIC0_PARENT
#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
UIC_HANDLERS(0);
UIC_HANDLERS(1);
UIC_HANDLERS(2);
UIC_HANDLERS(3);
static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
if (uic0 & UIC0_UIC1NC)
return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
else if (uic0 & UIC0_UIC2NC)
return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
else if (uic0 & UIC0_UIC3NC)
return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3)));
else
return uic0 ? 32 - ffs(uic0) : -1;
}
static void __init ppc4xx_pic_impl_init(void)
{
/* Enable cascade interrupts in UIC0 */
ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
}
#elif NR_UICS == 3
#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -170,6 +202,9 @@ static struct ppc4xx_uic_impl {
{ .decl = DECLARE_UIC(1), .base = UIC1 },
#if NR_UICS > 2
{ .decl = DECLARE_UIC(2), .base = UIC2 },
#if NR_UICS > 3
{ .decl = DECLARE_UIC(3), .base = UIC3 },
#endif
#endif
#endif
};

938
arch/ppc/syslib/ppc85xx_rio.c Normal file
Fájl megtekintése

@@ -0,0 +1,938 @@
/*
* MPC85xx RapidIO support
*
* Copyright 2005 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <asm/io.h>
#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
#define RIO_ATMU_REGS_OFFSET 0x10c00
#define RIO_MSG_REGS_OFFSET 0x11000
#define RIO_MAINT_WIN_SIZE 0x400000
#define RIO_DBELL_WIN_SIZE 0x1000
#define RIO_MSG_OMR_MUI 0x00000002
#define RIO_MSG_OSR_TE 0x00000080
#define RIO_MSG_OSR_QOI 0x00000020
#define RIO_MSG_OSR_QFI 0x00000010
#define RIO_MSG_OSR_MUB 0x00000004
#define RIO_MSG_OSR_EOMI 0x00000002
#define RIO_MSG_OSR_QEI 0x00000001
#define RIO_MSG_IMR_MI 0x00000002
#define RIO_MSG_ISR_TE 0x00000080
#define RIO_MSG_ISR_QFI 0x00000010
#define RIO_MSG_ISR_DIQI 0x00000001
#define RIO_MSG_DESC_SIZE 32
#define RIO_MSG_BUFFER_SIZE 4096
#define RIO_MIN_TX_RING_SIZE 2
#define RIO_MAX_TX_RING_SIZE 2048
#define RIO_MIN_RX_RING_SIZE 2
#define RIO_MAX_RX_RING_SIZE 2048
#define DOORBELL_DMR_DI 0x00000002
#define DOORBELL_DSR_TE 0x00000080
#define DOORBELL_DSR_QFI 0x00000010
#define DOORBELL_DSR_DIQI 0x00000001
#define DOORBELL_TID_OFFSET 0x03
#define DOORBELL_SID_OFFSET 0x05
#define DOORBELL_INFO_OFFSET 0x06
#define DOORBELL_MESSAGE_SIZE 0x08
#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
#define is_power_of_2(x) (((x) & ((x) - 1)) == 0)
struct rio_atmu_regs {
u32 rowtar;
u32 pad1;
u32 rowbar;
u32 pad2;
u32 rowar;
u32 pad3[3];
};
struct rio_msg_regs {
u32 omr;
u32 osr;
u32 pad1;
u32 odqdpar;
u32 pad2;
u32 osar;
u32 odpr;
u32 odatr;
u32 odcr;
u32 pad3;
u32 odqepar;
u32 pad4[13];
u32 imr;
u32 isr;
u32 pad5;
u32 ifqdpar;
u32 pad6;
u32 ifqepar;
u32 pad7[250];
u32 dmr;
u32 dsr;
u32 pad8;
u32 dqdpar;
u32 pad9;
u32 dqepar;
u32 pad10[26];
u32 pwmr;
u32 pwsr;
u32 pad11;
u32 pwqbar;
};
struct rio_tx_desc {
u32 res1;
u32 saddr;
u32 dport;
u32 dattr;
u32 res2;
u32 res3;
u32 dwcnt;
u32 res4;
};
static u32 regs_win;
static struct rio_atmu_regs *atmu_regs;
static struct rio_atmu_regs *maint_atmu_regs;
static struct rio_atmu_regs *dbell_atmu_regs;
static u32 dbell_win;
static u32 maint_win;
static struct rio_msg_regs *msg_regs;
static struct rio_dbell_ring {
void *virt;
dma_addr_t phys;
} dbell_ring;
static struct rio_msg_tx_ring {
void *virt;
dma_addr_t phys;
void *virt_buffer[RIO_MAX_TX_RING_SIZE];
dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
int tx_slot;
int size;
void *dev_id;
} msg_tx_ring;
static struct rio_msg_rx_ring {
void *virt;
dma_addr_t phys;
void *virt_buffer[RIO_MAX_RX_RING_SIZE];
int rx_slot;
int size;
void *dev_id;
} msg_rx_ring;
/**
* mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
* @index: ID of RapidIO interface
* @destid: Destination ID of target device
* @data: 16-bit info field of RapidIO doorbell message
*
* Sends a MPC85xx doorbell message. Returns %0 on success or
* %-EINVAL on failure.
*/
static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
{
pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
index, destid, data);
out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
out_be16((void *)(dbell_win), data);
return 0;
}
/**
* mpc85xx_local_config_read - Generate a MPC85xx local config space read
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be read into
*
* Generates a MPC85xx local configuration space read. Returns %0 on
* success or %-EINVAL on failure.
*/
static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
{
pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
offset);
*data = in_be32((void *)(regs_win + offset));
return 0;
}
/**
* mpc85xx_local_config_write - Generate a MPC85xx local config space write
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be written
*
* Generates a MPC85xx local configuration space write. Returns %0 on
* success or %-EINVAL on failure.
*/
static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
{
pr_debug
("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
index, offset, data);
out_be32((void *)(regs_win + offset), data);
return 0;
}
/**
* mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @val: Location to be read into
*
* Generates a MPC85xx read maintenance transaction. Returns %0 on
* success or %-EINVAL on failure.
*/
static int
mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
u32 * val)
{
u8 *data;
pr_debug
("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
index, destid, hopcount, offset, len);
out_be32((void *)&maint_atmu_regs->rowtar,
(destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
data = (u8 *) maint_win + offset;
switch (len) {
case 1:
*val = in_8((u8 *) data);
break;
case 2:
*val = in_be16((u16 *) data);
break;
default:
*val = in_be32((u32 *) data);
break;
}
return 0;
}
/**
* mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @val: Value to be written
*
* Generates an MPC85xx write maintenance transaction. Returns %0 on
* success or %-EINVAL on failure.
*/
static int
mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
int len, u32 val)
{
u8 *data;
pr_debug
("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
index, destid, hopcount, offset, len, val);
out_be32((void *)&maint_atmu_regs->rowtar,
(destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
data = (u8 *) maint_win + offset;
switch (len) {
case 1:
out_8((u8 *) data, val);
break;
case 2:
out_be16((u16 *) data, val);
break;
default:
out_be32((u32 *) data, val);
break;
}
return 0;
}
/**
* rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
* @mport: Master port with outbound message queue
* @rdev: Target of outbound message
* @mbox: Outbound mailbox
* @buffer: Message to add to outbound queue
* @len: Length of message
*
* Adds the @buffer message to the MPC85xx outbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
int
rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
void *buffer, size_t len)
{
u32 omr;
struct rio_tx_desc *desc =
(struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
int ret = 0;
pr_debug
("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
rdev->destid, mbox, (int)buffer, len);
if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
ret = -EINVAL;
goto out;
}
/* Copy and clear rest of buffer */
memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
if (len < (RIO_MAX_MSG_SIZE - 4))
memset((void *)((u32) msg_tx_ring.
virt_buffer[msg_tx_ring.tx_slot] + len), 0,
RIO_MAX_MSG_SIZE - len);
/* Set mbox field for message */
desc->dport = mbox & 0x3;
/* Enable EOMI interrupt, set priority, and set destid */
desc->dattr = 0x28000000 | (rdev->destid << 2);
/* Set transfer size aligned to next power of 2 (in double words) */
desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
/* Set snooping and source buffer address */
desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
/* Increment enqueue pointer */
omr = in_be32((void *)&msg_regs->omr);
out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
/* Go to next descriptor */
if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
msg_tx_ring.tx_slot = 0;
out:
return ret;
}
EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
/**
* mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
* @regs: Register context
*
* Handles outbound message interrupts. Executes a register outbound
* mailbox event handler and acks the interrupt occurence.
*/
static irqreturn_t
mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs)
{
int osr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
osr = in_be32((void *)&msg_regs->osr);
if (osr & RIO_MSG_OSR_TE) {
pr_info("RIO: outbound message transmission error\n");
out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
goto out;
}
if (osr & RIO_MSG_OSR_QOI) {
pr_info("RIO: outbound message queue overflow\n");
out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
goto out;
}
if (osr & RIO_MSG_OSR_EOMI) {
u32 dqp = in_be32((void *)&msg_regs->odqdpar);
int slot = (dqp - msg_tx_ring.phys) >> 5;
port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
/* Ack the end-of-message interrupt */
out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
}
out:
return IRQ_HANDLED;
}
/**
* rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
* @mport: Master port implementing the outbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
* @entries: Number of entries in the outbound mailbox ring
*
* Initializes buffer ring, request the outbound message interrupt,
* and enables the outbound message unit. Returns %0 on success and
* %-EINVAL or %-ENOMEM on failure.
*/
int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, j, rc = 0;
if ((entries < RIO_MIN_TX_RING_SIZE) ||
(entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
rc = -EINVAL;
goto out;
}
/* Initialize shadow copy ring */
msg_tx_ring.dev_id = dev_id;
msg_tx_ring.size = entries;
for (i = 0; i < msg_tx_ring.size; i++) {
if (!
(msg_tx_ring.virt_buffer[i] =
dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
&msg_tx_ring.phys_buffer[i],
GFP_KERNEL))) {
rc = -ENOMEM;
for (j = 0; j < msg_tx_ring.size; j++)
if (msg_tx_ring.virt_buffer[j])
dma_free_coherent(NULL,
RIO_MSG_BUFFER_SIZE,
msg_tx_ring.
virt_buffer[j],
msg_tx_ring.
phys_buffer[j]);
goto out;
}
}
/* Initialize outbound message descriptor ring */
if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
msg_tx_ring.size *
RIO_MSG_DESC_SIZE,
&msg_tx_ring.phys,
GFP_KERNEL))) {
rc = -ENOMEM;
goto out_dma;
}
memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
msg_tx_ring.tx_slot = 0;
/* Point dequeue/enqueue pointers at first entry in ring */
out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
/* Configure for snooping */
out_be32((void *)&msg_regs->osar, 0x00000004);
/* Clear interrupt status */
out_be32((void *)&msg_regs->osr, 0x000000b3);
/* Hook up outbound message handler */
if ((rc =
request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
"msg_tx", (void *)mport)) < 0)
goto out_irq;
/*
* Configure outbound message unit
* Snooping
* Interrupts (all enabled, except QEIE)
* Chaining mode
* Disable
*/
out_be32((void *)&msg_regs->omr, 0x00100220);
/* Set number of entries */
out_be32((void *)&msg_regs->omr,
in_be32((void *)&msg_regs->omr) |
((get_bitmask_order(entries) - 2) << 12));
/* Now enable the unit */
out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
out:
return rc;
out_irq:
dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
msg_tx_ring.virt, msg_tx_ring.phys);
out_dma:
for (i = 0; i < msg_tx_ring.size; i++)
dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
msg_tx_ring.virt_buffer[i],
msg_tx_ring.phys_buffer[i]);
return rc;
}
/**
* rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
* @mport: Master port implementing the outbound message unit
* @mbox: Mailbox to close
*
* Disables the outbound message unit, free all buffers, and
* frees the outbound message interrupt.
*/
void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
{
/* Disable inbound message unit */
out_be32((void *)&msg_regs->omr, 0);
/* Free ring */
dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
msg_tx_ring.virt, msg_tx_ring.phys);
/* Free interrupt */
free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
}
/**
* mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
* @regs: Register context
*
* Handles inbound message interrupts. Executes a registered inbound
* mailbox event handler and acks the interrupt occurence.
*/
static irqreturn_t
mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs)
{
int isr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
isr = in_be32((void *)&msg_regs->isr);
if (isr & RIO_MSG_ISR_TE) {
pr_info("RIO: inbound message reception error\n");
out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
goto out;
}
/* XXX Need to check/dispatch until queue empty */
if (isr & RIO_MSG_ISR_DIQI) {
/*
* We implement *only* mailbox 0, but can receive messages
* for any mailbox/letter to that mailbox destination. So,
* make the callback with an unknown/invalid mailbox number
* argument.
*/
port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
/* Ack the queueing interrupt */
out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
}
out:
return IRQ_HANDLED;
}
/**
* rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
* @mport: Master port implementing the inbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
* @entries: Number of entries in the inbound mailbox ring
*
* Initializes buffer ring, request the inbound message interrupt,
* and enables the inbound message unit. Returns %0 on success
* and %-EINVAL or %-ENOMEM on failure.
*/
int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, rc = 0;
if ((entries < RIO_MIN_RX_RING_SIZE) ||
(entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
rc = -EINVAL;
goto out;
}
/* Initialize client buffer ring */
msg_rx_ring.dev_id = dev_id;
msg_rx_ring.size = entries;
msg_rx_ring.rx_slot = 0;
for (i = 0; i < msg_rx_ring.size; i++)
msg_rx_ring.virt_buffer[i] = NULL;
/* Initialize inbound message ring */
if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
msg_rx_ring.size *
RIO_MAX_MSG_SIZE,
&msg_rx_ring.phys,
GFP_KERNEL))) {
rc = -ENOMEM;
goto out;
}
/* Point dequeue/enqueue pointers at first entry in ring */
out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
/* Clear interrupt status */
out_be32((void *)&msg_regs->isr, 0x00000091);
/* Hook up inbound message handler */
if ((rc =
request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
"msg_rx", (void *)mport)) < 0) {
dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
msg_tx_ring.virt_buffer[i],
msg_tx_ring.phys_buffer[i]);
goto out;
}
/*
* Configure inbound message unit:
* Snooping
* 4KB max message size
* Unmask all interrupt sources
* Disable
*/
out_be32((void *)&msg_regs->imr, 0x001b0060);
/* Set number of queue entries */
out_be32((void *)&msg_regs->imr,
in_be32((void *)&msg_regs->imr) |
((get_bitmask_order(entries) - 2) << 12));
/* Now enable the unit */
out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
out:
return rc;
}
/**
* rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
* @mport: Master port implementing the inbound message unit
* @mbox: Mailbox to close
*
* Disables the inbound message unit, free all buffers, and
* frees the inbound message interrupt.
*/
void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
{
/* Disable inbound message unit */
out_be32((void *)&msg_regs->imr, 0);
/* Free ring */
dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
msg_rx_ring.virt, msg_rx_ring.phys);
/* Free interrupt */
free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
}
/**
* rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
* @buf: Buffer to add to inbound queue
*
* Adds the @buf buffer to the MPC85xx inbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
{
int rc = 0;
pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
msg_rx_ring.rx_slot);
if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
printk(KERN_ERR
"RIO: error adding inbound buffer %d, buffer exists\n",
msg_rx_ring.rx_slot);
rc = -EINVAL;
goto out;
}
msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
msg_rx_ring.rx_slot = 0;
out:
return rc;
}
EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
/**
* rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
*
* Gets the next available inbound message from the inbound message queue.
* A pointer to the message is returned on success or NULL on failure.
*/
void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
{
u32 imr;
u32 phys_buf, virt_buf;
void *buf = NULL;
int buf_idx;
phys_buf = in_be32((void *)&msg_regs->ifqdpar);
/* If no more messages, then bail out */
if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
goto out2;
virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
buf = msg_rx_ring.virt_buffer[buf_idx];
if (!buf) {
printk(KERN_ERR
"RIO: inbound message copy failed, no buffers\n");
goto out1;
}
/* Copy max message size, caller is expected to allocate that big */
memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
/* Clear the available buffer */
msg_rx_ring.virt_buffer[buf_idx] = NULL;
out1:
imr = in_be32((void *)&msg_regs->imr);
out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
out2:
return buf;
}
EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
/**
* mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
* @regs: Register context
*
* Handles doorbell interrupts. Parses a list of registered
* doorbell event handlers and executes a matching event handler.
*/
static irqreturn_t
mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs)
{
int dsr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
dsr = in_be32((void *)&msg_regs->dsr);
if (dsr & DOORBELL_DSR_TE) {
pr_info("RIO: doorbell reception error\n");
out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
goto out;
}
if (dsr & DOORBELL_DSR_QFI) {
pr_info("RIO: doorbell queue full\n");
out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
goto out;
}
/* XXX Need to check/dispatch until queue empty */
if (dsr & DOORBELL_DSR_DIQI) {
u32 dmsg =
(u32) dbell_ring.virt +
(in_be32((void *)&msg_regs->dqdpar) & 0xfff);
u32 dmr;
struct rio_dbell *dbell;
int found = 0;
pr_debug
("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
list_for_each_entry(dbell, &port->dbells, node) {
if ((dbell->res->start <= DBELL_INF(dmsg)) &&
(dbell->res->end >= DBELL_INF(dmsg))) {
found = 1;
break;
}
}
if (found) {
dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
DBELL_INF(dmsg));
} else {
pr_debug
("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
}
dmr = in_be32((void *)&msg_regs->dmr);
out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
}
out:
return IRQ_HANDLED;
}
/**
* mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
* @mport: Master port implementing the inbound doorbell unit
*
* Initializes doorbell unit hardware and inbound DMA buffer
* ring. Called from mpc85xx_rio_setup(). Returns %0 on success
* or %-ENOMEM on failure.
*/
static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
{
int rc = 0;
/* Map outbound doorbell window immediately after maintenance window */
if (!(dbell_win =
(u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
RIO_DBELL_WIN_SIZE))) {
printk(KERN_ERR
"RIO: unable to map outbound doorbell window\n");
rc = -ENOMEM;
goto out;
}
/* Initialize inbound doorbells */
if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
512 * DOORBELL_MESSAGE_SIZE,
&dbell_ring.phys,
GFP_KERNEL))) {
printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
rc = -ENOMEM;
iounmap((void *)dbell_win);
goto out;
}
/* Point dequeue/enqueue pointers at first entry in ring */
out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
/* Clear interrupt status */
out_be32((void *)&msg_regs->dsr, 0x00000091);
/* Hook up doorbell handler */
if ((rc =
request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
"dbell_rx", (void *)mport) < 0)) {
iounmap((void *)dbell_win);
dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
dbell_ring.virt, dbell_ring.phys);
printk(KERN_ERR
"MPC85xx RIO: unable to request inbound doorbell irq");
goto out;
}
/* Configure doorbells for snooping, 512 entries, and enable */
out_be32((void *)&msg_regs->dmr, 0x00108161);
out:
return rc;
}
static char *cmdline = NULL;
static int mpc85xx_rio_get_hdid(int index)
{
/* XXX Need to parse multiple entries in some format */
if (!cmdline)
return -1;
return simple_strtol(cmdline, NULL, 0);
}
static int mpc85xx_rio_get_cmdline(char *s)
{
if (!s)
return 0;
cmdline = s;
return 1;
}
__setup("riohdid=", mpc85xx_rio_get_cmdline);
/**
* mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
* @law_start: Starting physical address of RapidIO LAW
* @law_size: Size of RapidIO LAW
*
* Initializes MPC85xx RapidIO hardware interface, configures
* master port with system-specific info, and registers the
* master port with the RapidIO subsystem.
*/
void mpc85xx_rio_setup(int law_start, int law_size)
{
struct rio_ops *ops;
struct rio_mport *port;
ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
ops->lcread = mpc85xx_local_config_read;
ops->lcwrite = mpc85xx_local_config_write;
ops->cread = mpc85xx_rio_config_read;
ops->cwrite = mpc85xx_rio_config_write;
ops->dsend = mpc85xx_rio_doorbell_send;
port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
port->id = 0;
port->index = 0;
INIT_LIST_HEAD(&port->dbells);
port->iores.start = law_start;
port->iores.end = law_start + law_size;
port->iores.flags = IORESOURCE_MEM;
rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
strcpy(port->name, "RIO0 mport");
port->ops = ops;
port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
rio_register_mport(port);
regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
maint_atmu_regs = atmu_regs + 1;
dbell_atmu_regs = atmu_regs + 2;
msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
/* Configure maintenance transaction window */
out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
/* Configure outbound doorbell window */
out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
mpc85xx_rio_doorbell_init(port);
}

21
arch/ppc/syslib/ppc85xx_rio.h Normal file
Fájl megtekintése

@@ -0,0 +1,21 @@
/*
* MPC85xx RapidIO definitions
*
* Copyright 2005 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PPC_SYSLIB_PPC85XX_RIO_H
#define __PPC_SYSLIB_PPC85XX_RIO_H
#include <linux/config.h>
#include <linux/init.h>
extern void mpc85xx_rio_setup(int law_start, int law_size);
#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */

1
arch/ppc/syslib/ppc_sys.c
Fájl megtekintése

@@ -14,6 +14,7 @@
* option) any later version.
*/
#include <linux/string.h>
#include <asm/ppc_sys.h>
int (*ppc_sys_device_fixup) (struct platform_device * pdev);

6
arch/ppc/syslib/prom.c
Fájl megtekintése

@@ -1335,10 +1335,8 @@ release_OF_resource(struct device_node* node, int index)
if (!res)
return -ENODEV;
if (res->name) {
kfree(res->name);
res->name = NULL;
}
kfree(res->name);
res->name = NULL;
release_resource(res);
kfree(res);