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Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

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Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d71 clk: samsung: exynos4: fix g3d clocks
c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244a clk: samsung: exynos5260: fix typo in clock name
e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
This commit is contained in:
Mike Turquette
2014-09-29 23:43:12 -07:00
parent 82de1bc86c fa0111be4f
commit 24afc3852e
7 changed files with 257 additions and 20 deletions
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27
include/dt-bindings/clock/exynos3250.h
View File

@@ -255,4 +255,31 @@
*/
#define CLK_NR_CLKS 248
/*
* CMU DMC
*/
#define CLK_FOUT_BPLL 1
#define CLK_FOUT_EPLL 2
/* Muxes */
#define CLK_MOUT_MPLL_MIF 8
#define CLK_MOUT_BPLL 9
#define CLK_MOUT_DPHY 10
#define CLK_MOUT_DMC_BUS 11
#define CLK_MOUT_EPLL 12
/* Dividers */
#define CLK_DIV_DMC 16
#define CLK_DIV_DPHY 17
#define CLK_DIV_DMC_PRE 18
#define CLK_DIV_DMCP 19
#define CLK_DIV_DMCD 20
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_DMC 21
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

12
include/dt-bindings/clock/exynos4.h
View File

@@ -115,11 +115,11 @@
#define CLK_SMMU_MFCR 275
#define CLK_G3D 276
#define CLK_G2D 277
#define CLK_ROTATOR 278 /* Exynos4210 only */
#define CLK_MDMA 279 /* Exynos4210 only */
#define CLK_SMMU_G2D 280 /* Exynos4210 only */
#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */
#define CLK_SMMU_MDMA 282 /* Exynos4210 only */
#define CLK_ROTATOR 278
#define CLK_MDMA 279
#define CLK_SMMU_G2D 280
#define CLK_SMMU_ROTATOR 281
#define CLK_SMMU_MDMA 282
#define CLK_FIMD0 283
#define CLK_MIE0 284
#define CLK_MDNIE0 285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
#define CLK_MOUT_G3D1 393
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
#define CLK_MOUT_HDMI 396
#define CLK_MOUT_MIXER 397
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400