Merge branches 'at91', 'ep93xx', 'errata', 'footbridge', 'fncpy', 'gemini', 'irqdata', 'pm', 'sh', 'smp', 'spear', 'ux500' and 'via' into devel
This commit is contained in:
Russell King
@@ -107,11 +107,17 @@ ENTRY(cpu_v7_switch_mm)
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ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
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#ifdef CONFIG_ARM_ERRATA_430973
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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#endif
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#ifdef CONFIG_ARM_ERRATA_754322
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dsb
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#endif
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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isb
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#ifdef CONFIG_ARM_ERRATA_754322
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dsb
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#endif
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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#endif
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@@ -171,6 +177,87 @@ cpu_v7_name:
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.ascii "ARMv7 Processor"
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.align
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/*
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* Memory region attributes with SCTLR.TRE=1
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*
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* n = TEX[0],C,B
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* TR = PRRR[2n+1:2n] - memory type
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* IR = NMRR[2n+1:2n] - inner cacheable property
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* OR = NMRR[2n+17:2n+16] - outer cacheable property
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*
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* n TR IR OR
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* UNCACHED 000 00
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* BUFFERABLE 001 10 00 00
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* WRITETHROUGH 010 10 10 10
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* WRITEBACK 011 10 11 11
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* reserved 110
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* WRITEALLOC 111 10 01 01
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* DEV_SHARED 100 01
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* DEV_NONSHARED 100 01
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* DEV_WC 001 10
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* DEV_CACHED 011 10
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*
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* Other attributes:
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*
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* DS0 = PRRR[16] = 0 - device shareable property
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* DS1 = PRRR[17] = 1 - device shareable property
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* NS0 = PRRR[18] = 0 - normal shareable property
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* NS1 = PRRR[19] = 1 - normal shareable property
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* NOS = PRRR[24+n] = 1 - not outer shareable
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*/
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.equ PRRR, 0xff0a81a8
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.equ NMRR, 0x40e040e0
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 8
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#ifdef CONFIG_PM
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r11, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 1 @ Context ID
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 0 @ TTB 0
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mrc p15, 0, r8, c2, c0, 1 @ TTB 1
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
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stmia r0, {r4 - r11}
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_v7_do_suspend)
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ENTRY(cpu_v7_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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ldmia r0, {r4 - r11}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 1 @ Context ID
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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mcr p15, 0, r7, c2, c0, 0 @ TTB 0
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mcr p15, 0, r8, c2, c0, 1 @ TTB 1
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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isb
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mov r0, r9 @ control register
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, cpu_resume_l1_flags
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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cpu_resume_l1_flags:
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ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
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ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
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#else
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#define cpu_v7_do_suspend 0
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#define cpu_v7_do_resume 0
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#endif
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__CPUINIT
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/*
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@@ -264,6 +351,12 @@ __v7_setup:
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_751472
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cmp r6, #0x30 @ present prior to r3p0
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mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrlt r10, r10, #1 << 11 @ set bit #11
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mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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3: mov r10, #0
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#ifdef HARVARD_CACHE
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@@ -276,36 +369,8 @@ __v7_setup:
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ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
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ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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/*
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* Memory region attributes with SCTLR.TRE=1
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*
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* n = TEX[0],C,B
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* TR = PRRR[2n+1:2n] - memory type
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* IR = NMRR[2n+1:2n] - inner cacheable property
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* OR = NMRR[2n+17:2n+16] - outer cacheable property
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*
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* n TR IR OR
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* UNCACHED 000 00
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* BUFFERABLE 001 10 00 00
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* WRITETHROUGH 010 10 10 10
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* WRITEBACK 011 10 11 11
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* reserved 110
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* WRITEALLOC 111 10 01 01
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* DEV_SHARED 100 01
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* DEV_NONSHARED 100 01
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* DEV_WC 001 10
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* DEV_CACHED 011 10
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*
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* Other attributes:
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*
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* DS0 = PRRR[16] = 0 - device shareable property
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* DS1 = PRRR[17] = 1 - device shareable property
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* NS0 = PRRR[18] = 0 - normal shareable property
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* NS1 = PRRR[19] = 1 - normal shareable property
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* NOS = PRRR[24+n] = 1 - not outer shareable
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*/
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ldr r5, =0xff0a81a8 @ PRRR
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ldr r6, =0x40e040e0 @ NMRR
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ldr r5, =PRRR @ PRRR
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ldr r6, =NMRR @ NMRR
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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#endif
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@@ -351,6 +416,9 @@ ENTRY(v7_processor_functions)
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.word cpu_v7_dcache_clean_area
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.word cpu_v7_switch_mm
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.word cpu_v7_set_pte_ext
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.word 0
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.word 0
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.word 0
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.size v7_processor_functions, . - v7_processor_functions
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.section ".rodata"
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