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Merge branch 'core/urgent' into x86/urgent, to pick up objtool fix

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Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
2018-11-03 23:42:16 +01:00
parent 98f76206b3 bcb6fb5da7
commit 23a12ddee1
4068 changed files with 262354 additions and 74077 deletions
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4
include/asm-generic/percpu.h
View File

@@ -62,10 +62,6 @@ extern void setup_per_cpu_areas(void);
#define PER_CPU_ATTRIBUTES
#endif
#ifndef PER_CPU_DEF_ATTRIBUTES
#define PER_CPU_DEF_ATTRIBUTES
#endif
#define raw_cpu_generic_read(pcp) \
({ \
*raw_cpu_ptr(&(pcp)); \

3
include/drm/drmP.h
View File

@@ -110,7 +110,4 @@ static inline bool drm_can_sleep(void)
return true;
}
/* helper for handling conditionals in various for_each macros */
#define for_each_if(condition) if (!(condition)) {} else
#endif

23
include/drm/drm_atomic.h
View File

@@ -29,6 +29,7 @@
#define DRM_ATOMIC_H_
#include <drm/drm_crtc.h>
#include <drm/drm_util.h>
/**
* struct drm_crtc_commit - track modeset commits on a CRTC
@@ -384,9 +385,6 @@ void drm_atomic_state_default_release(struct drm_atomic_state *state);
struct drm_crtc_state * __must_check
drm_atomic_get_crtc_state(struct drm_atomic_state *state,
struct drm_crtc *crtc);
int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state, struct drm_property *property,
uint64_t val);
struct drm_plane_state * __must_check
drm_atomic_get_plane_state(struct drm_atomic_state *state,
struct drm_plane *plane);
@@ -597,25 +595,6 @@ __drm_atomic_get_current_plane_state(struct drm_atomic_state *state,
return plane->state;
}
int __must_check
drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
const struct drm_display_mode *mode);
int __must_check
drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
struct drm_property_blob *blob);
int __must_check
drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
struct drm_crtc *crtc);
void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
struct drm_framebuffer *fb);
void drm_atomic_set_fence_for_plane(struct drm_plane_state *plane_state,
struct dma_fence *fence);
int __must_check
drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
struct drm_crtc *crtc);
int drm_atomic_set_writeback_fb_for_connector(
struct drm_connector_state *conn_state,
struct drm_framebuffer *fb);
int __must_check
drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
struct drm_crtc *crtc);

3
include/drm/drm_atomic_helper.h
View File

@@ -31,6 +31,7 @@
#include <drm/drm_crtc.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_modeset_helper.h>
#include <drm/drm_util.h>
struct drm_atomic_state;
struct drm_private_obj;
@@ -156,6 +157,8 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state);
void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
struct drm_plane_state *state);
void drm_atomic_helper_plane_reset(struct drm_plane *plane);
void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,
struct drm_plane_state *state);

58
include/drm/drm_atomic_uapi.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (C) 2014 Red Hat
* Copyright (C) 2014 Intel Corp.
* Copyright (C) 2018 Intel Corp.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Rob Clark <robdclark@gmail.com>
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
#ifndef DRM_ATOMIC_UAPI_H_
#define DRM_ATOMIC_UAPI_H_
struct drm_crtc_state;
struct drm_display_mode;
struct drm_property_blob;
struct drm_plane_state;
struct drm_crtc;
struct drm_connector_state;
struct dma_fence;
struct drm_framebuffer;
int __must_check
drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
const struct drm_display_mode *mode);
int __must_check
drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
struct drm_property_blob *blob);
int __must_check
drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
struct drm_crtc *crtc);
void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
struct drm_framebuffer *fb);
void drm_atomic_set_fence_for_plane(struct drm_plane_state *plane_state,
struct dma_fence *fence);
int __must_check
drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
struct drm_crtc *crtc);
#endif

6
include/drm/drm_blend.h
View File

@@ -27,6 +27,10 @@
#include <linux/ctype.h>
#include <drm/drm_mode.h>
#define DRM_MODE_BLEND_PREMULTI 0
#define DRM_MODE_BLEND_COVERAGE 1
#define DRM_MODE_BLEND_PIXEL_NONE 2
struct drm_device;
struct drm_atomic_state;
struct drm_plane;
@@ -52,4 +56,6 @@ int drm_plane_create_zpos_immutable_property(struct drm_plane *plane,
unsigned int zpos);
int drm_atomic_normalize_zpos(struct drm_device *dev,
struct drm_atomic_state *state);
int drm_plane_create_blend_mode_property(struct drm_plane *plane,
unsigned int supported_modes);
#endif

1
include/drm/drm_color_mgmt.h
View File

@@ -24,6 +24,7 @@
#define __DRM_COLOR_MGMT_H__
#include <linux/ctype.h>
#include <drm/drm_property.h>
struct drm_crtc;
struct drm_plane;

1
include/drm/drm_connector.h
View File

@@ -28,6 +28,7 @@
#include <linux/ctype.h>
#include <linux/hdmi.h>
#include <drm/drm_mode_object.h>
#include <drm/drm_util.h>
#include <uapi/drm/drm_mode.h>

41
include/drm/drm_crtc.h
View File

@@ -744,8 +744,45 @@ struct drm_crtc_funcs {
*
* 0 on success or a negative error code on failure.
*/
int (*set_crc_source)(struct drm_crtc *crtc, const char *source,
size_t *values_cnt);
int (*set_crc_source)(struct drm_crtc *crtc, const char *source);
/**
* @verify_crc_source:
*
* verifies the source of CRC checksums of frames before setting the
* source for CRC and during crc open. Source parameter can be NULL
* while disabling crc source.
*
* This callback is optional if the driver does not support any CRC
* generation functionality.
*
* RETURNS:
*
* 0 on success or a negative error code on failure.
*/
int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
size_t *values_cnt);
/**
* @get_crc_sources:
*
* Driver callback for getting a list of all the available sources for
* CRC generation. This callback depends upon verify_crc_source, So
* verify_crc_source callback should be implemented before implementing
* this. Driver can pass full list of available crc sources, this
* callback does the verification on each crc-source before passing it
* to userspace.
*
* This callback is optional if the driver does not support exporting of
* possible CRC sources list.
*
* RETURNS:
*
* a constant character pointer to the list of all the available CRC
* sources. On failure driver should return NULL. count should be
* updated with number of sources in list. if zero we don't process any
* source from the list.
*/
const char *const *(*get_crc_sources)(struct drm_crtc *crtc,
size_t *count);
/**
* @atomic_print_state:

10
include/drm/drm_device.h
View File

@@ -45,6 +45,16 @@ struct drm_device {
/* currently active master for this device. Protected by master_mutex */
struct drm_master *master;
/**
* @driver_features: per-device driver features
*
* Drivers can clear specific flags here to disallow
* certain features on a per-device basis while still
* sharing a single &struct drm_driver instance across
* all devices.
*/
u32 driver_features;
/**
* @unplugged:
*

11
include/drm/drm_dp_helper.h
View File

@@ -123,8 +123,9 @@
# define DP_FRAMING_CHANGE_CAP (1 << 1)
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
@@ -1260,12 +1261,12 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
*/
enum drm_dp_quirk {
/**
* @DP_DPCD_QUIRK_LIMITED_M_N:
* @DP_DPCD_QUIRK_CONSTANT_N:
*
* The device requires main link attributes Mvid and Nvid to be limited
* to 16 bits.
* to 16 bits. So will give a constant value (0x8000) for compatability.
*/
DP_DPCD_QUIRK_LIMITED_M_N,
DP_DPCD_QUIRK_CONSTANT_N,
};
/**

9
include/drm/drm_drv.h
View File

@@ -56,7 +56,6 @@ struct drm_printer;
#define DRIVER_ATOMIC 0x10000
#define DRIVER_KMS_LEGACY_CONTEXT 0x20000
#define DRIVER_SYNCOBJ 0x40000
#define DRIVER_PREFER_XBGR_30BPP 0x80000
/**
* struct drm_driver - DRM driver structure
@@ -654,14 +653,14 @@ static inline bool drm_dev_is_unplugged(struct drm_device *dev)
* @dev: DRM device to check
* @feature: feature flag
*
* This checks @dev for driver features, see &drm_driver.driver_features and the
* various DRIVER_\* flags.
* This checks @dev for driver features, see &drm_driver.driver_features,
* &drm_device.driver_features, and the various DRIVER_\* flags.
*
* Returns true if the @feature is supported, false otherwise.
*/
static inline bool drm_core_check_feature(struct drm_device *dev, int feature)
static inline bool drm_core_check_feature(struct drm_device *dev, u32 feature)
{
return dev->driver->driver_features & feature;
return dev->driver->driver_features & dev->driver_features & feature;
}
/**

1
include/drm/drm_encoder.h
View File

@@ -28,6 +28,7 @@
#include <drm/drm_crtc.h>
#include <drm/drm_mode.h>
#include <drm/drm_mode_object.h>
#include <drm/drm_util.h>
struct drm_encoder;

1
include/drm/drm_fb_cma_helper.h
View File

@@ -26,7 +26,6 @@ void drm_fbdev_cma_fini(struct drm_fbdev_cma *fbdev_cma);
void drm_fbdev_cma_restore_mode(struct drm_fbdev_cma *fbdev_cma);
void drm_fbdev_cma_hotplug_event(struct drm_fbdev_cma *fbdev_cma);
void drm_fbdev_cma_set_suspend(struct drm_fbdev_cma *fbdev_cma, bool state);
void drm_fbdev_cma_set_suspend_unlocked(struct drm_fbdev_cma *fbdev_cma,
bool state);

34
include/drm/drm_fb_helper.h
View File

@@ -604,6 +604,16 @@ drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp)
#endif
/**
* drm_fb_helper_remove_conflicting_framebuffers - remove firmware-configured framebuffers
* @a: memory range, users of which are to be removed
* @name: requesting driver name
* @primary: also kick vga16fb if present
*
* This function removes framebuffer devices (initialized by firmware/bootloader)
* which use memory range described by @a. If @a is NULL all such devices are
* removed.
*/
static inline int
drm_fb_helper_remove_conflicting_framebuffers(struct apertures_struct *a,
const char *name, bool primary)
@@ -615,4 +625,28 @@ drm_fb_helper_remove_conflicting_framebuffers(struct apertures_struct *a,
#endif
}
/**
* drm_fb_helper_remove_conflicting_pci_framebuffers - remove firmware-configured framebuffers for PCI devices
* @pdev: PCI device
* @resource_id: index of PCI BAR configuring framebuffer memory
* @name: requesting driver name
*
* This function removes framebuffer devices (eg. initialized by firmware)
* using memory range configured for @pdev's BAR @resource_id.
*
* The function assumes that PCI device with shadowed ROM drives a primary
* display and so kicks out vga16fb.
*/
static inline int
drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
int resource_id,
const char *name)
{
#if IS_REACHABLE(CONFIG_FB)
return remove_conflicting_pci_framebuffers(pdev, resource_id, name);
#else
return 0;
#endif
}
#endif

24
include/drm/drm_fourcc.h
View File

@@ -25,6 +25,28 @@
#include <linux/types.h>
#include <uapi/drm/drm_fourcc.h>
/*
* DRM formats are little endian. Define host endian variants for the
* most common formats here, to reduce the #ifdefs needed in drivers.
*
* Note that the DRM_FORMAT_BIG_ENDIAN flag should only be used in
* case the format can't be specified otherwise, so we don't end up
* with two values describing the same format.
*/
#ifdef __BIG_ENDIAN
# define DRM_FORMAT_HOST_XRGB1555 (DRM_FORMAT_XRGB1555 | \
DRM_FORMAT_BIG_ENDIAN)
# define DRM_FORMAT_HOST_RGB565 (DRM_FORMAT_RGB565 | \
DRM_FORMAT_BIG_ENDIAN)
# define DRM_FORMAT_HOST_XRGB8888 DRM_FORMAT_BGRX8888
# define DRM_FORMAT_HOST_ARGB8888 DRM_FORMAT_BGRA8888
#else
# define DRM_FORMAT_HOST_XRGB1555 DRM_FORMAT_XRGB1555
# define DRM_FORMAT_HOST_RGB565 DRM_FORMAT_RGB565
# define DRM_FORMAT_HOST_XRGB8888 DRM_FORMAT_XRGB8888
# define DRM_FORMAT_HOST_ARGB8888 DRM_FORMAT_ARGB8888
#endif
struct drm_device;
struct drm_mode_fb_cmd2;
@@ -66,6 +88,8 @@ const struct drm_format_info *
drm_get_format_info(struct drm_device *dev,
const struct drm_mode_fb_cmd2 *mode_cmd);
uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth);
uint32_t drm_driver_legacy_fb_format(struct drm_device *dev,
uint32_t bpp, uint32_t depth);
int drm_format_num_planes(uint32_t format);
int drm_format_plane_cpp(uint32_t format, int plane);
int drm_format_horz_chroma_subsampling(uint32_t format);

15
include/drm/drm_mode_config.h
View File

@@ -809,6 +809,21 @@ struct drm_mode_config {
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
bool quirk_addfb_prefer_xbgr_30bpp;
/**
* @quirk_addfb_prefer_host_byte_order:
*
* When set to true drm_mode_addfb() will pick host byte order
* pixel_format when calling drm_mode_addfb2(). This is how
* drm_mode_addfb() should have worked from day one. It
* didn't though, so we ended up with quirks in both kernel
* and userspace drivers to deal with the broken behavior.
* Simply fixing drm_mode_addfb() unconditionally would break
* these drivers, so add a quirk bit here to allow drivers
* opt-in.
*/
bool quirk_addfb_prefer_host_byte_order;
/**
* @async_page_flip: Does this device support async flips on the primary

1
include/drm/drm_panel.h
View File

@@ -82,6 +82,7 @@ struct drm_panel_funcs {
* @drm: DRM device owning the panel
* @connector: DRM connector that the panel is attached to
* @dev: parent device of the panel
* @link: link from panel device (supplier) to DRM device (consumer)
* @funcs: operations that can be performed on the panel
* @list: panel entry in registry
*/

2
include/drm/drm_pciids.h
View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: MIT */
#define radeon_PCI_IDS \
{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

19
include/drm/drm_plane.h
View File

@@ -27,6 +27,9 @@
#include <linux/ctype.h>
#include <drm/drm_mode_object.h>
#include <drm/drm_color_mgmt.h>
#include <drm/drm_rect.h>
#include <drm/drm_modeset_lock.h>
#include <drm/drm_util.h>
struct drm_crtc;
struct drm_printer;
@@ -118,6 +121,14 @@ struct drm_plane_state {
*/
u16 alpha;
/**
* @pixel_blend_mode:
* The alpha blending equation selection, describing how the pixels from
* the current plane are composited with the background. Value can be
* one of DRM_MODE_BLEND_*
*/
uint16_t pixel_blend_mode;
/**
* @rotation:
* Rotation of the plane. See drm_plane_create_rotation_property() for
@@ -659,6 +670,14 @@ struct drm_plane {
* drm_plane_create_rotation_property().
*/
struct drm_property *rotation_property;
/**
* @blend_mode_property:
* Optional "pixel blend mode" enum property for this plane.
* Blend mode property represents the alpha blending equation selection,
* describing how the pixels from the current plane are composited with
* the background.
*/
struct drm_property *blend_mode_property;
/**
* @color_encoding_property:

2
include/drm/drm_print.h
View File

@@ -381,7 +381,7 @@ void drm_err(const char *format, ...);
#define DRM_DEV_DEBUG_DP(dev, fmt, ...) \
drm_dev_dbg(dev, DRM_UT_DP, fmt, ## __VA_ARGS__)
#define DRM_DEBUG_DP(dev, fmt, ...) \
#define DRM_DEBUG_DP(fmt, ...) \
drm_dbg(DRM_UT_DP, fmt, ## __VA_ARGS__)
#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...) \

2
include/drm/drm_property.h
View File

@@ -27,6 +27,8 @@
#include <linux/ctype.h>
#include <drm/drm_mode_object.h>
#include <uapi/drm/drm_mode.h>
/**
* struct drm_property_enum - symbolic values for enumerations
* @value: numeric property value for this enum entry

9
include/drm/drm_syncobj.h
View File

@@ -131,15 +131,10 @@ drm_syncobj_fence_get(struct drm_syncobj *syncobj)
struct drm_syncobj *drm_syncobj_find(struct drm_file *file_private,
u32 handle);
void drm_syncobj_add_callback(struct drm_syncobj *syncobj,
struct drm_syncobj_cb *cb,
drm_syncobj_func_t func);
void drm_syncobj_remove_callback(struct drm_syncobj *syncobj,
struct drm_syncobj_cb *cb);
void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, u64 point,
struct dma_fence *fence);
int drm_syncobj_find_fence(struct drm_file *file_private,
u32 handle,
u32 handle, u64 point,
struct dma_fence **fence);
void drm_syncobj_free(struct kref *kref);
int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,

32
include/drm/drm_util.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* Internal Header for the Direct Rendering Manager
*
* Copyright 2018 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DRM_UTIL_H_
#define _DRM_UTIL_H_
/* helper for handling conditionals in various for_each macros */
#define for_each_if(condition) if (!(condition)) {} else
#endif

48
include/drm/gpu_scheduler.h
View File

@@ -50,7 +50,10 @@ enum drm_sched_priority {
*
* @list: used to append this struct to the list of entities in the
* runqueue.
* @rq: runqueue to which this entity belongs.
* @rq: runqueue on which this entity is currently scheduled.
* @rq_list: a list of run queues on which jobs from this entity can
* be scheduled
* @num_rq_list: number of run queues in the rq_list
* @rq_lock: lock to modify the runqueue to which this entity belongs.
* @job_queue: the list of jobs of this entity.
* @fence_seq: a linearly increasing seqno incremented with each
@@ -67,6 +70,7 @@ enum drm_sched_priority {
* @fini_status: contains the exit status in case the process was signalled.
* @last_scheduled: points to the finished fence of the last scheduled job.
* @last_user: last group leader pushing a job into the entity.
* @stopped: Marks the enity as removed from rq and destined for termination.
*
* Entities will emit jobs in order to their corresponding hardware
* ring, and the scheduler will alternate between entities based on
@@ -75,6 +79,8 @@ enum drm_sched_priority {
struct drm_sched_entity {
struct list_head list;
struct drm_sched_rq *rq;
struct drm_sched_rq **rq_list;
unsigned int num_rq_list;
spinlock_t rq_lock;
struct spsc_queue job_queue;
@@ -87,6 +93,7 @@ struct drm_sched_entity {
atomic_t *guilty;
struct dma_fence *last_scheduled;
struct task_struct *last_user;
bool stopped;
};
/**
@@ -168,8 +175,6 @@ struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
* finished to remove the job from the
* @drm_gpu_scheduler.ring_mirror_list.
* @node: used to append this struct to the @drm_gpu_scheduler.ring_mirror_list.
* @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the timeout
* interval is over.
* @id: a unique id assigned to each job scheduled on the scheduler.
* @karma: increment on every hang caused by this job. If this exceeds the hang
* limit of the scheduler then the job is marked guilty and will not
@@ -188,7 +193,6 @@ struct drm_sched_job {
struct dma_fence_cb finish_cb;
struct work_struct finish_work;
struct list_head node;
struct delayed_work work_tdr;
uint64_t id;
atomic_t karma;
enum drm_sched_priority s_priority;
@@ -252,11 +256,14 @@ struct drm_sched_backend_ops {
* finished.
* @hw_rq_count: the number of jobs currently in the hardware queue.
* @job_id_count: used to assign unique id to the each job.
* @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the
* timeout interval is over.
* @thread: the kthread on which the scheduler which run.
* @ring_mirror_list: the list of jobs which are currently in the job queue.
* @job_list_lock: lock to protect the ring_mirror_list.
* @hang_limit: once the hangs by a job crosses this limit then it is marked
* guilty and it will be considered for scheduling further.
* @num_jobs: the number of jobs in queue in the scheduler
*
* One scheduler is implemented for each hardware ring.
*/
@@ -270,10 +277,12 @@ struct drm_gpu_scheduler {
wait_queue_head_t job_scheduled;
atomic_t hw_rq_count;
atomic64_t job_id_count;
struct delayed_work work_tdr;
struct task_struct *thread;
struct list_head ring_mirror_list;
spinlock_t job_list_lock;
int hang_limit;
atomic_t num_jobs;
};
int drm_sched_init(struct drm_gpu_scheduler *sched,
@@ -281,6 +290,21 @@ int drm_sched_init(struct drm_gpu_scheduler *sched,
uint32_t hw_submission, unsigned hang_limit, long timeout,
const char *name);
void drm_sched_fini(struct drm_gpu_scheduler *sched);
int drm_sched_job_init(struct drm_sched_job *job,
struct drm_sched_entity *entity,
void *owner);
void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
struct drm_sched_job *job);
void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
bool drm_sched_dependency_optimized(struct dma_fence* fence,
struct drm_sched_entity *entity);
void drm_sched_job_kickout(struct drm_sched_job *s_job);
void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
struct drm_sched_entity *entity);
void drm_sched_rq_remove_entity(struct drm_sched_rq *rq,
struct drm_sched_entity *entity);
int drm_sched_entity_init(struct drm_sched_entity *entity,
struct drm_sched_rq **rq_list,
@@ -289,23 +313,17 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout);
void drm_sched_entity_fini(struct drm_sched_entity *entity);
void drm_sched_entity_destroy(struct drm_sched_entity *entity);
void drm_sched_entity_select_rq(struct drm_sched_entity *entity);
struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity);
void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
struct drm_sched_entity *entity);
void drm_sched_entity_set_rq(struct drm_sched_entity *entity,
struct drm_sched_rq *rq);
void drm_sched_entity_set_priority(struct drm_sched_entity *entity,
enum drm_sched_priority priority);
bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
struct drm_sched_fence *drm_sched_fence_create(
struct drm_sched_entity *s_entity, void *owner);
void drm_sched_fence_scheduled(struct drm_sched_fence *fence);
void drm_sched_fence_finished(struct drm_sched_fence *fence);
int drm_sched_job_init(struct drm_sched_job *job,
struct drm_sched_entity *entity,
void *owner);
void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
struct drm_sched_job *job);
void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
bool drm_sched_dependency_optimized(struct dma_fence* fence,
struct drm_sched_entity *entity);
void drm_sched_job_kickout(struct drm_sched_job *s_job);
#endif

1
include/drm/i915_pciids.h
View File

@@ -386,6 +386,7 @@
INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
/* CFL H */

34
include/drm/ttm/ttm_bo_api.h
View File

@@ -51,6 +51,8 @@ struct ttm_placement;
struct ttm_place;
struct ttm_lru_bulk_move;
/**
* struct ttm_bus_placement
*
@@ -310,6 +312,24 @@ ttm_bo_reference(struct ttm_buffer_object *bo)
return bo;
}
/**
* ttm_bo_get_unless_zero - reference a struct ttm_buffer_object unless
* its refcount has already reached zero.
* @bo: The buffer object.
*
* Used to reference a TTM buffer object in lookups where the object is removed
* from the lookup structure during the destructor and for RCU lookups.
*
* Returns: @bo if the referencing was successful, NULL otherwise.
*/
static inline __must_check struct ttm_buffer_object *
ttm_bo_get_unless_zero(struct ttm_buffer_object *bo)
{
if (!kref_get_unless_zero(&bo->kref))
return NULL;
return bo;
}
/**
* ttm_bo_wait - wait for buffer idle.
*
@@ -405,12 +425,24 @@ void ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
* ttm_bo_move_to_lru_tail
*
* @bo: The buffer object.
* @bulk: optional bulk move structure to remember BO positions
*
* Move this BO to the tail of all lru lists used to lookup and reserve an
* object. This function must be called with struct ttm_bo_global::lru_lock
* held, and is used to make a BO less likely to be considered for eviction.
*/
void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
struct ttm_lru_bulk_move *bulk);
/**
* ttm_bo_bulk_move_lru_tail
*
* @bulk: bulk move structure
*
* Bulk move BOs to the LRU tail, only valid to use when driver makes sure that
* BO order never changes. Should be called with ttm_bo_global::lru_lock held.
*/
void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move *bulk);
/**
* ttm_bo_lock_delayed_workqueue

28
include/drm/ttm/ttm_bo_driver.h
View File

@@ -490,6 +490,34 @@ struct ttm_bo_device {
bool no_retry;
};
/**
* struct ttm_lru_bulk_move_pos
*
* @first: first BO in the bulk move range
* @last: last BO in the bulk move range
*
* Positions for a lru bulk move.
*/
struct ttm_lru_bulk_move_pos {
struct ttm_buffer_object *first;
struct ttm_buffer_object *last;
};
/**
* struct ttm_lru_bulk_move
*
* @tt: first/last lru entry for BOs in the TT domain
* @vram: first/last lru entry for BOs in the VRAM domain
* @swap: first/last lru entry for BOs on the swap list
*
* Helper structure for bulk moves on the LRU list.
*/
struct ttm_lru_bulk_move {
struct ttm_lru_bulk_move_pos tt[TTM_MAX_BO_PRIORITY];
struct ttm_lru_bulk_move_pos vram[TTM_MAX_BO_PRIORITY];
struct ttm_lru_bulk_move_pos swap[TTM_MAX_BO_PRIORITY];
};
/**
* ttm_flag_masked
*

248
include/drm/ttm/ttm_lock.h
View File

@@ -1,248 +0,0 @@
/**************************************************************************
*
* Copyright (c) 2007-2009 VMware, Inc., Palo Alto, CA., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/*
* Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
*/
/** @file ttm_lock.h
* This file implements a simple replacement for the buffer manager use
* of the DRM heavyweight hardware lock.
* The lock is a read-write lock. Taking it in read mode and write mode
* is relatively fast, and intended for in-kernel use only.
*
* The vt mode is used only when there is a need to block all
* user-space processes from validating buffers.
* It's allowed to leave kernel space with the vt lock held.
* If a user-space process dies while having the vt-lock,
* it will be released during the file descriptor release. The vt lock
* excludes write lock and read lock.
*
* The suspend mode is used to lock out all TTM users when preparing for
* and executing suspend operations.
*
*/
#ifndef _TTM_LOCK_H_
#define _TTM_LOCK_H_
#include <linux/wait.h>
#include <linux/atomic.h>
#include "ttm_object.h"
/**
* struct ttm_lock
*
* @base: ttm base object used solely to release the lock if the client
* holding the lock dies.
* @queue: Queue for processes waiting for lock change-of-status.
* @lock: Spinlock protecting some lock members.
* @rw: Read-write lock counter. Protected by @lock.
* @flags: Lock state. Protected by @lock.
* @kill_takers: Boolean whether to kill takers of the lock.
* @signal: Signal to send when kill_takers is true.
*/
struct ttm_lock {
struct ttm_base_object base;
wait_queue_head_t queue;
spinlock_t lock;
int32_t rw;
uint32_t flags;
bool kill_takers;
int signal;
struct ttm_object_file *vt_holder;
};
/**
* ttm_lock_init
*
* @lock: Pointer to a struct ttm_lock
* Initializes the lock.
*/
extern void ttm_lock_init(struct ttm_lock *lock);
/**
* ttm_read_unlock
*
* @lock: Pointer to a struct ttm_lock
*
* Releases a read lock.
*/
extern void ttm_read_unlock(struct ttm_lock *lock);
/**
* ttm_read_lock
*
* @lock: Pointer to a struct ttm_lock
* @interruptible: Interruptible sleeping while waiting for a lock.
*
* Takes the lock in read mode.
* Returns:
* -ERESTARTSYS If interrupted by a signal and interruptible is true.
*/
extern int ttm_read_lock(struct ttm_lock *lock, bool interruptible);
/**
* ttm_read_trylock
*
* @lock: Pointer to a struct ttm_lock
* @interruptible: Interruptible sleeping while waiting for a lock.
*
* Tries to take the lock in read mode. If the lock is already held
* in write mode, the function will return -EBUSY. If the lock is held
* in vt or suspend mode, the function will sleep until these modes
* are unlocked.
*
* Returns:
* -EBUSY The lock was already held in write mode.
* -ERESTARTSYS If interrupted by a signal and interruptible is true.
*/
extern int ttm_read_trylock(struct ttm_lock *lock, bool interruptible);
/**
* ttm_write_unlock
*
* @lock: Pointer to a struct ttm_lock
*
* Releases a write lock.
*/
extern void ttm_write_unlock(struct ttm_lock *lock);
/**
* ttm_write_lock
*
* @lock: Pointer to a struct ttm_lock
* @interruptible: Interruptible sleeping while waiting for a lock.
*
* Takes the lock in write mode.
* Returns:
* -ERESTARTSYS If interrupted by a signal and interruptible is true.
*/
extern int ttm_write_lock(struct ttm_lock *lock, bool interruptible);
/**
* ttm_lock_downgrade
*
* @lock: Pointer to a struct ttm_lock
*
* Downgrades a write lock to a read lock.
*/
extern void ttm_lock_downgrade(struct ttm_lock *lock);
/**
* ttm_suspend_lock
*
* @lock: Pointer to a struct ttm_lock
*
* Takes the lock in suspend mode. Excludes read and write mode.
*/
extern void ttm_suspend_lock(struct ttm_lock *lock);
/**
* ttm_suspend_unlock
*
* @lock: Pointer to a struct ttm_lock
*
* Releases a suspend lock
*/
extern void ttm_suspend_unlock(struct ttm_lock *lock);
/**
* ttm_vt_lock
*
* @lock: Pointer to a struct ttm_lock
* @interruptible: Interruptible sleeping while waiting for a lock.
* @tfile: Pointer to a struct ttm_object_file to register the lock with.
*
* Takes the lock in vt mode.
* Returns:
* -ERESTARTSYS If interrupted by a signal and interruptible is true.
* -ENOMEM: Out of memory when locking.
*/
extern int ttm_vt_lock(struct ttm_lock *lock, bool interruptible,
struct ttm_object_file *tfile);
/**
* ttm_vt_unlock
*
* @lock: Pointer to a struct ttm_lock
*
* Releases a vt lock.
* Returns:
* -EINVAL If the lock was not held.
*/
extern int ttm_vt_unlock(struct ttm_lock *lock);
/**
* ttm_write_unlock
*
* @lock: Pointer to a struct ttm_lock
*
* Releases a write lock.
*/
extern void ttm_write_unlock(struct ttm_lock *lock);
/**
* ttm_write_lock
*
* @lock: Pointer to a struct ttm_lock
* @interruptible: Interruptible sleeping while waiting for a lock.
*
* Takes the lock in write mode.
* Returns:
* -ERESTARTSYS If interrupted by a signal and interruptible is true.
*/
extern int ttm_write_lock(struct ttm_lock *lock, bool interruptible);
/**
* ttm_lock_set_kill
*
* @lock: Pointer to a struct ttm_lock
* @val: Boolean whether to kill processes taking the lock.
* @signal: Signal to send to the process taking the lock.
*
* The kill-when-taking-lock functionality is used to kill processes that keep
* on using the TTM functionality when its resources has been taken down, for
* example when the X server exits. A typical sequence would look like this:
* - X server takes lock in write mode.
* - ttm_lock_set_kill() is called with @val set to true.
* - As part of X server exit, TTM resources are taken down.
* - X server releases the lock on file release.
* - Another dri client wants to render, takes the lock and is killed.
*
*/
static inline void ttm_lock_set_kill(struct ttm_lock *lock, bool val,
int signal)
{
lock->kill_takers = val;
if (val)
lock->signal = signal;
}
#endif

354
include/drm/ttm/ttm_object.h
View File

@@ -1,354 +0,0 @@
/**************************************************************************
*
* Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/*
* Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
*/
/** @file ttm_object.h
*
* Base- and reference object implementation for the various
* ttm objects. Implements reference counting, minimal security checks
* and release on file close.
*/
#ifndef _TTM_OBJECT_H_
#define _TTM_OBJECT_H_
#include <linux/list.h>
#include <drm/drm_hashtab.h>
#include <linux/kref.h>
#include <linux/rcupdate.h>
#include <linux/dma-buf.h>
#include "ttm_memory.h"
/**
* enum ttm_ref_type
*
* Describes what type of reference a ref object holds.
*
* TTM_REF_USAGE is a simple refcount on a base object.
*
* TTM_REF_SYNCCPU_READ is a SYNCCPU_READ reference on a
* buffer object.
*
* TTM_REF_SYNCCPU_WRITE is a SYNCCPU_WRITE reference on a
* buffer object.
*
*/
enum ttm_ref_type {
TTM_REF_USAGE,
TTM_REF_SYNCCPU_READ,
TTM_REF_SYNCCPU_WRITE,
TTM_REF_NUM
};
/**
* enum ttm_object_type
*
* One entry per ttm object type.
* Device-specific types should use the
* ttm_driver_typex types.
*/
enum ttm_object_type {
ttm_fence_type,
ttm_buffer_type,
ttm_lock_type,
ttm_prime_type,
ttm_driver_type0 = 256,
ttm_driver_type1,
ttm_driver_type2,
ttm_driver_type3,
ttm_driver_type4,
ttm_driver_type5
};
struct ttm_object_file;
struct ttm_object_device;
/**
* struct ttm_base_object
*
* @hash: hash entry for the per-device object hash.
* @type: derived type this object is base class for.
* @shareable: Other ttm_object_files can access this object.
*
* @tfile: Pointer to ttm_object_file of the creator.
* NULL if the object was not created by a user request.
* (kernel object).
*
* @refcount: Number of references to this object, not
* including the hash entry. A reference to a base object can
* only be held by a ref object.
*
* @refcount_release: A function to be called when there are
* no more references to this object. This function should
* destroy the object (or make sure destruction eventually happens),
* and when it is called, the object has
* already been taken out of the per-device hash. The parameter
* "base" should be set to NULL by the function.
*
* @ref_obj_release: A function to be called when a reference object
* with another ttm_ref_type than TTM_REF_USAGE is deleted.
* This function may, for example, release a lock held by a user-space
* process.
*
* This struct is intended to be used as a base struct for objects that
* are visible to user-space. It provides a global name, race-safe
* access and refcounting, minimal access contol and hooks for unref actions.
*/
struct ttm_base_object {
struct rcu_head rhead;
struct drm_hash_item hash;
enum ttm_object_type object_type;
bool shareable;
struct ttm_object_file *tfile;
struct kref refcount;
void (*refcount_release) (struct ttm_base_object **base);
void (*ref_obj_release) (struct ttm_base_object *base,
enum ttm_ref_type ref_type);
};
/**
* struct ttm_prime_object - Modified base object that is prime-aware
*
* @base: struct ttm_base_object that we derive from
* @mutex: Mutex protecting the @dma_buf member.
* @size: Size of the dma_buf associated with this object
* @real_type: Type of the underlying object. Needed since we're setting
* the value of @base::object_type to ttm_prime_type
* @dma_buf: Non ref-coutned pointer to a struct dma_buf created from this
* object.
* @refcount_release: The underlying object's release method. Needed since
* we set @base::refcount_release to our own release method.
*/
struct ttm_prime_object {
struct ttm_base_object base;
struct mutex mutex;
size_t size;
enum ttm_object_type real_type;
struct dma_buf *dma_buf;
void (*refcount_release) (struct ttm_base_object **);
};
/**
* ttm_base_object_init
*
* @tfile: Pointer to a struct ttm_object_file.
* @base: The struct ttm_base_object to initialize.
* @shareable: This object is shareable with other applcations.
* (different @tfile pointers.)
* @type: The object type.
* @refcount_release: See the struct ttm_base_object description.
* @ref_obj_release: See the struct ttm_base_object description.
*
* Initializes a struct ttm_base_object.
*/
extern int ttm_base_object_init(struct ttm_object_file *tfile,
struct ttm_base_object *base,
bool shareable,
enum ttm_object_type type,
void (*refcount_release) (struct ttm_base_object
**),
void (*ref_obj_release) (struct ttm_base_object
*,
enum ttm_ref_type
ref_type));
/**
* ttm_base_object_lookup
*
* @tfile: Pointer to a struct ttm_object_file.
* @key: Hash key
*
* Looks up a struct ttm_base_object with the key @key.
*/
extern struct ttm_base_object *ttm_base_object_lookup(struct ttm_object_file
*tfile, uint32_t key);
/**
* ttm_base_object_lookup_for_ref
*
* @tdev: Pointer to a struct ttm_object_device.
* @key: Hash key
*
* Looks up a struct ttm_base_object with the key @key.
* This function should only be used when the struct tfile associated with the
* caller doesn't yet have a reference to the base object.
*/
extern struct ttm_base_object *
ttm_base_object_lookup_for_ref(struct ttm_object_device *tdev, uint32_t key);
/**
* ttm_base_object_unref
*
* @p_base: Pointer to a pointer referencing a struct ttm_base_object.
*
* Decrements the base object refcount and clears the pointer pointed to by
* p_base.
*/
extern void ttm_base_object_unref(struct ttm_base_object **p_base);
/**
* ttm_ref_object_add.
*
* @tfile: A struct ttm_object_file representing the application owning the
* ref_object.
* @base: The base object to reference.
* @ref_type: The type of reference.
* @existed: Upon completion, indicates that an identical reference object
* already existed, and the refcount was upped on that object instead.
* @require_existed: Fail with -EPERM if an identical ref object didn't
* already exist.
*
* Checks that the base object is shareable and adds a ref object to it.
*
* Adding a ref object to a base object is basically like referencing the
* base object, but a user-space application holds the reference. When the
* file corresponding to @tfile is closed, all its reference objects are
* deleted. A reference object can have different types depending on what
* it's intended for. It can be refcounting to prevent object destruction,
* When user-space takes a lock, it can add a ref object to that lock to
* make sure the lock is released if the application dies. A ref object
* will hold a single reference on a base object.
*/
extern int ttm_ref_object_add(struct ttm_object_file *tfile,
struct ttm_base_object *base,
enum ttm_ref_type ref_type, bool *existed,
bool require_existed);
extern bool ttm_ref_object_exists(struct ttm_object_file *tfile,
struct ttm_base_object *base);
/**
* ttm_ref_object_base_unref
*
* @key: Key representing the base object.
* @ref_type: Ref type of the ref object to be dereferenced.
*
* Unreference a ref object with type @ref_type
* on the base object identified by @key. If there are no duplicate
* references, the ref object will be destroyed and the base object
* will be unreferenced.
*/
extern int ttm_ref_object_base_unref(struct ttm_object_file *tfile,
unsigned long key,
enum ttm_ref_type ref_type);
/**
* ttm_object_file_init - initialize a struct ttm_object file
*
* @tdev: A struct ttm_object device this file is initialized on.
* @hash_order: Order of the hash table used to hold the reference objects.
*
* This is typically called by the file_ops::open function.
*/
extern struct ttm_object_file *ttm_object_file_init(struct ttm_object_device
*tdev,
unsigned int hash_order);
/**
* ttm_object_file_release - release data held by a ttm_object_file
*
* @p_tfile: Pointer to pointer to the ttm_object_file object to release.
* *p_tfile will be set to NULL by this function.
*
* Releases all data associated by a ttm_object_file.
* Typically called from file_ops::release. The caller must
* ensure that there are no concurrent users of tfile.
*/
extern void ttm_object_file_release(struct ttm_object_file **p_tfile);
/**
* ttm_object device init - initialize a struct ttm_object_device
*
* @mem_glob: struct ttm_mem_global for memory accounting.
* @hash_order: Order of hash table used to hash the base objects.
* @ops: DMA buf ops for prime objects of this device.
*
* This function is typically called on device initialization to prepare
* data structures needed for ttm base and ref objects.
*/
extern struct ttm_object_device *
ttm_object_device_init(struct ttm_mem_global *mem_glob,
unsigned int hash_order,
const struct dma_buf_ops *ops);
/**
* ttm_object_device_release - release data held by a ttm_object_device
*
* @p_tdev: Pointer to pointer to the ttm_object_device object to release.
* *p_tdev will be set to NULL by this function.
*
* Releases all data associated by a ttm_object_device.
* Typically called from driver::unload before the destruction of the
* device private data structure.
*/
extern void ttm_object_device_release(struct ttm_object_device **p_tdev);
#define ttm_base_object_kfree(__object, __base)\
kfree_rcu(__object, __base.rhead)
extern int ttm_prime_object_init(struct ttm_object_file *tfile,
size_t size,
struct ttm_prime_object *prime,
bool shareable,
enum ttm_object_type type,
void (*refcount_release)
(struct ttm_base_object **),
void (*ref_obj_release)
(struct ttm_base_object *,
enum ttm_ref_type ref_type));
static inline enum ttm_object_type
ttm_base_object_type(struct ttm_base_object *base)
{
return (base->object_type == ttm_prime_type) ?
container_of(base, struct ttm_prime_object, base)->real_type :
base->object_type;
}
extern int ttm_prime_fd_to_handle(struct ttm_object_file *tfile,
int fd, u32 *handle);
extern int ttm_prime_handle_to_fd(struct ttm_object_file *tfile,
uint32_t handle, uint32_t flags,
int *prime_fd);
#define ttm_prime_object_kfree(__obj, __prime) \
kfree_rcu(__obj, __prime.base.rhead)
#endif

119
include/dt-bindings/clock/am3.h
View File

@@ -16,6 +16,8 @@
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
@@ -105,4 +107,121 @@
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
/* XXX: Compatibility part end */
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
/* l3s clocks */
#define AM3_L3S_CLKCTRL_OFFSET 0x1c
#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
/* l3 clocks */
#define AM3_L3_CLKCTRL_OFFSET 0x24
#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
/* l4hs clocks */
#define AM3_L4HS_CLKCTRL_OFFSET 0x120
#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
/* pruss_ocp clocks */
#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
/* cpsw_125mhz clocks */
#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
/* lcdc clocks */
#define AM3_LCDC_CLKCTRL_OFFSET 0x18
#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
/* clk_24mhz clocks */
#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
/* l3_aon clocks */
#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
/* l4_wkup_aon clocks */
#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
/* mpu clocks */
#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
#endif

132
include/dt-bindings/clock/am4.h
View File

@@ -16,6 +16,8 @@
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_wkup clocks */
#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
@@ -110,4 +112,134 @@
#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
/* XXX: Compatibility part end. */
/* l3s_tsc clocks */
#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
/* l4_wkup_aon clocks */
#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
/* l4_wkup clocks */
#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
/* mpu clocks */
#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* gfx_l3 clocks */
#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_rtc clocks */
#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l3 clocks */
#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
/* l3s clocks */
#define AM4_L3S_CLKCTRL_OFFSET 0x68
#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
/* pruss_ocp clocks */
#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
/* l4ls clocks */
#define AM4_L4LS_CLKCTRL_OFFSET 0x420
#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
/* emif clocks */
#define AM4_EMIF_CLKCTRL_OFFSET 0x720
#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
/* dss clocks */
#define AM4_DSS_CLKCTRL_OFFSET 0xa20
#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
/* cpsw_125mhz clocks */
#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
#endif

15
include/dt-bindings/clock/at91.h
View File

@@ -9,6 +9,20 @@
#ifndef _DT_BINDINGS_CLK_AT91_H
#define _DT_BINDINGS_CLK_AT91_H
#define PMC_TYPE_CORE 0
#define PMC_TYPE_SYSTEM 1
#define PMC_TYPE_PERIPHERAL 2
#define PMC_TYPE_GCK 3
#define PMC_SLOW 0
#define PMC_MCK 1
#define PMC_UTMI 2
#define PMC_MAIN 3
#define PMC_MCK2 4
#define PMC_I2S0_MUX 5
#define PMC_I2S1_MUX 6
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
#define AT91_PMC_LOCKA 1 /* PLLA Lock */
#define AT91_PMC_LOCKB 2 /* PLLB Lock */
@@ -19,5 +33,6 @@
#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
#endif
#endif

326
include/dt-bindings/clock/dra7.h
View File

@@ -16,19 +16,21 @@
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
@@ -99,65 +101,65 @@
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@@ -170,4 +172,192 @@
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* XXX: Compatibility part end. */
/* mpu clocks */
#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dsp1 clocks */
#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu1 clocks */
#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x50
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
/* dsp2 clocks */
#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
/* l3main1 clocks */
#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
/* ipu2 clocks */
#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dma clocks */
#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
/* l4cfg clocks */
#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* l3instr clocks */
#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* l3init clocks */
#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* pcie clocks */
#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0
#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
/* gmac clocks */
#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0
#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x28
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
/* l4sec clocks */
#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0
#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
/* l4per2 clocks */
#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18)
#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20)
#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138)
#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160)
#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190)
#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198)
#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204)
#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208)
/* l4per3 clocks */
#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14
#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
/* wkupaon clocks */
#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
#endif

30
include/dt-bindings/clock/exynos4.h
View File

@@ -187,32 +187,6 @@
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
#define CLK_PIXELASYNCM0 351
#define CLK_PIXELASYNCM1 352
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
#define CLK_PPMUISPX 355 /* Exynos4x12 only */
#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
#define CLK_FIMC_FD 359 /* Exynos4x12 only */
#define CLK_MCUISP 360 /* Exynos4x12 only */
#define CLK_GICISP 361 /* Exynos4x12 only */
#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
#define CLK_SMMU_FD 364 /* Exynos4x12 only */
#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
#define CLK_PWM_ISP 372 /* Exynos4x12 only */
#define CLK_WDT_ISP 373 /* Exynos4x12 only */
#define CLK_UART_ISP 374 /* Exynos4x12 only */
#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
@@ -254,10 +228,6 @@
#define CLK_PPMUACP 415
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
#define CLK_DIV_ACP 456

348
include/dt-bindings/clock/hi3670-clock.h Normal file
View File

@@ -0,0 +1,348 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree binding constants for HiSilicon Hi3670 SoC
*
* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
* Copyright (c) 2018 Linaro Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_HI3670_H
#define __DT_BINDINGS_CLOCK_HI3670_H
/* clk in stub clock */
#define HI3670_CLK_STUB_CLUSTER0 0
#define HI3670_CLK_STUB_CLUSTER1 1
#define HI3670_CLK_STUB_GPU 2
#define HI3670_CLK_STUB_DDR 3
#define HI3670_CLK_STUB_DDR_VOTE 4
#define HI3670_CLK_STUB_DDR_LIMIT 5
#define HI3670_CLK_STUB_NUM 6
/* clk in crg clock */
#define HI3670_CLKIN_SYS 0
#define HI3670_CLKIN_REF 1
#define HI3670_CLK_FLL_SRC 2
#define HI3670_CLK_PPLL0 3
#define HI3670_CLK_PPLL1 4
#define HI3670_CLK_PPLL2 5
#define HI3670_CLK_PPLL3 6
#define HI3670_CLK_PPLL4 7
#define HI3670_CLK_PPLL6 8
#define HI3670_CLK_PPLL7 9
#define HI3670_CLK_PPLL_PCIE 10
#define HI3670_CLK_PCIEPLL_REV 11
#define HI3670_CLK_SCPLL 12
#define HI3670_PCLK 13
#define HI3670_CLK_UART0_DBG 14
#define HI3670_CLK_UART6 15
#define HI3670_OSC32K 16
#define HI3670_OSC19M 17
#define HI3670_CLK_480M 18
#define HI3670_CLK_INVALID 19
#define HI3670_CLK_DIV_SYSBUS 20
#define HI3670_CLK_FACTOR_MMC 21
#define HI3670_CLK_SD_SYS 22
#define HI3670_CLK_SDIO_SYS 23
#define HI3670_CLK_DIV_A53HPM 24
#define HI3670_CLK_DIV_320M 25
#define HI3670_PCLK_GATE_UART0 26
#define HI3670_CLK_FACTOR_UART0 27
#define HI3670_CLK_FACTOR_USB3PHY_PLL 28
#define HI3670_CLK_GATE_ABB_USB 29
#define HI3670_CLK_GATE_UFSPHY_REF 30
#define HI3670_ICS_VOLT_HIGH 31
#define HI3670_ICS_VOLT_MIDDLE 32
#define HI3670_VENC_VOLT_HOLD 33
#define HI3670_VDEC_VOLT_HOLD 34
#define HI3670_EDC_VOLT_HOLD 35
#define HI3670_CLK_ISP_SNCLK_FAC 36
#define HI3670_CLK_FACTOR_RXDPHY 37
#define HI3670_AUTODIV_SYSBUS 38
#define HI3670_AUTODIV_EMMC0BUS 39
#define HI3670_PCLK_ANDGT_MMC1_PCIE 40
#define HI3670_CLK_GATE_VCODECBUS_GT 41
#define HI3670_CLK_ANDGT_SD 42
#define HI3670_CLK_SD_SYS_GT 43
#define HI3670_CLK_ANDGT_SDIO 44
#define HI3670_CLK_SDIO_SYS_GT 45
#define HI3670_CLK_A53HPM_ANDGT 46
#define HI3670_CLK_320M_PLL_GT 47
#define HI3670_CLK_ANDGT_UARTH 48
#define HI3670_CLK_ANDGT_UARTL 49
#define HI3670_CLK_ANDGT_UART0 50
#define HI3670_CLK_ANDGT_SPI 51
#define HI3670_CLK_ANDGT_PCIEAXI 52
#define HI3670_CLK_DIV_AO_ASP_GT 53
#define HI3670_CLK_GATE_CSI_TRANS 54
#define HI3670_CLK_GATE_DSI_TRANS 55
#define HI3670_CLK_ANDGT_PTP 56
#define HI3670_CLK_ANDGT_OUT0 57
#define HI3670_CLK_ANDGT_OUT1 58
#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
#define HI3670_CLK_ANDGT_VDEC 60
#define HI3670_CLK_ANDGT_VENC 61
#define HI3670_CLK_ISP_SNCLK_ANGT 62
#define HI3670_CLK_ANDGT_RXDPHY 63
#define HI3670_CLK_ANDGT_ICS 64
#define HI3670_AUTODIV_DMABUS 65
#define HI3670_CLK_MUX_SYSBUS 66
#define HI3670_CLK_MUX_VCODECBUS 67
#define HI3670_CLK_MUX_SD_SYS 68
#define HI3670_CLK_MUX_SD_PLL 69
#define HI3670_CLK_MUX_SDIO_SYS 70
#define HI3670_CLK_MUX_SDIO_PLL 71
#define HI3670_CLK_MUX_A53HPM 72
#define HI3670_CLK_MUX_320M 73
#define HI3670_CLK_MUX_UARTH 74
#define HI3670_CLK_MUX_UARTL 75
#define HI3670_CLK_MUX_UART0 76
#define HI3670_CLK_MUX_I2C 77
#define HI3670_CLK_MUX_SPI 78
#define HI3670_CLK_MUX_PCIEAXI 79
#define HI3670_CLK_MUX_AO_ASP 80
#define HI3670_CLK_MUX_VDEC 81
#define HI3670_CLK_MUX_VENC 82
#define HI3670_CLK_ISP_SNCLK_MUX0 83
#define HI3670_CLK_ISP_SNCLK_MUX1 84
#define HI3670_CLK_ISP_SNCLK_MUX2 85
#define HI3670_CLK_MUX_RXDPHY_CFG 86
#define HI3670_CLK_MUX_ICS 87
#define HI3670_CLK_DIV_CFGBUS 88
#define HI3670_CLK_DIV_MMC0BUS 89
#define HI3670_CLK_DIV_MMC1BUS 90
#define HI3670_PCLK_DIV_MMC1_PCIE 91
#define HI3670_CLK_DIV_VCODECBUS 92
#define HI3670_CLK_DIV_SD 93
#define HI3670_CLK_DIV_SDIO 94
#define HI3670_CLK_DIV_UARTH 95
#define HI3670_CLK_DIV_UARTL 96
#define HI3670_CLK_DIV_UART0 97
#define HI3670_CLK_DIV_I2C 98
#define HI3670_CLK_DIV_SPI 99
#define HI3670_CLK_DIV_PCIEAXI 100
#define HI3670_CLK_DIV_AO_ASP 101
#define HI3670_CLK_DIV_CSI_TRANS 102
#define HI3670_CLK_DIV_DSI_TRANS 103
#define HI3670_CLK_DIV_PTP 104
#define HI3670_CLK_DIV_CLKOUT0_PLL 105
#define HI3670_CLK_DIV_CLKOUT1_PLL 106
#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
#define HI3670_CLK_DIV_VDEC 108
#define HI3670_CLK_DIV_VENC 109
#define HI3670_CLK_ISP_SNCLK_DIV0 110
#define HI3670_CLK_ISP_SNCLK_DIV1 111
#define HI3670_CLK_ISP_SNCLK_DIV2 112
#define HI3670_CLK_DIV_ICS 113
#define HI3670_PPLL1_EN_ACPU 114
#define HI3670_PPLL2_EN_ACPU 115
#define HI3670_PPLL3_EN_ACPU 116
#define HI3670_PPLL1_GT_CPU 117
#define HI3670_PPLL2_GT_CPU 118
#define HI3670_PPLL3_GT_CPU 119
#define HI3670_CLK_GATE_PPLL2_MEDIA 120
#define HI3670_CLK_GATE_PPLL3_MEDIA 121
#define HI3670_CLK_GATE_PPLL4_MEDIA 122
#define HI3670_CLK_GATE_PPLL6_MEDIA 123
#define HI3670_CLK_GATE_PPLL7_MEDIA 124
#define HI3670_PCLK_GPIO0 125
#define HI3670_PCLK_GPIO1 126
#define HI3670_PCLK_GPIO2 127
#define HI3670_PCLK_GPIO3 128
#define HI3670_PCLK_GPIO4 129
#define HI3670_PCLK_GPIO5 130
#define HI3670_PCLK_GPIO6 131
#define HI3670_PCLK_GPIO7 132
#define HI3670_PCLK_GPIO8 133
#define HI3670_PCLK_GPIO9 134
#define HI3670_PCLK_GPIO10 135
#define HI3670_PCLK_GPIO11 136
#define HI3670_PCLK_GPIO12 137
#define HI3670_PCLK_GPIO13 138
#define HI3670_PCLK_GPIO14 139
#define HI3670_PCLK_GPIO15 140
#define HI3670_PCLK_GPIO16 141
#define HI3670_PCLK_GPIO17 142
#define HI3670_PCLK_GPIO20 143
#define HI3670_PCLK_GPIO21 144
#define HI3670_PCLK_GATE_DSI0 145
#define HI3670_PCLK_GATE_DSI1 146
#define HI3670_HCLK_GATE_USB3OTG 147
#define HI3670_ACLK_GATE_USB3DVFS 148
#define HI3670_HCLK_GATE_SDIO 149
#define HI3670_PCLK_GATE_PCIE_SYS 150
#define HI3670_PCLK_GATE_PCIE_PHY 151
#define HI3670_PCLK_GATE_MMC1_PCIE 152
#define HI3670_PCLK_GATE_MMC0_IOC 153
#define HI3670_PCLK_GATE_MMC1_IOC 154
#define HI3670_CLK_GATE_DMAC 155
#define HI3670_CLK_GATE_VCODECBUS2DDR 156
#define HI3670_CLK_CCI400_BYPASS 157
#define HI3670_CLK_GATE_CCI400 158
#define HI3670_CLK_GATE_SD 159
#define HI3670_HCLK_GATE_SD 160
#define HI3670_CLK_GATE_SDIO 161
#define HI3670_CLK_GATE_A57HPM 162
#define HI3670_CLK_GATE_A53HPM 163
#define HI3670_CLK_GATE_PA_A53 164
#define HI3670_CLK_GATE_PA_A57 165
#define HI3670_CLK_GATE_PA_G3D 166
#define HI3670_CLK_GATE_GPUHPM 167
#define HI3670_CLK_GATE_PERIHPM 168
#define HI3670_CLK_GATE_AOHPM 169
#define HI3670_CLK_GATE_UART1 170
#define HI3670_CLK_GATE_UART4 171
#define HI3670_PCLK_GATE_UART1 172
#define HI3670_PCLK_GATE_UART4 173
#define HI3670_CLK_GATE_UART2 174
#define HI3670_CLK_GATE_UART5 175
#define HI3670_PCLK_GATE_UART2 176
#define HI3670_PCLK_GATE_UART5 177
#define HI3670_CLK_GATE_UART0 178
#define HI3670_CLK_GATE_I2C3 179
#define HI3670_CLK_GATE_I2C4 180
#define HI3670_CLK_GATE_I2C7 181
#define HI3670_PCLK_GATE_I2C3 182
#define HI3670_PCLK_GATE_I2C4 183
#define HI3670_PCLK_GATE_I2C7 184
#define HI3670_CLK_GATE_SPI1 185
#define HI3670_CLK_GATE_SPI4 186
#define HI3670_PCLK_GATE_SPI1 187
#define HI3670_PCLK_GATE_SPI4 188
#define HI3670_CLK_GATE_USB3OTG_REF 189
#define HI3670_CLK_GATE_USB2PHY_REF 190
#define HI3670_CLK_GATE_PCIEAUX 191
#define HI3670_ACLK_GATE_PCIE 192
#define HI3670_CLK_GATE_MMC1_PCIEAXI 193
#define HI3670_CLK_GATE_PCIEPHY_REF 194
#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
#define HI3670_CLK_GATE_PCIEIO 196
#define HI3670_CLK_GATE_PCIE_HP 197
#define HI3670_CLK_GATE_AO_ASP 198
#define HI3670_PCLK_GATE_PCTRL 199
#define HI3670_CLK_CSI_TRANS_GT 200
#define HI3670_CLK_DSI_TRANS_GT 201
#define HI3670_CLK_GATE_PWM 202
#define HI3670_ABB_AUDIO_EN0 203
#define HI3670_ABB_AUDIO_EN1 204
#define HI3670_ABB_AUDIO_GT_EN0 205
#define HI3670_ABB_AUDIO_GT_EN1 206
#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
#define HI3670_PERI_VOLT_HOLD 208
#define HI3670_PERI_VOLT_MIDDLE 209
#define HI3670_CLK_GATE_ISP_SNCLK0 210
#define HI3670_CLK_GATE_ISP_SNCLK1 211
#define HI3670_CLK_GATE_ISP_SNCLK2 212
#define HI3670_CLK_GATE_RXDPHY0_CFG 213
#define HI3670_CLK_GATE_RXDPHY1_CFG 214
#define HI3670_CLK_GATE_RXDPHY2_CFG 215
#define HI3670_CLK_GATE_TXDPHY0_CFG 216
#define HI3670_CLK_GATE_TXDPHY0_REF 217
#define HI3670_CLK_GATE_TXDPHY1_CFG 218
#define HI3670_CLK_GATE_TXDPHY1_REF 219
#define HI3670_CLK_GATE_MEDIA_TCXO 220
/* clk in sctrl */
#define HI3670_CLK_ANDGT_IOPERI 0
#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
#define HI3670_CLK_ANGT_ASP_SUBSYS 2
#define HI3670_CLK_MUX_UFS_SUBSYS 3
#define HI3670_CLK_MUX_CLKOUT0 4
#define HI3670_CLK_MUX_CLKOUT1 5
#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
#define HI3670_CLK_MUX_ASP_PLL 7
#define HI3670_CLK_DIV_AOBUS 8
#define HI3670_CLK_DIV_UFS_SUBSYS 9
#define HI3670_CLK_DIV_IOPERI 10
#define HI3670_CLK_DIV_CLKOUT0_TCXO 11
#define HI3670_CLK_DIV_CLKOUT1_TCXO 12
#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
#define HI3670_CLK_DIV_ASP_SUBSYS 14
#define HI3670_PPLL0_EN_ACPU 15
#define HI3670_PPLL0_GT_CPU 16
#define HI3670_CLK_GATE_PPLL0_MEDIA 17
#define HI3670_PCLK_GPIO18 18
#define HI3670_PCLK_GPIO19 19
#define HI3670_CLK_GATE_SPI 20
#define HI3670_PCLK_GATE_SPI 21
#define HI3670_CLK_GATE_UFS_SUBSYS 22
#define HI3670_CLK_GATE_UFSIO_REF 23
#define HI3670_PCLK_AO_GPIO0 24
#define HI3670_PCLK_AO_GPIO1 25
#define HI3670_PCLK_AO_GPIO2 26
#define HI3670_PCLK_AO_GPIO3 27
#define HI3670_PCLK_AO_GPIO4 28
#define HI3670_PCLK_AO_GPIO5 29
#define HI3670_PCLK_AO_GPIO6 30
#define HI3670_CLK_GATE_OUT0 31
#define HI3670_CLK_GATE_OUT1 32
#define HI3670_PCLK_GATE_SYSCNT 33
#define HI3670_CLK_GATE_SYSCNT 34
#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
#define HI3670_CLK_GATE_ASP_SUBSYS 36
#define HI3670_CLK_GATE_ASP_TCXO 37
#define HI3670_CLK_GATE_DP_AUDIO_PLL 38
/* clk in pmuctrl */
#define HI3670_GATE_ABB_192 0
/* clk in pctrl */
#define HI3670_GATE_UFS_TCXO_EN 0
#define HI3670_GATE_USB_TCXO_EN 1
/* clk in iomcu */
#define HI3670_CLK_GATE_I2C0 0
#define HI3670_CLK_GATE_I2C1 1
#define HI3670_CLK_GATE_I2C2 2
#define HI3670_CLK_GATE_SPI0 3
#define HI3670_CLK_GATE_SPI2 4
#define HI3670_CLK_GATE_UART3 5
#define HI3670_CLK_I2C0_GATE_IOMCU 6
#define HI3670_CLK_I2C1_GATE_IOMCU 7
#define HI3670_CLK_I2C2_GATE_IOMCU 8
#define HI3670_CLK_SPI0_GATE_IOMCU 9
#define HI3670_CLK_SPI2_GATE_IOMCU 10
#define HI3670_CLK_UART3_GATE_IOMCU 11
#define HI3670_CLK_GATE_PERI0_IOMCU 12
/* clk in media1 */
#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
#define HI3670_CLK_ANDGT_EDC0 1
#define HI3670_CLK_ANDGT_LDI0 2
#define HI3670_CLK_ANDGT_LDI1 3
#define HI3670_CLK_MMBUF_PLL_ANDGT 4
#define HI3670_PCLK_MMBUF_ANDGT 5
#define HI3670_CLK_MUX_VIVOBUS 6
#define HI3670_CLK_MUX_EDC0 7
#define HI3670_CLK_MUX_LDI0 8
#define HI3670_CLK_MUX_LDI1 9
#define HI3670_CLK_SW_MMBUF 10
#define HI3670_CLK_DIV_VIVOBUS 11
#define HI3670_CLK_DIV_EDC0 12
#define HI3670_CLK_DIV_LDI0 13
#define HI3670_CLK_DIV_LDI1 14
#define HI3670_ACLK_DIV_MMBUF 15
#define HI3670_PCLK_DIV_MMBUF 16
#define HI3670_ACLK_GATE_NOC_DSS 17
#define HI3670_PCLK_GATE_NOC_DSS_CFG 18
#define HI3670_PCLK_GATE_MMBUF_CFG 19
#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
#define HI3670_PCLK_GATE_DSS 22
#define HI3670_ACLK_GATE_DSS 23
#define HI3670_CLK_GATE_VIVOBUSFREQ 24
#define HI3670_CLK_GATE_EDC0 25
#define HI3670_CLK_GATE_LDI0 26
#define HI3670_CLK_GATE_LDI1FREQ 27
#define HI3670_CLK_GATE_BRG 28
#define HI3670_ACLK_GATE_ASC 29
#define HI3670_CLK_GATE_DSS_AXI_MM 30
#define HI3670_CLK_GATE_MMBUF 31
#define HI3670_PCLK_GATE_MMBUF 32
#define HI3670_CLK_GATE_ATDIV_VIVO 33
/* clk in media2 */
#define HI3670_CLK_GATE_VDECFREQ 0
#define HI3670_CLK_GATE_VENCFREQ 1
#define HI3670_CLK_GATE_ICSFREQ 2
#endif /* __DT_BINDINGS_CLOCK_HI3670_H */

3
include/dt-bindings/clock/imx6qdl-clock.h
View File

@@ -273,6 +273,7 @@
#define IMX6QDL_CLK_MLB_PODF 260
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_END 263
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_END 264
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

4
include/dt-bindings/clock/imx6sl-clock.h
View File

@@ -175,6 +175,8 @@
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_SPDIF_GCLK 164
#define IMX6SL_CLK_END 165
#define IMX6SL_CLK_MMDC_P0_IPG 165
#define IMX6SL_CLK_MMDC_P1_IPG 166
#define IMX6SL_CLK_END 167
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

3
include/dt-bindings/clock/imx6sll-clock.h
View File

@@ -203,7 +203,8 @@
#define IMX6SLL_CLK_GPIO4 176
#define IMX6SLL_CLK_GPIO5 177
#define IMX6SLL_CLK_GPIO6 178
#define IMX6SLL_CLK_MMDC_P1_IPG 179
#define IMX6SLL_CLK_END 179
#define IMX6SLL_CLK_END 180
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */

3
include/dt-bindings/clock/imx6sx-clock.h
View File

@@ -279,6 +279,7 @@
#define IMX6SX_CLK_LVDS2_OUT 266
#define IMX6SX_CLK_LVDS2_IN 267
#define IMX6SX_CLK_ANACLK2 268
#define IMX6SX_CLK_CLK_END 269
#define IMX6SX_CLK_MMDC_P1_IPG 269
#define IMX6SX_CLK_CLK_END 270
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

3
include/dt-bindings/clock/imx6ul-clock.h
View File

@@ -259,7 +259,8 @@
#define IMX6UL_CLK_GPIO3 246
#define IMX6UL_CLK_GPIO4 247
#define IMX6UL_CLK_GPIO5 248
#define IMX6UL_CLK_MMDC_P1_IPG 249
#define IMX6UL_CLK_END 249
#define IMX6UL_CLK_END 250
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

35
include/dt-bindings/clock/jz4725b-cgu.h Normal file
View File

@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
*/
#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
#define JZ4725B_CLK_EXT 0
#define JZ4725B_CLK_OSC32K 1
#define JZ4725B_CLK_PLL 2
#define JZ4725B_CLK_PLL_HALF 3
#define JZ4725B_CLK_CCLK 4
#define JZ4725B_CLK_HCLK 5
#define JZ4725B_CLK_PCLK 6
#define JZ4725B_CLK_MCLK 7
#define JZ4725B_CLK_IPU 8
#define JZ4725B_CLK_LCD 9
#define JZ4725B_CLK_I2S 10
#define JZ4725B_CLK_SPI 11
#define JZ4725B_CLK_MMC_MUX 12
#define JZ4725B_CLK_UDC 13
#define JZ4725B_CLK_UART 14
#define JZ4725B_CLK_DMA 15
#define JZ4725B_CLK_ADC 16
#define JZ4725B_CLK_I2C 17
#define JZ4725B_CLK_AIC 18
#define JZ4725B_CLK_MMC0 19
#define JZ4725B_CLK_MMC1 20
#define JZ4725B_CLK_BCH 21
#define JZ4725B_CLK_TCU 22
#define JZ4725B_CLK_EXT512 23
#define JZ4725B_CLK_RTC 24
#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */

5
include/dt-bindings/clock/maxim,max77686.h
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@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77686 PMIC.
*/

5
include/dt-bindings/clock/maxim,max77802.h
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@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77802 PMIC.
*/

116
include/dt-bindings/clock/qcom,camcc-sdm845.h Normal file
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@@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
/* CAM_CC clock registers */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_AXI_CLK 2
#define CAM_CC_BPS_CLK 3
#define CAM_CC_BPS_CLK_SRC 4
#define CAM_CC_CAMNOC_ATB_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK 6
#define CAM_CC_CCI_CLK 7
#define CAM_CC_CCI_CLK_SRC 8
#define CAM_CC_CPAS_AHB_CLK 9
#define CAM_CC_CPHY_RX_CLK_SRC 10
#define CAM_CC_CSI0PHYTIMER_CLK 11
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
#define CAM_CC_CSI1PHYTIMER_CLK 13
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
#define CAM_CC_CSI2PHYTIMER_CLK 15
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
#define CAM_CC_CSI3PHYTIMER_CLK 17
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
#define CAM_CC_CSIPHY0_CLK 19
#define CAM_CC_CSIPHY1_CLK 20
#define CAM_CC_CSIPHY2_CLK 21
#define CAM_CC_CSIPHY3_CLK 22
#define CAM_CC_FAST_AHB_CLK_SRC 23
#define CAM_CC_FD_CORE_CLK 24
#define CAM_CC_FD_CORE_CLK_SRC 25
#define CAM_CC_FD_CORE_UAR_CLK 26
#define CAM_CC_ICP_APB_CLK 27
#define CAM_CC_ICP_ATB_CLK 28
#define CAM_CC_ICP_CLK 29
#define CAM_CC_ICP_CLK_SRC 30
#define CAM_CC_ICP_CTI_CLK 31
#define CAM_CC_ICP_TS_CLK 32
#define CAM_CC_IFE_0_AXI_CLK 33
#define CAM_CC_IFE_0_CLK 34
#define CAM_CC_IFE_0_CLK_SRC 35
#define CAM_CC_IFE_0_CPHY_RX_CLK 36
#define CAM_CC_IFE_0_CSID_CLK 37
#define CAM_CC_IFE_0_CSID_CLK_SRC 38
#define CAM_CC_IFE_0_DSP_CLK 39
#define CAM_CC_IFE_1_AXI_CLK 40
#define CAM_CC_IFE_1_CLK 41
#define CAM_CC_IFE_1_CLK_SRC 42
#define CAM_CC_IFE_1_CPHY_RX_CLK 43
#define CAM_CC_IFE_1_CSID_CLK 44
#define CAM_CC_IFE_1_CSID_CLK_SRC 45
#define CAM_CC_IFE_1_DSP_CLK 46
#define CAM_CC_IFE_LITE_CLK 47
#define CAM_CC_IFE_LITE_CLK_SRC 48
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
#define CAM_CC_IFE_LITE_CSID_CLK 50
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
#define CAM_CC_IPE_0_AHB_CLK 52
#define CAM_CC_IPE_0_AREG_CLK 53
#define CAM_CC_IPE_0_AXI_CLK 54
#define CAM_CC_IPE_0_CLK 55
#define CAM_CC_IPE_0_CLK_SRC 56
#define CAM_CC_IPE_1_AHB_CLK 57
#define CAM_CC_IPE_1_AREG_CLK 58
#define CAM_CC_IPE_1_AXI_CLK 59
#define CAM_CC_IPE_1_CLK 60
#define CAM_CC_IPE_1_CLK_SRC 61
#define CAM_CC_JPEG_CLK 62
#define CAM_CC_JPEG_CLK_SRC 63
#define CAM_CC_LRME_CLK 64
#define CAM_CC_LRME_CLK_SRC 65
#define CAM_CC_MCLK0_CLK 66
#define CAM_CC_MCLK0_CLK_SRC 67
#define CAM_CC_MCLK1_CLK 68
#define CAM_CC_MCLK1_CLK_SRC 69
#define CAM_CC_MCLK2_CLK 70
#define CAM_CC_MCLK2_CLK_SRC 71
#define CAM_CC_MCLK3_CLK 72
#define CAM_CC_MCLK3_CLK_SRC 73
#define CAM_CC_PLL0 74
#define CAM_CC_PLL0_OUT_EVEN 75
#define CAM_CC_PLL1 76
#define CAM_CC_PLL1_OUT_EVEN 77
#define CAM_CC_PLL2 78
#define CAM_CC_PLL2_OUT_EVEN 79
#define CAM_CC_PLL3 80
#define CAM_CC_PLL3_OUT_EVEN 81
#define CAM_CC_SLOW_AHB_CLK_SRC 82
#define CAM_CC_SOC_AHB_CLK 83
#define CAM_CC_SYS_TMR_CLK 84
/* CAM_CC Resets */
#define TITAN_CAM_CC_CCI_BCR 0
#define TITAN_CAM_CC_CPAS_BCR 1
#define TITAN_CAM_CC_CSI0PHY_BCR 2
#define TITAN_CAM_CC_CSI1PHY_BCR 3
#define TITAN_CAM_CC_CSI2PHY_BCR 4
#define TITAN_CAM_CC_MCLK0_BCR 5
#define TITAN_CAM_CC_MCLK1_BCR 6
#define TITAN_CAM_CC_MCLK2_BCR 7
#define TITAN_CAM_CC_MCLK3_BCR 8
#define TITAN_CAM_CC_TITAN_TOP_BCR 9
/* CAM_CC GDSCRs */
#define BPS_GDSC 0
#define IPE_0_GDSC 1
#define IPE_1_GDSC 2
#define IFE_0_GDSC 3
#define IFE_1_GDSC 4
#define TITAN_TOP_GDSC 5
#endif

2
include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -319,5 +319,7 @@
#define CE3_SRC 303
#define CE3_CORE_CLK 304
#define CE3_H_CLK 305
#define PLL16 306
#define PLL17 307
#endif

9
include/dt-bindings/clock/qcom,gcc-msm8996.h
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@@ -235,6 +235,15 @@
#define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_EDP_CLKREF_CLK 221
#define GCC_MSS_CFG_AHB_CLK 222
#define GCC_MSS_Q6_BIMC_AXI_CLK 223
#define GCC_MSS_SNOC_AXI_CLK 224
#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
#define GCC_DCC_AHB_CLK 226
#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
#define GCC_MMSS_GPLL0_DIV_CLK 228
#define GCC_MSS_GPLL0_DIV_CLK 229
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1

165
include/dt-bindings/clock/qcom,gcc-qcs404.h Normal file
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@@ -0,0 +1,165 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
#define GCC_APSS_AHB_CLK_SRC 0
#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
#define GCC_BYTE0_CLK_SRC 18
#define GCC_EMAC_CLK_SRC 19
#define GCC_EMAC_PTP_CLK_SRC 20
#define GCC_ESC0_CLK_SRC 21
#define GCC_APSS_AHB_CLK 22
#define GCC_APSS_AXI_CLK 23
#define GCC_BIMC_APSS_AXI_CLK 24
#define GCC_BIMC_GFX_CLK 25
#define GCC_BIMC_MDSS_CLK 26
#define GCC_BLSP1_AHB_CLK 27
#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
#define GCC_BLSP1_UART0_APPS_CLK 38
#define GCC_BLSP1_UART1_APPS_CLK 39
#define GCC_BLSP1_UART2_APPS_CLK 40
#define GCC_BLSP1_UART3_APPS_CLK 41
#define GCC_BLSP2_AHB_CLK 42
#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
#define GCC_BLSP2_UART0_APPS_CLK 45
#define GCC_BOOT_ROM_AHB_CLK 46
#define GCC_DCC_CLK 47
#define GCC_GENI_IR_H_CLK 48
#define GCC_ETH_AXI_CLK 49
#define GCC_ETH_PTP_CLK 50
#define GCC_ETH_RGMII_CLK 51
#define GCC_ETH_SLAVE_AHB_CLK 52
#define GCC_GENI_IR_S_CLK 53
#define GCC_GP1_CLK 54
#define GCC_GP2_CLK 55
#define GCC_GP3_CLK 56
#define GCC_MDSS_AHB_CLK 57
#define GCC_MDSS_AXI_CLK 58
#define GCC_MDSS_BYTE0_CLK 59
#define GCC_MDSS_ESC0_CLK 60
#define GCC_MDSS_HDMI_APP_CLK 61
#define GCC_MDSS_HDMI_PCLK_CLK 62
#define GCC_MDSS_MDP_CLK 63
#define GCC_MDSS_PCLK0_CLK 64
#define GCC_MDSS_VSYNC_CLK 65
#define GCC_OXILI_AHB_CLK 66
#define GCC_OXILI_GFX3D_CLK 67
#define GCC_PCIE_0_AUX_CLK 68
#define GCC_PCIE_0_CFG_AHB_CLK 69
#define GCC_PCIE_0_MSTR_AXI_CLK 70
#define GCC_PCIE_0_PIPE_CLK 71
#define GCC_PCIE_0_SLV_AXI_CLK 72
#define GCC_PCNOC_USB2_CLK 73
#define GCC_PCNOC_USB3_CLK 74
#define GCC_PDM2_CLK 75
#define GCC_PDM_AHB_CLK 76
#define GCC_VSYNC_CLK_SRC 77
#define GCC_PRNG_AHB_CLK 78
#define GCC_PWM0_XO512_CLK 79
#define GCC_PWM1_XO512_CLK 80
#define GCC_PWM2_XO512_CLK 81
#define GCC_SDCC1_AHB_CLK 82
#define GCC_SDCC1_APPS_CLK 83
#define GCC_SDCC1_ICE_CORE_CLK 84
#define GCC_SDCC2_AHB_CLK 85
#define GCC_SDCC2_APPS_CLK 86
#define GCC_SYS_NOC_USB3_CLK 87
#define GCC_USB20_MOCK_UTMI_CLK 88
#define GCC_USB2A_PHY_SLEEP_CLK 89
#define GCC_USB30_MASTER_CLK 90
#define GCC_USB30_MOCK_UTMI_CLK 91
#define GCC_USB30_SLEEP_CLK 92
#define GCC_USB3_PHY_AUX_CLK 93
#define GCC_USB3_PHY_PIPE_CLK 94
#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
#define GCC_USB_HS_SYSTEM_CLK 96
#define GCC_GFX3D_CLK_SRC 97
#define GCC_GP1_CLK_SRC 98
#define GCC_GP2_CLK_SRC 99
#define GCC_GP3_CLK_SRC 100
#define GCC_GPLL0_OUT_MAIN 101
#define GCC_GPLL1_OUT_MAIN 102
#define GCC_GPLL3_OUT_MAIN 103
#define GCC_GPLL4_OUT_MAIN 104
#define GCC_HDMI_APP_CLK_SRC 105
#define GCC_HDMI_PCLK_CLK_SRC 106
#define GCC_MDP_CLK_SRC 107
#define GCC_PCIE_0_AUX_CLK_SRC 108
#define GCC_PCIE_0_PIPE_CLK_SRC 109
#define GCC_PCLK0_CLK_SRC 110
#define GCC_PDM2_CLK_SRC 111
#define GCC_SDCC1_APPS_CLK_SRC 112
#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
#define GCC_SDCC2_APPS_CLK_SRC 114
#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
#define GCC_USB30_MASTER_CLK_SRC 116
#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
#define GCC_USB3_PHY_AUX_CLK_SRC 118
#define GCC_USB_HS_SYSTEM_CLK_SRC 119
#define GCC_GPLL0_AO_CLK_SRC 120
#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
#define GCC_GPLL0_AO_OUT_MAIN 123
#define GCC_GPLL0_SLEEP_CLK_SRC 124
#define GCC_GPLL6 125
#define GCC_GPLL6_OUT_AUX 126
#define GCC_MDSS_MDP_VOTE_CLK 127
#define GCC_MDSS_ROTATOR_VOTE_CLK 128
#define GCC_BIMC_GPU_CLK 129
#define GCC_GTCU_AHB_CLK 130
#define GCC_GFX_TCU_CLK 131
#define GCC_GFX_TBU_CLK 132
#define GCC_SMMU_CFG_CLK 133
#define GCC_APSS_TCU_CLK 134
#define GCC_CRYPTO_AHB_CLK 135
#define GCC_CRYPTO_AXI_CLK 136
#define GCC_CRYPTO_CLK 137
#define GCC_MDP_TBU_CLK 138
#define GCC_QDSS_DAP_CLK 139
#define GCC_DCC_XO_CLK 140
#define GCC_GENI_IR_BCR 0
#define GCC_USB_HS_BCR 1
#define GCC_USB2_HS_PHY_ONLY_BCR 2
#define GCC_QUSB2_PHY_BCR 3
#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
#define GCC_USB2A_PHY_BCR 5
#define GCC_USB3_PHY_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB3PHY_PHY_BCR 8
#define GCC_PCIE_0_BCR 9
#define GCC_PCIE_0_PHY_BCR 10
#define GCC_PCIE_0_LINK_DOWN_BCR 11
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#endif

156
include/dt-bindings/clock/qcom,gcc-sdm660.h Normal file
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@@ -0,0 +1,156 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, Craig Tatlor.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
#define _DT_BINDINGS_CLK_MSM_GCC_660_H
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
#define BLSP1_UART1_APPS_CLK_SRC 8
#define BLSP1_UART2_APPS_CLK_SRC 9
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
#define BLSP2_UART1_APPS_CLK_SRC 18
#define BLSP2_UART2_APPS_CLK_SRC 19
#define GCC_AGGRE2_UFS_AXI_CLK 20
#define GCC_AGGRE2_USB3_AXI_CLK 21
#define GCC_BIMC_GFX_CLK 22
#define GCC_BIMC_HMSS_AXI_CLK 23
#define GCC_BIMC_MSS_Q6_AXI_CLK 24
#define GCC_BLSP1_AHB_CLK 25
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
#define GCC_BLSP1_UART1_APPS_CLK 34
#define GCC_BLSP1_UART2_APPS_CLK 35
#define GCC_BLSP2_AHB_CLK 36
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
#define GCC_BLSP2_UART1_APPS_CLK 45
#define GCC_BLSP2_UART2_APPS_CLK 46
#define GCC_BOOT_ROM_AHB_CLK 47
#define GCC_CFG_NOC_USB2_AXI_CLK 48
#define GCC_CFG_NOC_USB3_AXI_CLK 49
#define GCC_DCC_AHB_CLK 50
#define GCC_GP1_CLK 51
#define GCC_GP2_CLK 52
#define GCC_GP3_CLK 53
#define GCC_GPU_BIMC_GFX_CLK 54
#define GCC_GPU_CFG_AHB_CLK 55
#define GCC_GPU_GPLL0_CLK 56
#define GCC_GPU_GPLL0_DIV_CLK 57
#define GCC_HMSS_DVM_BUS_CLK 58
#define GCC_HMSS_RBCPR_CLK 59
#define GCC_MMSS_GPLL0_CLK 60
#define GCC_MMSS_GPLL0_DIV_CLK 61
#define GCC_MMSS_NOC_CFG_AHB_CLK 62
#define GCC_MMSS_SYS_NOC_AXI_CLK 63
#define GCC_MSS_CFG_AHB_CLK 64
#define GCC_MSS_GPLL0_DIV_CLK 65
#define GCC_MSS_MNOC_BIMC_AXI_CLK 66
#define GCC_MSS_Q6_BIMC_AXI_CLK 67
#define GCC_MSS_SNOC_AXI_CLK 68
#define GCC_PDM2_CLK 69
#define GCC_PDM_AHB_CLK 70
#define GCC_PRNG_AHB_CLK 71
#define GCC_QSPI_AHB_CLK 72
#define GCC_QSPI_SER_CLK 73
#define GCC_SDCC1_AHB_CLK 74
#define GCC_SDCC1_APPS_CLK 75
#define GCC_SDCC1_ICE_CORE_CLK 76
#define GCC_SDCC2_AHB_CLK 77
#define GCC_SDCC2_APPS_CLK 78
#define GCC_UFS_AHB_CLK 79
#define GCC_UFS_AXI_CLK 80
#define GCC_UFS_CLKREF_CLK 81
#define GCC_UFS_ICE_CORE_CLK 82
#define GCC_UFS_PHY_AUX_CLK 83
#define GCC_UFS_RX_SYMBOL_0_CLK 84
#define GCC_UFS_RX_SYMBOL_1_CLK 85
#define GCC_UFS_TX_SYMBOL_0_CLK 86
#define GCC_UFS_UNIPRO_CORE_CLK 87
#define GCC_USB20_MASTER_CLK 88
#define GCC_USB20_MOCK_UTMI_CLK 89
#define GCC_USB20_SLEEP_CLK 90
#define GCC_USB30_MASTER_CLK 91
#define GCC_USB30_MOCK_UTMI_CLK 92
#define GCC_USB30_SLEEP_CLK 93
#define GCC_USB3_CLKREF_CLK 94
#define GCC_USB3_PHY_AUX_CLK 95
#define GCC_USB3_PHY_PIPE_CLK 96
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
#define GP1_CLK_SRC 98
#define GP2_CLK_SRC 99
#define GP3_CLK_SRC 100
#define GPLL0 101
#define GPLL0_EARLY 102
#define GPLL1 103
#define GPLL1_EARLY 104
#define GPLL4 105
#define GPLL4_EARLY 106
#define HMSS_GPLL0_CLK_SRC 107
#define HMSS_GPLL4_CLK_SRC 108
#define HMSS_RBCPR_CLK_SRC 109
#define PDM2_CLK_SRC 110
#define QSPI_SER_CLK_SRC 111
#define SDCC1_APPS_CLK_SRC 112
#define SDCC1_ICE_CORE_CLK_SRC 113
#define SDCC2_APPS_CLK_SRC 114
#define UFS_AXI_CLK_SRC 115
#define UFS_ICE_CORE_CLK_SRC 116
#define UFS_PHY_AUX_CLK_SRC 117
#define UFS_UNIPRO_CORE_CLK_SRC 118
#define USB20_MASTER_CLK_SRC 119
#define USB20_MOCK_UTMI_CLK_SRC 120
#define USB30_MASTER_CLK_SRC 121
#define USB30_MOCK_UTMI_CLK_SRC 122
#define USB3_PHY_AUX_CLK_SRC 123
#define GPLL0_OUT_MSSCC 124
#define GCC_UFS_AXI_HW_CTL_CLK 125
#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
#define GCC_RX0_USB2_CLKREF_CLK 129
#define GCC_RX1_USB2_CLKREF_CLK 130
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
#define USB_30_GDSC 2
#define GCC_QUSB2PHY_PRIM_BCR 0
#define GCC_QUSB2PHY_SEC_BCR 1
#define GCC_UFS_BCR 2
#define GCC_USB3_DP_PHY_BCR 3
#define GCC_USB3_PHY_BCR 4
#define GCC_USB3PHY_PHY_BCR 5
#define GCC_USB_20_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
#endif

3
include/dt-bindings/clock/qcom,gcc-sdm845.h
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@@ -194,6 +194,9 @@
#define GPLL4 184
#define GCC_CPUSS_DVM_BUS_CLK 185
#define GCC_CPUSS_GNOC_CLK 186
#define GCC_QSPI_CORE_CLK_SRC 187
#define GCC_QSPI_CORE_CLK 188
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
/* GCC Resets */
#define GCC_MMSS_BCR 0

7
include/dt-bindings/clock/r7s72100-clock.h
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@@ -1,10 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2014 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__

20
include/dt-bindings/clock/r7s9210-cpg-mssr.h Normal file
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R7S9210 CPG Core Clocks */
#define R7S9210_CLK_I 0
#define R7S9210_CLK_G 1
#define R7S9210_CLK_B 2
#define R7S9210_CLK_P1 3
#define R7S9210_CLK_P1C 4
#define R7S9210_CLK_P0 5
#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7743-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__

39
include/dt-bindings/clock/r8a7744-cpg-mssr.h Normal file
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@@ -0,0 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7744 CPG Core Clocks */
#define R8A7744_CLK_Z 0
#define R8A7744_CLK_ZG 1
#define R8A7744_CLK_ZTR 2
#define R8A7744_CLK_ZTRD2 3
#define R8A7744_CLK_ZT 4
#define R8A7744_CLK_ZX 5
#define R8A7744_CLK_ZS 6
#define R8A7744_CLK_HP 7
#define R8A7744_CLK_B 9
#define R8A7744_CLK_LB 10
#define R8A7744_CLK_P 11
#define R8A7744_CLK_CL 12
#define R8A7744_CLK_M2 13
#define R8A7744_CLK_ZB3 15
#define R8A7744_CLK_ZB3D2 16
#define R8A7744_CLK_DDR 17
#define R8A7744_CLK_SDH 18
#define R8A7744_CLK_SD0 19
#define R8A7744_CLK_SD2 20
#define R8A7744_CLK_SD3 21
#define R8A7744_CLK_MMC0 22
#define R8A7744_CLK_MP 23
#define R8A7744_CLK_QSPI 26
#define R8A7744_CLK_CP 27
#define R8A7744_CLK_RCAN 28
#define R8A7744_CLK_R 29
#define R8A7744_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7745-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__

58
include/dt-bindings/clock/r8a774a1-cpg-mssr.h Normal file
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@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774a1 CPG Core Clocks */
#define R8A774A1_CLK_Z 0
#define R8A774A1_CLK_Z2 1
#define R8A774A1_CLK_ZG 2
#define R8A774A1_CLK_ZTR 3
#define R8A774A1_CLK_ZTRD2 4
#define R8A774A1_CLK_ZT 5
#define R8A774A1_CLK_ZX 6
#define R8A774A1_CLK_S0D1 7
#define R8A774A1_CLK_S0D2 8
#define R8A774A1_CLK_S0D3 9
#define R8A774A1_CLK_S0D4 10
#define R8A774A1_CLK_S0D6 11
#define R8A774A1_CLK_S0D8 12
#define R8A774A1_CLK_S0D12 13
#define R8A774A1_CLK_S1D2 14
#define R8A774A1_CLK_S1D4 15
#define R8A774A1_CLK_S2D1 16
#define R8A774A1_CLK_S2D2 17
#define R8A774A1_CLK_S2D4 18
#define R8A774A1_CLK_S3D1 19
#define R8A774A1_CLK_S3D2 20
#define R8A774A1_CLK_S3D4 21
#define R8A774A1_CLK_LB 22
#define R8A774A1_CLK_CL 23
#define R8A774A1_CLK_ZB3 24
#define R8A774A1_CLK_ZB3D2 25
#define R8A774A1_CLK_ZB3D4 26
#define R8A774A1_CLK_CR 27
#define R8A774A1_CLK_CRD2 28
#define R8A774A1_CLK_SD0H 29
#define R8A774A1_CLK_SD0 30
#define R8A774A1_CLK_SD1H 31
#define R8A774A1_CLK_SD1 32
#define R8A774A1_CLK_SD2H 33
#define R8A774A1_CLK_SD2 34
#define R8A774A1_CLK_SD3H 35
#define R8A774A1_CLK_SD3 36
#define R8A774A1_CLK_RPC 37
#define R8A774A1_CLK_RPCD2 38
#define R8A774A1_CLK_MSO 39
#define R8A774A1_CLK_HDMI 40
#define R8A774A1_CLK_CSI0 41
#define R8A774A1_CLK_CP 42
#define R8A774A1_CLK_CPEX 43
#define R8A774A1_CLK_R 44
#define R8A774A1_CLK_OSC 45
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

60
include/dt-bindings/clock/r8a774c0-cpg-mssr.h Normal file
View File

@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774c0 CPG Core Clocks */
#define R8A774C0_CLK_Z2 0
#define R8A774C0_CLK_ZG 1
#define R8A774C0_CLK_ZTR 2
#define R8A774C0_CLK_ZT 3
#define R8A774C0_CLK_ZX 4
#define R8A774C0_CLK_S0D1 5
#define R8A774C0_CLK_S0D3 6
#define R8A774C0_CLK_S0D6 7
#define R8A774C0_CLK_S0D12 8
#define R8A774C0_CLK_S0D24 9
#define R8A774C0_CLK_S1D1 10
#define R8A774C0_CLK_S1D2 11
#define R8A774C0_CLK_S1D4 12
#define R8A774C0_CLK_S2D1 13
#define R8A774C0_CLK_S2D2 14
#define R8A774C0_CLK_S2D4 15
#define R8A774C0_CLK_S3D1 16
#define R8A774C0_CLK_S3D2 17
#define R8A774C0_CLK_S3D4 18
#define R8A774C0_CLK_S0D6C 19
#define R8A774C0_CLK_S3D1C 20
#define R8A774C0_CLK_S3D2C 21
#define R8A774C0_CLK_S3D4C 22
#define R8A774C0_CLK_LB 23
#define R8A774C0_CLK_CL 24
#define R8A774C0_CLK_ZB3 25
#define R8A774C0_CLK_ZB3D2 26
#define R8A774C0_CLK_CR 27
#define R8A774C0_CLK_CRD2 28
#define R8A774C0_CLK_SD0H 29
#define R8A774C0_CLK_SD0 30
#define R8A774C0_CLK_SD1H 31
#define R8A774C0_CLK_SD1 32
#define R8A774C0_CLK_SD3H 33
#define R8A774C0_CLK_SD3 34
#define R8A774C0_CLK_RPC 35
#define R8A774C0_CLK_RPCD2 36
#define R8A774C0_CLK_ZA2 37
#define R8A774C0_CLK_ZA8 38
#define R8A774C0_CLK_Z2D 39
#define R8A774C0_CLK_MSO 40
#define R8A774C0_CLK_R 41
#define R8A774C0_CLK_OSC 42
#define R8A774C0_CLK_LV0 43
#define R8A774C0_CLK_LV1 44
#define R8A774C0_CLK_CSI0 45
#define R8A774C0_CLK_CP 46
#define R8A774C0_CLK_CPEX 47
#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7790-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7791-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7792-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__

12
include/dt-bindings/clock/r8a7793-clock.h
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@@ -1,16 +1,8 @@
/*
/* SPDX-License-Identifier: GPL-2.0
*
* r8a7793 clock definition
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__

8
include/dt-bindings/clock/r8a7793-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7794-clock.h
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@@ -1,11 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__

8
include/dt-bindings/clock/r8a7794-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7795-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7796-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a77970-cpg-mssr.h
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@@ -1,11 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a77995-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2017 Glider bvba
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2017 Glider bvba
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__

8
include/dt-bindings/clock/renesas-cpg-mssr.h
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@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__

3
include/dt-bindings/clock/rk3188-cru-common.h
View File

@@ -139,8 +139,9 @@
#define HCLK_CIF1 470
#define HCLK_VEPU 471
#define HCLK_VDPU 472
#define HCLK_HDMI 473
#define CLK_NR_CLKS (HCLK_VDPU + 1)
#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */
#define SRST_MCORE 2

5
include/dt-bindings/clock/samsung,s2mps11.h
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@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Markus Reichl
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Samsung S2MPS11 PMIC.
*/

7
include/dt-bindings/clock/samsung,s3c64xx-clock.h
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@@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung S3C64xx clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H

1
include/dt-bindings/clock/sun50i-a64-ccu.h
View File

@@ -43,6 +43,7 @@
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
#define CLK_BUS_MIPI_DSI 28

116
include/dt-bindings/clock/xlnx,zynqmp-clk.h Normal file
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@@ -0,0 +1,116 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2018 Xilinx, Inc.
*
*/
#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
#define _DT_BINDINGS_CLK_ZYNQMP_H
#define IOPLL 0
#define RPLL 1
#define APLL 2
#define DPLL 3
#define VPLL 4
#define IOPLL_TO_FPD 5
#define RPLL_TO_FPD 6
#define APLL_TO_LPD 7
#define DPLL_TO_LPD 8
#define VPLL_TO_LPD 9
#define ACPU 10
#define ACPU_HALF 11
#define DBF_FPD 12
#define DBF_LPD 13
#define DBG_TRACE 14
#define DBG_TSTMP 15
#define DP_VIDEO_REF 16
#define DP_AUDIO_REF 17
#define DP_STC_REF 18
#define GDMA_REF 19
#define DPDMA_REF 20
#define DDR_REF 21
#define SATA_REF 22
#define PCIE_REF 23
#define GPU_REF 24
#define GPU_PP0_REF 25
#define GPU_PP1_REF 26
#define TOPSW_MAIN 27
#define TOPSW_LSBUS 28
#define GTGREF0_REF 29
#define LPD_SWITCH 30
#define LPD_LSBUS 31
#define USB0_BUS_REF 32
#define USB1_BUS_REF 33
#define USB3_DUAL_REF 34
#define USB0 35
#define USB1 36
#define CPU_R5 37
#define CPU_R5_CORE 38
#define CSU_SPB 39
#define CSU_PLL 40
#define PCAP 41
#define IOU_SWITCH 42
#define GEM_TSU_REF 43
#define GEM_TSU 44
#define GEM0_REF 45
#define GEM1_REF 46
#define GEM2_REF 47
#define GEM3_REF 48
#define GEM0_TX 49
#define GEM1_TX 50
#define GEM2_TX 51
#define GEM3_TX 52
#define QSPI_REF 53
#define SDIO0_REF 54
#define SDIO1_REF 55
#define UART0_REF 56
#define UART1_REF 57
#define SPI0_REF 58
#define SPI1_REF 59
#define NAND_REF 60
#define I2C0_REF 61
#define I2C1_REF 62
#define CAN0_REF 63
#define CAN1_REF 64
#define CAN0 65
#define CAN1 66
#define DLL_REF 67
#define ADMA_REF 68
#define TIMESTAMP_REF 69
#define AMS_REF 70
#define PL0_REF 71
#define PL1_REF 72
#define PL2_REF 73
#define PL3_REF 74
#define WDT 75
#define IOPLL_INT 76
#define IOPLL_PRE_SRC 77
#define IOPLL_HALF 78
#define IOPLL_INT_MUX 79
#define IOPLL_POST_SRC 80
#define RPLL_INT 81
#define RPLL_PRE_SRC 82
#define RPLL_HALF 83
#define RPLL_INT_MUX 84
#define RPLL_POST_SRC 85
#define APLL_INT 86
#define APLL_PRE_SRC 87
#define APLL_HALF 88
#define APLL_INT_MUX 89
#define APLL_POST_SRC 90
#define DPLL_INT 91
#define DPLL_PRE_SRC 92
#define DPLL_HALF 93
#define DPLL_INT_MUX 94
#define DPLL_POST_SRC 95
#define VPLL_INT 96
#define VPLL_PRE_SRC 97
#define VPLL_HALF 98
#define VPLL_INT_MUX 99
#define VPLL_POST_SRC 100
#define CAN0_MIO 101
#define CAN1_MIO 102
#endif

125
include/dt-bindings/iio/qcom,spmi-vadc.h
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@@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -116,4 +108,117 @@
#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
/* ADC channels for SPMI PMIC5 */
#define ADC5_REF_GND 0x00
#define ADC5_1P25VREF 0x01
#define ADC5_VREF_VADC 0x02
#define ADC5_VREF_VADC5_DIV_3 0x82
#define ADC5_VPH_PWR 0x83
#define ADC5_VBAT_SNS 0x84
#define ADC5_VCOIN 0x85
#define ADC5_DIE_TEMP 0x06
#define ADC5_USB_IN_I 0x07
#define ADC5_USB_IN_V_16 0x08
#define ADC5_CHG_TEMP 0x09
#define ADC5_BAT_THERM 0x0a
#define ADC5_BAT_ID 0x0b
#define ADC5_XO_THERM 0x0c
#define ADC5_AMUX_THM1 0x0d
#define ADC5_AMUX_THM2 0x0e
#define ADC5_AMUX_THM3 0x0f
#define ADC5_AMUX_THM4 0x10
#define ADC5_AMUX_THM5 0x11
#define ADC5_GPIO1 0x12
#define ADC5_GPIO2 0x13
#define ADC5_GPIO3 0x14
#define ADC5_GPIO4 0x15
#define ADC5_GPIO5 0x16
#define ADC5_GPIO6 0x17
#define ADC5_GPIO7 0x18
#define ADC5_SBUx 0x99
#define ADC5_MID_CHG_DIV6 0x1e
#define ADC5_OFF 0xff
/* 30k pull-up1 */
#define ADC5_BAT_THERM_30K_PU 0x2a
#define ADC5_BAT_ID_30K_PU 0x2b
#define ADC5_XO_THERM_30K_PU 0x2c
#define ADC5_AMUX_THM1_30K_PU 0x2d
#define ADC5_AMUX_THM2_30K_PU 0x2e
#define ADC5_AMUX_THM3_30K_PU 0x2f
#define ADC5_AMUX_THM4_30K_PU 0x30
#define ADC5_AMUX_THM5_30K_PU 0x31
#define ADC5_GPIO1_30K_PU 0x32
#define ADC5_GPIO2_30K_PU 0x33
#define ADC5_GPIO3_30K_PU 0x34
#define ADC5_GPIO4_30K_PU 0x35
#define ADC5_GPIO5_30K_PU 0x36
#define ADC5_GPIO6_30K_PU 0x37
#define ADC5_GPIO7_30K_PU 0x38
#define ADC5_SBUx_30K_PU 0x39
/* 100k pull-up2 */
#define ADC5_BAT_THERM_100K_PU 0x4a
#define ADC5_BAT_ID_100K_PU 0x4b
#define ADC5_XO_THERM_100K_PU 0x4c
#define ADC5_AMUX_THM1_100K_PU 0x4d
#define ADC5_AMUX_THM2_100K_PU 0x4e
#define ADC5_AMUX_THM3_100K_PU 0x4f
#define ADC5_AMUX_THM4_100K_PU 0x50
#define ADC5_AMUX_THM5_100K_PU 0x51
#define ADC5_GPIO1_100K_PU 0x52
#define ADC5_GPIO2_100K_PU 0x53
#define ADC5_GPIO3_100K_PU 0x54
#define ADC5_GPIO4_100K_PU 0x55
#define ADC5_GPIO5_100K_PU 0x56
#define ADC5_GPIO6_100K_PU 0x57
#define ADC5_GPIO7_100K_PU 0x58
#define ADC5_SBUx_100K_PU 0x59
/* 400k pull-up3 */
#define ADC5_BAT_THERM_400K_PU 0x6a
#define ADC5_BAT_ID_400K_PU 0x6b
#define ADC5_XO_THERM_400K_PU 0x6c
#define ADC5_AMUX_THM1_400K_PU 0x6d
#define ADC5_AMUX_THM2_400K_PU 0x6e
#define ADC5_AMUX_THM3_400K_PU 0x6f
#define ADC5_AMUX_THM4_400K_PU 0x70
#define ADC5_AMUX_THM5_400K_PU 0x71
#define ADC5_GPIO1_400K_PU 0x72
#define ADC5_GPIO2_400K_PU 0x73
#define ADC5_GPIO3_400K_PU 0x74
#define ADC5_GPIO4_400K_PU 0x75
#define ADC5_GPIO5_400K_PU 0x76
#define ADC5_GPIO6_400K_PU 0x77
#define ADC5_GPIO7_400K_PU 0x78
#define ADC5_SBUx_400K_PU 0x79
/* 1/3 Divider */
#define ADC5_GPIO1_DIV3 0x92
#define ADC5_GPIO2_DIV3 0x93
#define ADC5_GPIO3_DIV3 0x94
#define ADC5_GPIO4_DIV3 0x95
#define ADC5_GPIO5_DIV3 0x96
#define ADC5_GPIO6_DIV3 0x97
#define ADC5_GPIO7_DIV3 0x98
#define ADC5_SBUx_DIV3 0x99
/* Current and combined current/voltage channels */
#define ADC5_INT_EXT_ISENSE 0xa1
#define ADC5_PARALLEL_ISENSE 0xa5
#define ADC5_CUR_REPLICA_VDS 0xa7
#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
#define ADC5_EXT_SENS_OFFSET 0xad
#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
#define ADC5_MAX_CHANNEL 0xc0
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */

18
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h Normal file
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@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
* pinctrl bindings.
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Author: Aapo Vienamo <avienamo@nvidia.com>
*/
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
/* Voltage levels of the I/O pad's source rail */
#define TEGRA_IO_PAD_VOLTAGE_1V8 0
#define TEGRA_IO_PAD_VOLTAGE_3V3 1
#endif

23
include/dt-bindings/power/owl-s900-powergate.h Normal file
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@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
/*
* Actions Semi S900 SPS
*
* Copyright (c) 2018 Linaro Ltd.
*/
#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
#define S900_PD_GPU_B 0
#define S900_PD_VCE 1
#define S900_PD_SENSOR 2
#define S900_PD_VDE 3
#define S900_PD_HDE 4
#define S900_PD_USB3 5
#define S900_PD_DDR0 6
#define S900_PD_DDR1 7
#define S900_PD_DE 8
#define S900_PD_NAND 9
#define S900_PD_USB2_H0 10
#define S900_PD_USB2_H1 11
#endif

24
include/dt-bindings/power/r8a7744-sysc.h Normal file
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@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*
* Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains.
*/
#define R8A7744_PD_CA15_CPU0 0
#define R8A7744_PD_CA15_CPU1 1
#define R8A7744_PD_CA15_SCU 12
#define R8A7744_PD_SGX 20
/* Always-on power area */
#define R8A7744_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */

31
include/dt-bindings/power/r8a774a1-sysc.h Normal file
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@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774A1_PD_CA57_CPU0 0
#define R8A774A1_PD_CA57_CPU1 1
#define R8A774A1_PD_CA53_CPU0 5
#define R8A774A1_PD_CA53_CPU1 6
#define R8A774A1_PD_CA53_CPU2 7
#define R8A774A1_PD_CA53_CPU3 8
#define R8A774A1_PD_CA57_SCU 12
#define R8A774A1_PD_A3VC 14
#define R8A774A1_PD_3DG_A 17
#define R8A774A1_PD_3DG_B 18
#define R8A774A1_PD_CA53_SCU 21
#define R8A774A1_PD_A2VC0 25
#define R8A774A1_PD_A2VC1 26
/* Always-on power area */
#define R8A774A1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */

25
include/dt-bindings/power/r8a774c0-sysc.h Normal file
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774C0_PD_CA53_CPU0 5
#define R8A774C0_PD_CA53_CPU1 6
#define R8A774C0_PD_A3VC 14
#define R8A774C0_PD_3DG_A 17
#define R8A774C0_PD_3DG_B 18
#define R8A774C0_PD_CA53_SCU 21
#define R8A774C0_PD_A2VC1 26
/* Always-on power area */
#define R8A774C0_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */

34
include/dt-bindings/reset/actions,s700-reset.h Normal file
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@@ -0,0 +1,34 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S700 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H
#define __DT_BINDINGS_ACTIONS_S700_RESET_H
#define RESET_AUDIO 0
#define RESET_CSI 1
#define RESET_DE 2
#define RESET_DSI 3
#define RESET_GPIO 4
#define RESET_I2C0 5
#define RESET_I2C1 6
#define RESET_I2C2 7
#define RESET_I2C3 8
#define RESET_KEY 9
#define RESET_LCD0 10
#define RESET_SI 11
#define RESET_SPI0 12
#define RESET_SPI1 13
#define RESET_SPI2 14
#define RESET_SPI3 15
#define RESET_UART0 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_UART3 19
#define RESET_UART4 20
#define RESET_UART5 21
#define RESET_UART6 22
#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */

65
include/dt-bindings/reset/actions,s900-reset.h Normal file
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@@ -0,0 +1,65 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S900 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
#define __DT_BINDINGS_ACTIONS_S900_RESET_H
#define RESET_CHIPID 0
#define RESET_CPU_SCNT 1
#define RESET_SRAMI 2
#define RESET_DDR_CTL_PHY 3
#define RESET_DMAC 4
#define RESET_GPIO 5
#define RESET_BISP_AXI 6
#define RESET_CSI0 7
#define RESET_CSI1 8
#define RESET_DE 9
#define RESET_DSI 10
#define RESET_GPU3D_PA 11
#define RESET_GPU3D_PB 12
#define RESET_HDE 13
#define RESET_I2C0 14
#define RESET_I2C1 15
#define RESET_I2C2 16
#define RESET_I2C3 17
#define RESET_I2C4 18
#define RESET_I2C5 19
#define RESET_IMX 20
#define RESET_NANDC0 21
#define RESET_NANDC1 22
#define RESET_SD0 23
#define RESET_SD1 24
#define RESET_SD2 25
#define RESET_SD3 26
#define RESET_SPI0 27
#define RESET_SPI1 28
#define RESET_SPI2 29
#define RESET_SPI3 30
#define RESET_UART0 31
#define RESET_UART1 32
#define RESET_UART2 33
#define RESET_UART3 34
#define RESET_UART4 35
#define RESET_UART5 36
#define RESET_UART6 37
#define RESET_HDMI 38
#define RESET_LVDS 39
#define RESET_EDP 40
#define RESET_USB2HUB 41
#define RESET_USB2HSIC 42
#define RESET_USB3 43
#define RESET_PCM1 44
#define RESET_AUDIO 45
#define RESET_PCM0 46
#define RESET_SE 47
#define RESET_GIC 48
#define RESET_DDR_CTL_PHY_AXI 49
#define RESET_CMU_DDR 50
#define RESET_DMM 51
#define RESET_HDCP2TX 52
#define RESET_ETHERNET 53
#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */

20
include/dt-bindings/reset/qcom,sdm845-pdc.h Normal file
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
#define _DT_BINDINGS_RESET_PDC_SDM_845_H
#define PDC_APPS_SYNC_RESET 0
#define PDC_SP_SYNC_RESET 1
#define PDC_AUDIO_SYNC_RESET 2
#define PDC_SENSORS_SYNC_RESET 3
#define PDC_AOP_SYNC_RESET 4
#define PDC_DEBUG_SYNC_RESET 5
#define PDC_GPU_SYNC_RESET 6
#define PDC_DISPLAY_SYNC_RESET 7
#define PDC_COMPUTE_SYNC_RESET 8
#define PDC_MODEM_SYNC_RESET 9
#endif

37
include/linux/bitmap.h
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@@ -28,8 +28,8 @@
* The available bitmap operations and their rough meaning in the
* case that the bitmap is a single unsigned long are thus:
*
* Note that nbits should be always a compile time evaluable constant.
* Otherwise many inlines will generate horrible code.
* The generated code is more efficient when nbits is known at
* compile-time and at most BITS_PER_LONG.
*
* ::
*
@@ -204,38 +204,31 @@ extern int bitmap_print_to_pagebuf(bool list, char *buf,
#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1)))
#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1)))
/*
* The static inlines below do not handle constant nbits==0 correctly,
* so make such users (should any ever turn up) call the out-of-line
* versions.
*/
#define small_const_nbits(nbits) \
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG && (nbits) > 0)
static inline void bitmap_zero(unsigned long *dst, unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = 0UL;
else {
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0, len);
}
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0, len);
}
static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = ~0UL;
else {
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0xff, len);
}
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0xff, len);
}
static inline void bitmap_copy(unsigned long *dst, const unsigned long *src,
unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = *src;
else {
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memcpy(dst, src, len);
}
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memcpy(dst, src, len);
}
/*
@@ -398,7 +391,7 @@ static __always_inline void bitmap_clear(unsigned long *map, unsigned int start,
}
static inline void bitmap_shift_right(unsigned long *dst, const unsigned long *src,
unsigned int shift, int nbits)
unsigned int shift, unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = (*src & BITMAP_LAST_WORD_MASK(nbits)) >> shift;

30
include/linux/bitops.h
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@@ -236,33 +236,33 @@ static __always_inline void __assign_bit(long nr, volatile unsigned long *addr,
#ifdef __KERNEL__
#ifndef set_mask_bits
#define set_mask_bits(ptr, _mask, _bits) \
#define set_mask_bits(ptr, mask, bits) \
({ \
const typeof(*ptr) mask = (_mask), bits = (_bits); \
typeof(*ptr) old, new; \
const typeof(*(ptr)) mask__ = (mask), bits__ = (bits); \
typeof(*(ptr)) old__, new__; \
\
do { \
old = READ_ONCE(*ptr); \
new = (old & ~mask) | bits; \
} while (cmpxchg(ptr, old, new) != old); \
old__ = READ_ONCE(*(ptr)); \
new__ = (old__ & ~mask__) | bits__; \
} while (cmpxchg(ptr, old__, new__) != old__); \
\
new; \
new__; \
})
#endif
#ifndef bit_clear_unless
#define bit_clear_unless(ptr, _clear, _test) \
#define bit_clear_unless(ptr, clear, test) \
({ \
const typeof(*ptr) clear = (_clear), test = (_test); \
typeof(*ptr) old, new; \
const typeof(*(ptr)) clear__ = (clear), test__ = (test);\
typeof(*(ptr)) old__, new__; \
\
do { \
old = READ_ONCE(*ptr); \
new = old & ~clear; \
} while (!(old & test) && \
cmpxchg(ptr, old, new) != old); \
old__ = READ_ONCE(*(ptr)); \
new__ = old__ & ~clear__; \
} while (!(old__ & test__) && \
cmpxchg(ptr, old__, new__) != old__); \
\
!(old & test); \
!(old__ & test__); \
})
#endif

404
include/linux/bootmem.h
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@@ -1,404 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Discontiguous memory support, Kanoj Sarcar, SGI, Nov 1999
*/
#ifndef _LINUX_BOOTMEM_H
#define _LINUX_BOOTMEM_H
#include <linux/mmzone.h>
#include <linux/mm_types.h>
#include <asm/dma.h>
#include <asm/processor.h>
/*
* simple boot-time physical memory area allocator.
*/
extern unsigned long max_low_pfn;
extern unsigned long min_low_pfn;
/*
* highest page
*/
extern unsigned long max_pfn;
/*
* highest possible page
*/
extern unsigned long long max_possible_pfn;
#ifndef CONFIG_NO_BOOTMEM
/**
* struct bootmem_data - per-node information used by the bootmem allocator
* @node_min_pfn: the starting physical address of the node's memory
* @node_low_pfn: the end physical address of the directly addressable memory
* @node_bootmem_map: is a bitmap pointer - the bits represent all physical
* memory pages (including holes) on the node.
* @last_end_off: the offset within the page of the end of the last allocation;
* if 0, the page used is full
* @hint_idx: the PFN of the page used with the last allocation;
* together with using this with the @last_end_offset field,
* a test can be made to see if allocations can be merged
* with the page used for the last allocation rather than
* using up a full new page.
* @list: list entry in the linked list ordered by the memory addresses
*/
typedef struct bootmem_data {
unsigned long node_min_pfn;
unsigned long node_low_pfn;
void *node_bootmem_map;
unsigned long last_end_off;
unsigned long hint_idx;
struct list_head list;
} bootmem_data_t;
extern bootmem_data_t bootmem_node_data[];
#endif
extern unsigned long bootmem_bootmap_pages(unsigned long);
extern unsigned long init_bootmem_node(pg_data_t *pgdat,
unsigned long freepfn,
unsigned long startpfn,
unsigned long endpfn);
extern unsigned long init_bootmem(unsigned long addr, unsigned long memend);
extern unsigned long free_all_bootmem(void);
extern void reset_node_managed_pages(pg_data_t *pgdat);
extern void reset_all_zones_managed_pages(void);
extern void free_bootmem_node(pg_data_t *pgdat,
unsigned long addr,
unsigned long size);
extern void free_bootmem(unsigned long physaddr, unsigned long size);
extern void free_bootmem_late(unsigned long physaddr, unsigned long size);
/*
* Flags for reserve_bootmem (also if CONFIG_HAVE_ARCH_BOOTMEM_NODE,
* the architecture-specific code should honor this).
*
* If flags is BOOTMEM_DEFAULT, then the return value is always 0 (success).
* If flags contains BOOTMEM_EXCLUSIVE, then -EBUSY is returned if the memory
* already was reserved.
*/
#define BOOTMEM_DEFAULT 0
#define BOOTMEM_EXCLUSIVE (1<<0)
extern int reserve_bootmem(unsigned long addr,
unsigned long size,
int flags);
extern int reserve_bootmem_node(pg_data_t *pgdat,
unsigned long physaddr,
unsigned long size,
int flags);
extern void *__alloc_bootmem(unsigned long size,
unsigned long align,
unsigned long goal);
extern void *__alloc_bootmem_nopanic(unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
extern void *__alloc_bootmem_node(pg_data_t *pgdat,
unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
void *__alloc_bootmem_node_high(pg_data_t *pgdat,
unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
extern void *__alloc_bootmem_node_nopanic(pg_data_t *pgdat,
unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
void *___alloc_bootmem_node_nopanic(pg_data_t *pgdat,
unsigned long size,
unsigned long align,
unsigned long goal,
unsigned long limit) __malloc;
extern void *__alloc_bootmem_low(unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
void *__alloc_bootmem_low_nopanic(unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
extern void *__alloc_bootmem_low_node(pg_data_t *pgdat,
unsigned long size,
unsigned long align,
unsigned long goal) __malloc;
#ifdef CONFIG_NO_BOOTMEM
/* We are using top down, so it is safe to use 0 here */
#define BOOTMEM_LOW_LIMIT 0
#else
#define BOOTMEM_LOW_LIMIT __pa(MAX_DMA_ADDRESS)
#endif
#ifndef ARCH_LOW_ADDRESS_LIMIT
#define ARCH_LOW_ADDRESS_LIMIT 0xffffffffUL
#endif
#define alloc_bootmem(x) \
__alloc_bootmem(x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_align(x, align) \
__alloc_bootmem(x, align, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_nopanic(x) \
__alloc_bootmem_nopanic(x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages(x) \
__alloc_bootmem(x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_nopanic(x) \
__alloc_bootmem_nopanic(x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_node(pgdat, x) \
__alloc_bootmem_node(pgdat, x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_node_nopanic(pgdat, x) \
__alloc_bootmem_node_nopanic(pgdat, x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_node(pgdat, x) \
__alloc_bootmem_node(pgdat, x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_node_nopanic(pgdat, x) \
__alloc_bootmem_node_nopanic(pgdat, x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_low(x) \
__alloc_bootmem_low(x, SMP_CACHE_BYTES, 0)
#define alloc_bootmem_low_pages_nopanic(x) \
__alloc_bootmem_low_nopanic(x, PAGE_SIZE, 0)
#define alloc_bootmem_low_pages(x) \
__alloc_bootmem_low(x, PAGE_SIZE, 0)
#define alloc_bootmem_low_pages_node(pgdat, x) \
__alloc_bootmem_low_node(pgdat, x, PAGE_SIZE, 0)
#if defined(CONFIG_HAVE_MEMBLOCK) && defined(CONFIG_NO_BOOTMEM)
/* FIXME: use MEMBLOCK_ALLOC_* variants here */
#define BOOTMEM_ALLOC_ACCESSIBLE 0
#define BOOTMEM_ALLOC_ANYWHERE (~(phys_addr_t)0)
/* FIXME: Move to memblock.h at a point where we remove nobootmem.c */
void *memblock_virt_alloc_try_nid_raw(phys_addr_t size, phys_addr_t align,
phys_addr_t min_addr,
phys_addr_t max_addr, int nid);
void *memblock_virt_alloc_try_nid_nopanic(phys_addr_t size,
phys_addr_t align, phys_addr_t min_addr,
phys_addr_t max_addr, int nid);
void *memblock_virt_alloc_try_nid(phys_addr_t size, phys_addr_t align,
phys_addr_t min_addr, phys_addr_t max_addr, int nid);
void __memblock_free_early(phys_addr_t base, phys_addr_t size);
void __memblock_free_late(phys_addr_t base, phys_addr_t size);
static inline void * __init memblock_virt_alloc(
phys_addr_t size, phys_addr_t align)
{
return memblock_virt_alloc_try_nid(size, align, BOOTMEM_LOW_LIMIT,
BOOTMEM_ALLOC_ACCESSIBLE,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_raw(
phys_addr_t size, phys_addr_t align)
{
return memblock_virt_alloc_try_nid_raw(size, align, BOOTMEM_LOW_LIMIT,
BOOTMEM_ALLOC_ACCESSIBLE,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_nopanic(
phys_addr_t size, phys_addr_t align)
{
return memblock_virt_alloc_try_nid_nopanic(size, align,
BOOTMEM_LOW_LIMIT,
BOOTMEM_ALLOC_ACCESSIBLE,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_low(
phys_addr_t size, phys_addr_t align)
{
return memblock_virt_alloc_try_nid(size, align,
BOOTMEM_LOW_LIMIT,
ARCH_LOW_ADDRESS_LIMIT,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_low_nopanic(
phys_addr_t size, phys_addr_t align)
{
return memblock_virt_alloc_try_nid_nopanic(size, align,
BOOTMEM_LOW_LIMIT,
ARCH_LOW_ADDRESS_LIMIT,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_from_nopanic(
phys_addr_t size, phys_addr_t align, phys_addr_t min_addr)
{
return memblock_virt_alloc_try_nid_nopanic(size, align, min_addr,
BOOTMEM_ALLOC_ACCESSIBLE,
NUMA_NO_NODE);
}
static inline void * __init memblock_virt_alloc_node(
phys_addr_t size, int nid)
{
return memblock_virt_alloc_try_nid(size, 0, BOOTMEM_LOW_LIMIT,
BOOTMEM_ALLOC_ACCESSIBLE, nid);
}
static inline void * __init memblock_virt_alloc_node_nopanic(
phys_addr_t size, int nid)
{
return memblock_virt_alloc_try_nid_nopanic(size, 0, BOOTMEM_LOW_LIMIT,
BOOTMEM_ALLOC_ACCESSIBLE,
nid);
}
static inline void __init memblock_free_early(
phys_addr_t base, phys_addr_t size)
{
__memblock_free_early(base, size);
}
static inline void __init memblock_free_early_nid(
phys_addr_t base, phys_addr_t size, int nid)
{
__memblock_free_early(base, size);
}
static inline void __init memblock_free_late(
phys_addr_t base, phys_addr_t size)
{
__memblock_free_late(base, size);
}
#else
#define BOOTMEM_ALLOC_ACCESSIBLE 0
/* Fall back to all the existing bootmem APIs */
static inline void * __init memblock_virt_alloc(
phys_addr_t size, phys_addr_t align)
{
if (!align)
align = SMP_CACHE_BYTES;
return __alloc_bootmem(size, align, BOOTMEM_LOW_LIMIT);
}
static inline void * __init memblock_virt_alloc_raw(
phys_addr_t size, phys_addr_t align)
{
if (!align)
align = SMP_CACHE_BYTES;
return __alloc_bootmem_nopanic(size, align, BOOTMEM_LOW_LIMIT);
}
static inline void * __init memblock_virt_alloc_nopanic(
phys_addr_t size, phys_addr_t align)
{
if (!align)
align = SMP_CACHE_BYTES;
return __alloc_bootmem_nopanic(size, align, BOOTMEM_LOW_LIMIT);
}
static inline void * __init memblock_virt_alloc_low(
phys_addr_t size, phys_addr_t align)
{
if (!align)
align = SMP_CACHE_BYTES;
return __alloc_bootmem_low(size, align, 0);
}
static inline void * __init memblock_virt_alloc_low_nopanic(
phys_addr_t size, phys_addr_t align)
{
if (!align)
align = SMP_CACHE_BYTES;
return __alloc_bootmem_low_nopanic(size, align, 0);
}
static inline void * __init memblock_virt_alloc_from_nopanic(
phys_addr_t size, phys_addr_t align, phys_addr_t min_addr)
{
return __alloc_bootmem_nopanic(size, align, min_addr);
}
static inline void * __init memblock_virt_alloc_node(
phys_addr_t size, int nid)
{
return __alloc_bootmem_node(NODE_DATA(nid), size, SMP_CACHE_BYTES,
BOOTMEM_LOW_LIMIT);
}
static inline void * __init memblock_virt_alloc_node_nopanic(
phys_addr_t size, int nid)
{
return __alloc_bootmem_node_nopanic(NODE_DATA(nid), size,
SMP_CACHE_BYTES,
BOOTMEM_LOW_LIMIT);
}
static inline void * __init memblock_virt_alloc_try_nid(phys_addr_t size,
phys_addr_t align, phys_addr_t min_addr, phys_addr_t max_addr, int nid)
{
return __alloc_bootmem_node_high(NODE_DATA(nid), size, align,
min_addr);
}
static inline void * __init memblock_virt_alloc_try_nid_raw(
phys_addr_t size, phys_addr_t align,
phys_addr_t min_addr, phys_addr_t max_addr, int nid)
{
return ___alloc_bootmem_node_nopanic(NODE_DATA(nid), size, align,
min_addr, max_addr);
}
static inline void * __init memblock_virt_alloc_try_nid_nopanic(
phys_addr_t size, phys_addr_t align,
phys_addr_t min_addr, phys_addr_t max_addr, int nid)
{
return ___alloc_bootmem_node_nopanic(NODE_DATA(nid), size, align,
min_addr, max_addr);
}
static inline void __init memblock_free_early(
phys_addr_t base, phys_addr_t size)
{
free_bootmem(base, size);
}
static inline void __init memblock_free_early_nid(
phys_addr_t base, phys_addr_t size, int nid)
{
free_bootmem_node(NODE_DATA(nid), base, size);
}
static inline void __init memblock_free_late(
phys_addr_t base, phys_addr_t size)
{
free_bootmem_late(base, size);
}
#endif /* defined(CONFIG_HAVE_MEMBLOCK) && defined(CONFIG_NO_BOOTMEM) */
extern void *alloc_large_system_hash(const char *tablename,
unsigned long bucketsize,
unsigned long numentries,
int scale,
int flags,
unsigned int *_hash_shift,
unsigned int *_hash_mask,
unsigned long low_limit,
unsigned long high_limit);
#define HASH_EARLY 0x00000001 /* Allocating during early boot? */
#define HASH_SMALL 0x00000002 /* sub-page allocation allowed, min
* shift passed via *_hash_shift */
#define HASH_ZERO 0x00000004 /* Zero allocated hash table */
/* Only NUMA needs hash distribution. 64bit NUMA architectures have
* sufficient vmalloc space.
*/
#ifdef CONFIG_NUMA
#define HASHDIST_DEFAULT IS_ENABLED(CONFIG_64BIT)
extern int hashdist; /* Distribute hashes across NUMA nodes? */
#else
#define hashdist (0)
#endif
#endif /* _LINUX_BOOTMEM_H */

8
include/linux/ceph/libceph.h
View File

@@ -81,7 +81,13 @@ struct ceph_options {
#define CEPH_MSG_MAX_FRONT_LEN (16*1024*1024)
#define CEPH_MSG_MAX_MIDDLE_LEN (16*1024*1024)
#define CEPH_MSG_MAX_DATA_LEN (16*1024*1024)
/*
* Handle the largest possible rbd object in one message.
* There is no limit on the size of cephfs objects, but it has to obey
* rsize and wsize mount options anyway.
*/
#define CEPH_MSG_MAX_DATA_LEN (32*1024*1024)
#define CEPH_AUTH_NAME_DEFAULT "guest"

24
include/linux/ceph/messenger.h
View File

@@ -82,22 +82,6 @@ enum ceph_msg_data_type {
CEPH_MSG_DATA_BVECS, /* data source/destination is a bio_vec array */
};
static __inline__ bool ceph_msg_data_type_valid(enum ceph_msg_data_type type)
{
switch (type) {
case CEPH_MSG_DATA_NONE:
case CEPH_MSG_DATA_PAGES:
case CEPH_MSG_DATA_PAGELIST:
#ifdef CONFIG_BLOCK
case CEPH_MSG_DATA_BIO:
#endif /* CONFIG_BLOCK */
case CEPH_MSG_DATA_BVECS:
return true;
default:
return false;
}
}
#ifdef CONFIG_BLOCK
struct ceph_bio_iter {
@@ -181,7 +165,6 @@ struct ceph_bvec_iter {
} while (0)
struct ceph_msg_data {
struct list_head links; /* ceph_msg->data */
enum ceph_msg_data_type type;
union {
#ifdef CONFIG_BLOCK
@@ -202,7 +185,6 @@ struct ceph_msg_data {
struct ceph_msg_data_cursor {
size_t total_resid; /* across all data items */
struct list_head *data_head; /* = &ceph_msg->data */
struct ceph_msg_data *data; /* current data item */
size_t resid; /* bytes not yet consumed */
@@ -240,7 +222,9 @@ struct ceph_msg {
struct ceph_buffer *middle;
size_t data_length;
struct list_head data;
struct ceph_msg_data *data;
int num_data_items;
int max_data_items;
struct ceph_msg_data_cursor cursor;
struct ceph_connection *con;
@@ -381,6 +365,8 @@ void ceph_msg_data_add_bio(struct ceph_msg *msg, struct ceph_bio_iter *bio_pos,
void ceph_msg_data_add_bvecs(struct ceph_msg *msg,
struct ceph_bvec_iter *bvec_pos);
struct ceph_msg *ceph_msg_new2(int type, int front_len, int max_data_items,
gfp_t flags, bool can_fail);
extern struct ceph_msg *ceph_msg_new(int type, int front_len, gfp_t flags,
bool can_fail);

11
include/linux/ceph/msgpool.h
View File

@@ -13,14 +13,15 @@ struct ceph_msgpool {
mempool_t *pool;
int type; /* preallocated message type */
int front_len; /* preallocated payload size */
int max_data_items;
};
extern int ceph_msgpool_init(struct ceph_msgpool *pool, int type,
int front_len, int size, bool blocking,
const char *name);
int ceph_msgpool_init(struct ceph_msgpool *pool, int type,
int front_len, int max_data_items, int size,
const char *name);
extern void ceph_msgpool_destroy(struct ceph_msgpool *pool);
extern struct ceph_msg *ceph_msgpool_get(struct ceph_msgpool *,
int front_len);
struct ceph_msg *ceph_msgpool_get(struct ceph_msgpool *pool, int front_len,
int max_data_items);
extern void ceph_msgpool_put(struct ceph_msgpool *, struct ceph_msg *);
#endif

22
include/linux/ceph/osd_client.h
View File

@@ -136,6 +136,13 @@ struct ceph_osd_req_op {
u64 expected_object_size;
u64 expected_write_size;
} alloc_hint;
struct {
u64 snapid;
u64 src_version;
u8 flags;
u32 src_fadvise_flags;
struct ceph_osd_data osd_data;
} copy_from;
};
};
@@ -444,9 +451,8 @@ extern void osd_req_op_cls_response_data_pages(struct ceph_osd_request *,
struct page **pages, u64 length,
u32 alignment, bool pages_from_pool,
bool own_pages);
extern int osd_req_op_cls_init(struct ceph_osd_request *osd_req,
unsigned int which, u16 opcode,
const char *class, const char *method);
int osd_req_op_cls_init(struct ceph_osd_request *osd_req, unsigned int which,
const char *class, const char *method);
extern int osd_req_op_xattr_init(struct ceph_osd_request *osd_req, unsigned int which,
u16 opcode, const char *name, const void *value,
size_t size, u8 cmp_op, u8 cmp_mode);
@@ -511,6 +517,16 @@ extern int ceph_osdc_writepages(struct ceph_osd_client *osdc,
struct timespec64 *mtime,
struct page **pages, int nr_pages);
int ceph_osdc_copy_from(struct ceph_osd_client *osdc,
u64 src_snapid, u64 src_version,
struct ceph_object_id *src_oid,
struct ceph_object_locator *src_oloc,
u32 src_fadvise_flags,
struct ceph_object_id *dst_oid,
struct ceph_object_locator *dst_oloc,
u32 dst_fadvise_flags,
u8 copy_from_flags);
/* watch/notify */
struct ceph_osd_linger_request *
ceph_osdc_watch(struct ceph_osd_client *osdc,

11
include/linux/ceph/pagelist.h
View File

@@ -23,16 +23,7 @@ struct ceph_pagelist_cursor {
size_t room; /* room remaining to reset to */
};
static inline void ceph_pagelist_init(struct ceph_pagelist *pl)
{
INIT_LIST_HEAD(&pl->head);
pl->mapped_tail = NULL;
pl->length = 0;
pl->room = 0;
INIT_LIST_HEAD(&pl->free_list);
pl->num_pages_free = 0;
refcount_set(&pl->refcnt, 1);
}
struct ceph_pagelist *ceph_pagelist_alloc(gfp_t gfp_flags);
extern void ceph_pagelist_release(struct ceph_pagelist *pl);

28
include/linux/ceph/rados.h
View File

@@ -410,6 +410,14 @@ enum {
enum {
CEPH_OSD_OP_FLAG_EXCL = 1, /* EXCL object create */
CEPH_OSD_OP_FLAG_FAILOK = 2, /* continue despite failure */
CEPH_OSD_OP_FLAG_FADVISE_RANDOM = 0x4, /* the op is random */
CEPH_OSD_OP_FLAG_FADVISE_SEQUENTIAL = 0x8, /* the op is sequential */
CEPH_OSD_OP_FLAG_FADVISE_WILLNEED = 0x10,/* data will be accessed in
the near future */
CEPH_OSD_OP_FLAG_FADVISE_DONTNEED = 0x20,/* data will not be accessed
in the near future */
CEPH_OSD_OP_FLAG_FADVISE_NOCACHE = 0x40,/* data will be accessed only
once by this client */
};
#define EOLDSNAPC ERESTART /* ORDERSNAP flag set; writer has old snapc*/
@@ -431,6 +439,15 @@ enum {
CEPH_OSD_CMPXATTR_MODE_U64 = 2
};
enum {
CEPH_OSD_COPY_FROM_FLAG_FLUSH = 1, /* part of a flush operation */
CEPH_OSD_COPY_FROM_FLAG_IGNORE_OVERLAY = 2, /* ignore pool overlay */
CEPH_OSD_COPY_FROM_FLAG_IGNORE_CACHE = 4, /* ignore osd cache logic */
CEPH_OSD_COPY_FROM_FLAG_MAP_SNAP_CLONE = 8, /* map snap direct to
* cloneid */
CEPH_OSD_COPY_FROM_FLAG_RWORDERED = 16, /* order with write */
};
enum {
CEPH_OSD_WATCH_OP_UNWATCH = 0,
CEPH_OSD_WATCH_OP_LEGACY_WATCH = 1,
@@ -497,6 +514,17 @@ struct ceph_osd_op {
__le64 expected_object_size;
__le64 expected_write_size;
} __attribute__ ((packed)) alloc_hint;
struct {
__le64 snapid;
__le64 src_version;
__u8 flags; /* CEPH_OSD_COPY_FROM_FLAG_* */
/*
* CEPH_OSD_OP_FLAG_FADVISE_*: fadvise flags
* for src object, flags for dest object are in
* ceph_osd_op::flags.
*/
__le32 src_fadvise_flags;
} __attribute__ ((packed)) copy_from;
};
__le32 payload_len;
} __attribute__ ((packed));

9
include/linux/clk-provider.h
View File

@@ -119,6 +119,11 @@ struct clk_duty {
* Called with enable_lock held. This function must not
* sleep.
*
* @save_context: Save the context of the clock in prepration for poweroff.
*
* @restore_context: Restore the context of the clock after a restoration
* of power.
*
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call.
@@ -223,6 +228,8 @@ struct clk_ops {
void (*disable)(struct clk_hw *hw);
int (*is_enabled)(struct clk_hw *hw);
void (*disable_unused)(struct clk_hw *hw);
int (*save_context)(struct clk_hw *hw);
void (*restore_context)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
long (*round_rate)(struct clk_hw *hw, unsigned long rate,
@@ -1011,5 +1018,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
#endif /* platform dependent I/O accessors */
void clk_gate_restore_context(struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */

90
include/linux/clk.h
View File

@@ -312,7 +312,26 @@ struct clk *clk_get(struct device *dev, const char *id);
*/
int __must_check clk_bulk_get(struct device *dev, int num_clks,
struct clk_bulk_data *clks);
/**
* clk_bulk_get_all - lookup and obtain all available references to clock
* producer.
* @dev: device for clock "consumer"
* @clks: pointer to the clk_bulk_data table of consumer
*
* This helper function allows drivers to get all clk consumers in one
* operation. If any of the clk cannot be acquired then any clks
* that were obtained will be freed before returning to the caller.
*
* Returns a positive value for the number of clocks obtained while the
* clock references are stored in the clk_bulk_data table in @clks field.
* Returns 0 if there're none and a negative value if something failed.
*
* Drivers must assume that the clock source is not enabled.
*
* clk_bulk_get should not be called from within interrupt context.
*/
int __must_check clk_bulk_get_all(struct device *dev,
struct clk_bulk_data **clks);
/**
* devm_clk_bulk_get - managed get multiple clk consumers
* @dev: device for clock "consumer"
@@ -327,6 +346,22 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
*/
int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
struct clk_bulk_data *clks);
/**
* devm_clk_bulk_get_all - managed get multiple clk consumers
* @dev: device for clock "consumer"
* @clks: pointer to the clk_bulk_data table of consumer
*
* Returns a positive value for the number of clocks obtained while the
* clock references are stored in the clk_bulk_data table in @clks field.
* Returns 0 if there're none and a negative value if something failed.
*
* This helper function allows drivers to get several clk
* consumers in one operation with management, the clks will
* automatically be freed when the device is unbound.
*/
int __must_check devm_clk_bulk_get_all(struct device *dev,
struct clk_bulk_data **clks);
/**
* devm_clk_get - lookup and obtain a managed reference to a clock producer.
@@ -487,6 +522,19 @@ void clk_put(struct clk *clk);
*/
void clk_bulk_put(int num_clks, struct clk_bulk_data *clks);
/**
* clk_bulk_put_all - "free" all the clock source
* @num_clks: the number of clk_bulk_data
* @clks: the clk_bulk_data table of consumer
*
* Note: drivers must ensure that all clk_bulk_enable calls made on this
* clock source are balanced by clk_bulk_disable calls prior to calling
* this function.
*
* clk_bulk_put_all should not be called from within interrupt context.
*/
void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks);
/**
* devm_clk_put - "free" a managed clock source
* @dev: device used to acquire the clock
@@ -629,6 +677,23 @@ struct clk *clk_get_parent(struct clk *clk);
*/
struct clk *clk_get_sys(const char *dev_id, const char *con_id);
/**
* clk_save_context - save clock context for poweroff
*
* Saves the context of the clock register for powerstates in which the
* contents of the registers will be lost. Occurs deep within the suspend
* code so locking is not necessary.
*/
int clk_save_context(void);
/**
* clk_restore_context - restore clock context after poweroff
*
* This occurs with all clocks enabled. Occurs deep within the resume code
* so locking is not necessary.
*/
void clk_restore_context(void);
#else /* !CONFIG_HAVE_CLK */
static inline struct clk *clk_get(struct device *dev, const char *id)
@@ -642,6 +707,12 @@ static inline int __must_check clk_bulk_get(struct device *dev, int num_clks,
return 0;
}
static inline int __must_check clk_bulk_get_all(struct device *dev,
struct clk_bulk_data **clks)
{
return 0;
}
static inline struct clk *devm_clk_get(struct device *dev, const char *id)
{
return NULL;
@@ -653,6 +724,13 @@ static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clk
return 0;
}
static inline int __must_check devm_clk_bulk_get_all(struct device *dev,
struct clk_bulk_data **clks)
{
return 0;
}
static inline struct clk *devm_get_clk_from_child(struct device *dev,
struct device_node *np, const char *con_id)
{
@@ -663,6 +741,8 @@ static inline void clk_put(struct clk *clk) {}
static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {}
static inline void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) {}
static inline void devm_clk_put(struct device *dev, struct clk *clk) {}
@@ -728,6 +808,14 @@ static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
return NULL;
}
static inline int clk_save_context(void)
{
return 0;
}
static inline void clk_restore_context(void) {}
#endif
/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */

8
include/linux/clk/renesas.h
View File

@@ -1,14 +1,10 @@
/*
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright 2013 Ideas On Board SPRL
* Copyright 2013, 2014 Horms Solutions Ltd.
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Contact: Simon Horman <horms@verge.net.au>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __LINUX_CLK_RENESAS_H_

7
include/linux/clk/ti.h
View File

@@ -159,6 +159,7 @@ struct clk_hw_omap {
const char *clkdm_name;
struct clockdomain *clkdm;
const struct clk_hw_omap_ops *ops;
u32 context;
};
/*
@@ -290,9 +291,15 @@ struct ti_clk_features {
#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
#define TI_CLK_ERRATA_I810 BIT(3)
#define TI_CLK_CLKCTRL_COMPAT BIT(4)
void ti_clk_setup_features(struct ti_clk_features *features);
const struct ti_clk_features *ti_clk_get_features(void);
int omap3_noncore_dpll_save_context(struct clk_hw *hw);
void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
int omap3_core_dpll_save_context(struct clk_hw *hw);
void omap3_core_dpll_restore_context(struct clk_hw *hw);
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;

3
include/linux/compat.h
View File

@@ -488,8 +488,11 @@ put_compat_sigset(compat_sigset_t __user *compat, const sigset_t *set,
compat_sigset_t v;
switch (_NSIG_WORDS) {
case 4: v.sig[7] = (set->sig[3] >> 32); v.sig[6] = set->sig[3];
/* fall through */
case 3: v.sig[5] = (set->sig[2] >> 32); v.sig[4] = set->sig[2];
/* fall through */
case 2: v.sig[3] = (set->sig[1] >> 32); v.sig[2] = set->sig[1];
/* fall through */
case 1: v.sig[1] = (set->sig[0] >> 32); v.sig[0] = set->sig[0];
}
return copy_to_user(compat, &v, size) ? -EFAULT : 0;

17
include/linux/compiler.h
View File

@@ -344,29 +344,14 @@ static inline void *offset_to_ptr(const int *off)
#endif
#ifndef __compiletime_error
# define __compiletime_error(message)
/*
* Sparse complains of variable sized arrays due to the temporary variable in
* __compiletime_assert. Unfortunately we can't just expand it out to make
* sparse see a constant array size without breaking compiletime_assert on old
* versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.
*/
# ifndef __CHECKER__
# define __compiletime_error_fallback(condition) \
do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
# endif
#endif
#ifndef __compiletime_error_fallback
# define __compiletime_error_fallback(condition) do { } while (0)
#endif
#ifdef __OPTIMIZE__
# define __compiletime_assert(condition, msg, prefix, suffix) \
do { \
int __cond = !(condition); \
extern void prefix ## suffix(void) __compiletime_error(msg); \
if (__cond) \
if (!(condition)) \
prefix ## suffix(); \
__compiletime_error_fallback(__cond); \
} while (0)
#else
# define __compiletime_assert(condition, msg, prefix, suffix) do { } while (0)

1
include/linux/console_struct.h
View File

@@ -141,7 +141,6 @@ struct vc_data {
struct uni_pagedir *vc_uni_pagedir;
struct uni_pagedir **vc_uni_pagedir_loc; /* [!] Location of uni_pagedir variable for this console */
struct uni_screen *vc_uni_screen; /* unicode screen content */
bool vc_panic_force_write; /* when oops/panic this VC can accept forced output/blanking */
/* additional information is in vt_kern.h */
};

59
include/linux/fanotify.h
View File

@@ -4,6 +4,61 @@
#include <uapi/linux/fanotify.h>
/* not valid from userspace, only kernel internal */
#define FAN_MARK_ONDIR 0x00000100
#define FAN_GROUP_FLAG(group, flag) \
((group)->fanotify_data.flags & (flag))
/*
* Flags allowed to be passed from/to userspace.
*
* We intentionally do not add new bits to the old FAN_ALL_* constants, because
* they are uapi exposed constants. If there are programs out there using
* these constant, the programs may break if re-compiled with new uapi headers
* and then run on an old kernel.
*/
#define FANOTIFY_CLASS_BITS (FAN_CLASS_NOTIF | FAN_CLASS_CONTENT | \
FAN_CLASS_PRE_CONTENT)
#define FANOTIFY_INIT_FLAGS (FANOTIFY_CLASS_BITS | \
FAN_REPORT_TID | \
FAN_CLOEXEC | FAN_NONBLOCK | \
FAN_UNLIMITED_QUEUE | FAN_UNLIMITED_MARKS)
#define FANOTIFY_MARK_TYPE_BITS (FAN_MARK_INODE | FAN_MARK_MOUNT | \
FAN_MARK_FILESYSTEM)
#define FANOTIFY_MARK_FLAGS (FANOTIFY_MARK_TYPE_BITS | \
FAN_MARK_ADD | \
FAN_MARK_REMOVE | \
FAN_MARK_DONT_FOLLOW | \
FAN_MARK_ONLYDIR | \
FAN_MARK_IGNORED_MASK | \
FAN_MARK_IGNORED_SURV_MODIFY | \
FAN_MARK_FLUSH)
/* Events that user can request to be notified on */
#define FANOTIFY_EVENTS (FAN_ACCESS | FAN_MODIFY | \
FAN_CLOSE | FAN_OPEN)
/* Events that require a permission response from user */
#define FANOTIFY_PERM_EVENTS (FAN_OPEN_PERM | FAN_ACCESS_PERM)
/* Extra flags that may be reported with event or control handling of events */
#define FANOTIFY_EVENT_FLAGS (FAN_EVENT_ON_CHILD | FAN_ONDIR)
/* Events that may be reported to user */
#define FANOTIFY_OUTGOING_EVENTS (FANOTIFY_EVENTS | \
FANOTIFY_PERM_EVENTS | \
FAN_Q_OVERFLOW)
#define ALL_FANOTIFY_EVENT_BITS (FANOTIFY_OUTGOING_EVENTS | \
FANOTIFY_EVENT_FLAGS)
/* Do not use these old uapi constants internally */
#undef FAN_ALL_CLASS_BITS
#undef FAN_ALL_INIT_FLAGS
#undef FAN_ALL_MARK_FLAGS
#undef FAN_ALL_EVENTS
#undef FAN_ALL_PERM_EVENTS
#undef FAN_ALL_OUTGOING_EVENTS
#endif /* _LINUX_FANOTIFY_H */

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