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[MIPS] Fix loads of section missmatches

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2008-03-08 09:56:28 +00:00
parent 1af0eea214
commit 234fcd1484
30 changed files with 171 additions and 180 deletions
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4
arch/mips/kernel/cpu-bugs64.c
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@@ -167,7 +167,7 @@ static inline void check_mult_sh(void)
panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
}
static volatile int daddi_ov __initdata = 0;
static volatile int daddi_ov __cpuinitdata = 0;
asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
{
@@ -239,7 +239,7 @@ static inline void check_daddi(void)
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
}
int daddiu_bug __initdata = -1;
int daddiu_bug __cpuinitdata = -1;
static inline void check_daddiu(void)
{

10
arch/mips/kernel/cpu-probe.c
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@@ -550,7 +550,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
}
}
static char unknown_isa[] __initdata = KERN_ERR \
static char unknown_isa[] __cpuinitdata = KERN_ERR \
"Unsupported ISA type, c0.config0: %d.";
static inline unsigned int decode_config0(struct cpuinfo_mips *c)
@@ -656,7 +656,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
return config3 & MIPS_CONF_M;
}
static void __init decode_configs(struct cpuinfo_mips *c)
static void __cpuinit decode_configs(struct cpuinfo_mips *c)
{
/* MIPS32 or MIPS64 compliant CPU. */
c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
@@ -814,7 +814,7 @@ const char *__cpu_name[NR_CPUS];
/*
* Name a CPU
*/
static __init const char *cpu_to_name(struct cpuinfo_mips *c)
static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
{
const char *name = NULL;
@@ -896,7 +896,7 @@ static __init const char *cpu_to_name(struct cpuinfo_mips *c)
return name;
}
__init void cpu_probe(void)
__cpuinit void cpu_probe(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
unsigned int cpu = smp_processor_id();
@@ -959,7 +959,7 @@ __init void cpu_probe(void)
c->srsets = 1;
}
__init void cpu_report(void)
__cpuinit void cpu_report(void)
{
struct cpuinfo_mips *c = &current_cpu_data;

2
arch/mips/kernel/head.S
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@@ -195,7 +195,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
j start_kernel
END(kernel_entry)
__INIT
__CPUINIT
#ifdef CONFIG_SMP
/*

7
arch/mips/kernel/traps.c
View File

@@ -1306,7 +1306,7 @@ int cp0_compare_irq;
int cp0_perfcount_irq;
EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
void __init per_cpu_trap_init(void)
void __cpuinit per_cpu_trap_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int status_set = ST0_CU0;
@@ -1423,11 +1423,12 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size)
flush_icache_range(ebase + offset, ebase + offset + size);
}
static char panic_null_cerr[] __initdata =
static char panic_null_cerr[] __cpuinitdata =
"Trying to set NULL cache error exception handler";
/* Install uncached CPU exception handler */
void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
unsigned long size)
{
#ifdef CONFIG_32BIT
unsigned long uncached_ebase = KSEG1ADDR(ebase);