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clk: qcom: Add support for banked MD RCGs

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The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd
2014-04-28 15:59:16 -07:00
parent ae3669ac5c
commit 229fd4a505
3 changed files with 77 additions and 56 deletions
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6
drivers/clk/qcom/clk-rcg.h
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@@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
* struct clk_dyn_rcg - root clock generator with glitch free mux
*
* @mux_sel_bit: bit to switch glitch free mux
* @ns_reg: NS register
* @ns_reg: NS0 and NS1 register
* @md_reg: MD0 and MD1 register
* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
* @mn: mn counter (banked)
* @s: source selector (banked)
* @freq_tbl: frequency table
@@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
*
*/
struct clk_dyn_rcg {
u32 ns_reg;
u32 ns_reg[2];
u32 md_reg[2];
u32 bank_reg;
u8 mux_sel_bit;