Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu-feature updates from Ingo Molnar: - Rework the Intel model names symbols/macros, which were decades of ad-hoc extensions and added random noise. It's now a coherent, easy to follow nomenclature. - Add new Intel CPU model IDs: - "Tiger Lake" desktop and mobile models - "Elkhart Lake" model ID - and the "Lightning Mountain" variant of Airmont, plus support code - Add the new AVX512_VP2INTERSECT instruction to cpufeatures - Remove Intel MPX user-visible APIs and the self-tests, because the toolchain (gcc) is not supporting it going forward. This is the first, lowest-risk phase of MPX removal. - Remove X86_FEATURE_MFENCE_RDTSC - Various smaller cleanups and fixes * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) x86/cpu: Update init data for new Airmont CPU model x86/cpu: Add new Airmont variant to Intel family x86/cpu: Add Elkhart Lake to Intel family x86/cpu: Add Tiger Lake to Intel family x86: Correct misc typos x86/intel: Add common OPTDIFFs x86/intel: Aggregate microserver naming x86/intel: Aggregate big core graphics naming x86/intel: Aggregate big core mobile naming x86/intel: Aggregate big core client naming x86/cpufeature: Explain the macro duplication x86/ftrace: Remove mcount() declaration x86/PCI: Remove superfluous returns from void functions x86/msr-index: Move AMD MSRs where they belong x86/cpu: Use constant definitions for CPU models lib: Remove redundant ftrace flag removal x86/crash: Remove unnecessary comparison x86/bitops: Use __builtin_constant_p() directly instead of IS_IMMEDIATE() x86: Remove X86_FEATURE_MFENCE_RDTSC x86/mpx: Remove MPX APIs ...
This commit is contained in:
@@ -49,8 +49,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
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#define array_index_mask_nospec array_index_mask_nospec
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/* Prevent speculative execution past this barrier. */
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#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
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"lfence", X86_FEATURE_LFENCE_RDTSC)
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#define barrier_nospec() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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@@ -45,14 +45,13 @@
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* We do the locked ops that don't return the old value as
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* a mask operation on a byte.
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*/
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#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
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#define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3))
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#define CONST_MASK(nr) (1 << ((nr) & 7))
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static __always_inline void
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arch_set_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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if (__builtin_constant_p(nr)) {
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asm volatile(LOCK_PREFIX "orb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)CONST_MASK(nr))
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@@ -72,7 +71,7 @@ arch___set_bit(long nr, volatile unsigned long *addr)
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static __always_inline void
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arch_clear_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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if (__builtin_constant_p(nr)) {
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asm volatile(LOCK_PREFIX "andb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)~CONST_MASK(nr)));
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@@ -123,7 +122,7 @@ arch___change_bit(long nr, volatile unsigned long *addr)
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static __always_inline void
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arch_change_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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if (__builtin_constant_p(nr)) {
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asm volatile(LOCK_PREFIX "xorb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)CONST_MASK(nr)));
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@@ -61,6 +61,13 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \
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(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))
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/*
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* {REQUIRED,DISABLED}_MASK_CHECK below may seem duplicated with the
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* following BUILD_BUG_ON_ZERO() check but when NCAPINTS gets changed, all
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* header macros which use NCAPINTS need to be changed. The duplicated macro
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* use causes the compiler to issue errors for all headers so that all usage
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* sites can be corrected.
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*/
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#define REQUIRED_MASK_BIT_SET(feature_bit) \
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( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \
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@@ -96,7 +96,6 @@
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#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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@@ -355,6 +354,7 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
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#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
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#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
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#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
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@@ -5,9 +5,6 @@
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/*
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* "Big Core" Processors (Branded as Core, Xeon, etc...)
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*
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* The "_X" parts are generally the EP and EX Xeons, or the
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* "Extreme" ones, like Broadwell-E, or Atom microserver.
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*
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* While adding a new CPUID for a new microarchitecture, add a new
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* group to keep logically sorted out in chronological order. Within
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* that group keep the CPUID for the variants sorted by model number.
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@@ -21,9 +18,19 @@
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* MICROARCH Is the code name for the micro-architecture for this core.
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* N.B. Not the platform name.
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* OPTDIFF If needed, a short string to differentiate by market segment.
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* Exact strings here will vary over time. _DESKTOP, _MOBILE, and
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* _X (short for Xeon server) should be used when they are
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* appropriate.
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*
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* Common OPTDIFFs:
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*
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* - regular client parts
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* _L - regular mobile parts
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* _G - parts with extra graphics on
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* _X - regular server parts
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* _D - micro server parts
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*
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* Historical OPTDIFFs:
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*
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* _EP - 2 socket server parts
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* _EX - 4+ socket server parts
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*
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* The #define line may optionally include a comment including platform names.
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*/
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@@ -49,30 +56,33 @@
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#define INTEL_FAM6_IVYBRIDGE 0x3A
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#define INTEL_FAM6_IVYBRIDGE_X 0x3E
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#define INTEL_FAM6_HASWELL_CORE 0x3C
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#define INTEL_FAM6_HASWELL 0x3C
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#define INTEL_FAM6_HASWELL_X 0x3F
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#define INTEL_FAM6_HASWELL_ULT 0x45
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#define INTEL_FAM6_HASWELL_GT3E 0x46
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#define INTEL_FAM6_HASWELL_L 0x45
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#define INTEL_FAM6_HASWELL_G 0x46
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#define INTEL_FAM6_BROADWELL_CORE 0x3D
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#define INTEL_FAM6_BROADWELL_GT3E 0x47
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#define INTEL_FAM6_BROADWELL 0x3D
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#define INTEL_FAM6_BROADWELL_G 0x47
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#define INTEL_FAM6_BROADWELL_X 0x4F
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#define INTEL_FAM6_BROADWELL_XEON_D 0x56
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#define INTEL_FAM6_BROADWELL_D 0x56
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#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
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#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
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#define INTEL_FAM6_SKYLAKE_L 0x4E
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#define INTEL_FAM6_SKYLAKE 0x5E
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#define INTEL_FAM6_SKYLAKE_X 0x55
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#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
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#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
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#define INTEL_FAM6_KABYLAKE_L 0x8E
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#define INTEL_FAM6_KABYLAKE 0x9E
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#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
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#define INTEL_FAM6_CANNONLAKE_L 0x66
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#define INTEL_FAM6_ICELAKE_X 0x6A
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#define INTEL_FAM6_ICELAKE_XEON_D 0x6C
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#define INTEL_FAM6_ICELAKE_DESKTOP 0x7D
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#define INTEL_FAM6_ICELAKE_MOBILE 0x7E
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#define INTEL_FAM6_ICELAKE_D 0x6C
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#define INTEL_FAM6_ICELAKE 0x7D
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#define INTEL_FAM6_ICELAKE_L 0x7E
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#define INTEL_FAM6_ICELAKE_NNPI 0x9D
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#define INTEL_FAM6_TIGERLAKE_L 0x8C
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#define INTEL_FAM6_TIGERLAKE 0x8D
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/* "Small Core" Processors (Atom) */
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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@@ -83,17 +93,21 @@
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
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#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
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#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
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/* Note: the micro-architecture is "Goldmont Plus" */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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#define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */
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#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
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#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
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/* Xeon Phi */
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@@ -379,14 +379,18 @@
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#define MSR_RELOAD_PMC0 0x000014c1
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#define MSR_RELOAD_FIXED_CTR0 0x00001309
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/* AMD64 MSRs. Not complete. See the architecture manual for a more
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complete list. */
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/*
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* AMD64 MSRs. Not complete. See the architecture manual for a more
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* complete list.
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*/
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#define MSR_AMD64_PATCH_LEVEL 0x0000008b
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#define MSR_AMD64_TSC_RATIO 0xc0000104
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define MSR_AMD64_CPUID_FN_1 0xc0011004
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#define MSR_AMD64_PATCH_LOADER 0xc0010020
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#define MSR_AMD_PERF_CTL 0xc0010062
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#define MSR_AMD_PERF_STATUS 0xc0010063
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_LS_CFG 0xc0011020
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@@ -565,9 +569,6 @@
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define INTEL_PERF_CTL_MASK 0xffff
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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#define MSR_AMD_PERF_STATUS 0xc0010063
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#define MSR_AMD_PERF_CTL 0xc0010062
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#define MSR_IA32_MPERF 0x000000e7
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#define MSR_IA32_APERF 0x000000e8
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@@ -233,8 +233,7 @@ static __always_inline unsigned long long rdtsc_ordered(void)
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* Thus, use the preferred barrier on the respective CPU, aiming for
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* RDTSCP as the default.
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*/
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asm volatile(ALTERNATIVE_3("rdtsc",
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"mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
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asm volatile(ALTERNATIVE_2("rdtsc",
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"lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC,
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"rdtscp", X86_FEATURE_RDTSCP)
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: EAX_EDX_RET(val, low, high)
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@@ -20,7 +20,6 @@ struct real_mode_header {
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u32 ro_end;
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/* SMP trampoline */
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u32 trampoline_start;
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u32 trampoline_status;
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u32 trampoline_header;
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#ifdef CONFIG_X86_64
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u32 trampoline_pgd;
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@@ -45,8 +45,8 @@ extern void text_poke_early(void *addr, const void *opcode, size_t len);
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* no thread can be preempted in the instructions being modified (no iret to an
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* invalid instruction possible) or if the instructions are changed from a
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* consistent state to another consistent state atomically.
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* On the local CPU you need to be protected again NMI or MCE handlers seeing an
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* inconsistent instruction while you patch.
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* On the local CPU you need to be protected against NMI or MCE handlers seeing
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* an inconsistent instruction while you patch.
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*/
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extern void *text_poke(void *addr, const void *opcode, size_t len);
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extern void *text_poke_kgdb(void *addr, const void *opcode, size_t len);
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