Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini:
- ARM: GICv3 ITS emulation and various fixes. Removal of the
old VGIC implementation.
- s390: support for trapping software breakpoints, nested
virtualization (vSIE), the STHYI opcode, initial extensions
for CPU model support.
- MIPS: support for MIPS64 hosts (32-bit guests only) and lots
of cleanups, preliminary to this and the upcoming support for
hardware virtualization extensions.
- x86: support for execute-only mappings in nested EPT; reduced
vmexit latency for TSC deadline timer (by about 30%) on Intel
hosts; support for more than 255 vCPUs.
- PPC: bugfixes.
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (302 commits)
KVM: PPC: Introduce KVM_CAP_PPC_HTM
MIPS: Select HAVE_KVM for MIPS64_R{2,6}
MIPS: KVM: Reset CP0_PageMask during host TLB flush
MIPS: KVM: Fix ptr->int cast via KVM_GUEST_KSEGX()
MIPS: KVM: Sign extend MFC0/RDHWR results
MIPS: KVM: Fix 64-bit big endian dynamic translation
MIPS: KVM: Fail if ebase doesn't fit in CP0_EBase
MIPS: KVM: Use 64-bit CP0_EBase when appropriate
MIPS: KVM: Set CP0_Status.KX on MIPS64
MIPS: KVM: Make entry code MIPS64 friendly
MIPS: KVM: Use kmap instead of CKSEG0ADDR()
MIPS: KVM: Use virt_to_phys() to get commpage PFN
MIPS: Fix definition of KSEGX() for 64-bit
KVM: VMX: Add VMCS to CPU's loaded VMCSs before VMPTRLD
kvm: x86: nVMX: maintain internal copy of current VMCS
KVM: PPC: Book3S HV: Save/restore TM state in H_CEDE
KVM: PPC: Book3S HV: Pull out TM state save/restore into separate procedures
KVM: arm64: vgic-its: Simplify MAPI error handling
KVM: arm64: vgic-its: Make vgic_its_cmd_handle_mapi similar to other handlers
KVM: arm64: vgic-its: Turn device_id validation into generic ID validation
...
This commit is contained in:
Linus Torvalds
@@ -339,71 +339,9 @@ void output_pm_defines(void)
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}
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#endif
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void output_cpuinfo_defines(void)
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{
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COMMENT(" MIPS cpuinfo offsets. ");
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DEFINE(CPUINFO_SIZE, sizeof(struct cpuinfo_mips));
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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OFFSET(CPUINFO_ASID_MASK, cpuinfo_mips, asid_mask);
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#endif
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}
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void output_kvm_defines(void)
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{
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COMMENT(" KVM/MIPS Specfic offsets. ");
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DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
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OFFSET(VCPU_RUN, kvm_vcpu, run);
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OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
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OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
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OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
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OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
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OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
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OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
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OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
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OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
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OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
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OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
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OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
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OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
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OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
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OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
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OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
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OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
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OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
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OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
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OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
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OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
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OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
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OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
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OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
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OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
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OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
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OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
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OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
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OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
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OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
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OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
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OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
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OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
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OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
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OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
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OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
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OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
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OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
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OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
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OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
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OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
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OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
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OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
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OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
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OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
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OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
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BLANK();
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OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
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OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
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@@ -441,14 +379,6 @@ void output_kvm_defines(void)
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OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
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OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
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BLANK();
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OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
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OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
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OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
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OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
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OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
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BLANK();
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}
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#ifdef CONFIG_MIPS_CPS
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@@ -790,7 +790,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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epc += 4 + (insn.i_format.simmediate << 2);
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regs->cp0_epc = epc;
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break;
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case beqzcjic_op:
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case pop66_op:
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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break;
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@@ -798,7 +798,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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/* Compact branch: BEQZC || JIC */
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regs->cp0_epc += 8;
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break;
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case bnezcjialc_op:
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case pop76_op:
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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break;
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@@ -809,8 +809,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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regs->cp0_epc += 8;
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break;
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#endif
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case cbcond0_op:
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case cbcond1_op:
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case pop10_op:
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case pop30_op:
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/* Only valid for MIPS R6 */
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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@@ -619,17 +619,17 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
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1, regs, 0);
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switch (rd) {
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case 0: /* CPU number */
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case MIPS_HWR_CPUNUM: /* CPU number */
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regs->regs[rt] = smp_processor_id();
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return 0;
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case 1: /* SYNCI length */
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case MIPS_HWR_SYNCISTEP: /* SYNCI length */
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regs->regs[rt] = min(current_cpu_data.dcache.linesz,
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current_cpu_data.icache.linesz);
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return 0;
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case 2: /* Read count register */
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case MIPS_HWR_CC: /* Read count register */
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regs->regs[rt] = read_c0_count();
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return 0;
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case 3: /* Count register resolution */
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case MIPS_HWR_CCRES: /* Count register resolution */
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switch (current_cpu_type()) {
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case CPU_20KC:
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case CPU_25KF:
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@@ -639,7 +639,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
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regs->regs[rt] = 2;
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}
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return 0;
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case 29:
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case MIPS_HWR_ULR: /* Read UserLocal register */
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regs->regs[rt] = ti->tp_value;
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return 0;
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default:
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@@ -1859,6 +1859,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
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#define VECTORSPACING 0x100 /* for EI/VI mode */
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unsigned long ebase;
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EXPORT_SYMBOL_GPL(ebase);
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unsigned long exception_handlers[32];
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unsigned long vi_handlers[64];
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@@ -2063,16 +2064,22 @@ static void configure_status(void)
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status_set);
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}
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unsigned int hwrena;
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EXPORT_SYMBOL_GPL(hwrena);
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/* configure HWRENA register */
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static void configure_hwrena(void)
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{
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unsigned int hwrena = cpu_hwrena_impl_bits;
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hwrena = cpu_hwrena_impl_bits;
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if (cpu_has_mips_r2_r6)
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hwrena |= 0x0000000f;
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hwrena |= MIPS_HWRENA_CPUNUM |
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MIPS_HWRENA_SYNCISTEP |
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MIPS_HWRENA_CC |
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MIPS_HWRENA_CCRES;
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if (!noulri && cpu_has_userlocal)
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hwrena |= (1 << 29);
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hwrena |= MIPS_HWRENA_ULR;
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if (hwrena)
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write_c0_hwrena(hwrena);
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