Merge branch 'master' into for-2.6.33
This commit is contained in:
Jens Axboe
@@ -3,6 +3,7 @@
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#include <asm/scatterlist.h>
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#include <asm/cache.h>
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#include <asm-generic/dma-coherent.h>
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void *dma_alloc_noncoherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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@@ -73,14 +74,4 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
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extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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#if 0
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#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags);
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extern void dma_release_declared_memory(struct device *dev);
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extern void * dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size);
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#endif
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#endif /* _ASM_DMA_MAPPING_H */
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@@ -48,9 +48,9 @@ enum fixed_addresses {
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#define FIX_N_COLOURS 8
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FIX_CMAP_BEGIN,
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#ifdef CONFIG_MIPS_MT_SMTC
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FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
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FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
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#else
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FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
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FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
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#endif
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#ifdef CONFIG_HIGHMEM
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/* reserved pte's for temporary kernel mappings */
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@@ -19,15 +19,20 @@
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#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
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/* Offsets to individual GCMP registers from GCMP base */
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#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
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#define GCMPOFS(block, tag, reg) \
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(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
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#define GCMPOFSn(block, tag, reg, n) \
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(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
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#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
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#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
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#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
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#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
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#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
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/* GCMP register access */
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#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
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#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
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#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
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#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
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#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
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@@ -49,10 +54,10 @@
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#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
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#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
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#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
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#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0
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#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
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#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
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#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
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#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
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#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
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#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
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@@ -115,5 +120,6 @@
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#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
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extern int __init gcmp_probe(unsigned long, unsigned long);
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extern int __init gcmp_niocu(void);
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extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
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#endif /* _ASM_GCMPREGS_H */
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@@ -12,7 +12,6 @@
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#define _ASM_GICREGS_H
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#undef GICISBYTELITTLEENDIAN
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#define GICISWORDLITTLEENDIAN
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/* Constants */
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#define GIC_POL_POS 1
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@@ -20,11 +19,7 @@
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#define GIC_TRIG_EDGE 1
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#define GIC_TRIG_LEVEL 0
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#ifdef CONFIG_SMP
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#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
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#else
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#define GIC_NUM_INTRS 32
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#endif
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#define MSK(n) ((1 << (n)) - 1)
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#define REG32(addr) (*(volatile unsigned int *) (addr))
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@@ -70,13 +65,13 @@
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#define USM_VISIBLE_SECTION_SIZE 0x10000
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/* Register Map for Shared Section */
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#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
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#define GIC_SH_CONFIG_OFS 0x0000
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/* Shared Global Counter */
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#define GIC_SH_COUNTER_31_00_OFS 0x0010
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#define GIC_SH_COUNTER_63_32_OFS 0x0014
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Interrupt Polarity */
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#define GIC_SH_POL_31_0_OFS 0x0100
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@@ -164,24 +159,31 @@
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(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Convert an interrupt number to a byte offset/bit for multi-word registers */
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#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
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#define GIC_INTR_BIT(intr) ((intr) % 32)
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/* Polarity : Reset Value is always 0 */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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#define GIC_SET_POLARITY(intr, pol) \
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
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GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
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/* Triggering : Reset Value is always 0 */
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#define GIC_SH_SET_TRIGGER_OFS 0x0180
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#define GIC_SET_TRIGGER(intr, trig) \
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
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GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
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/* Mask manipulation */
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#define GIC_SH_SMASK_OFS 0x0380
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#define GIC_SET_INTR_MASK(intr, val) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
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#define GIC_SET_INTR_MASK(intr) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
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GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
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#define GIC_SH_RMASK_OFS 0x0300
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#define GIC_CLR_INTR_MASK(intr, val) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
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#define GIC_CLR_INTR_MASK(intr) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
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GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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@@ -219,161 +221,6 @@
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#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
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#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
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#else /* CONFIG_CPU_BIG_ENDIAN */
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#define GIC_SH_CONFIG_OFS 0x0000
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/* Shared Global Counter */
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#define GIC_SH_COUNTER_31_00_OFS 0x0014
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#define GIC_SH_COUNTER_63_32_OFS 0x0010
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/* Interrupt Polarity */
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#define GIC_SH_POL_31_0_OFS 0x0104
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#define GIC_SH_POL_63_32_OFS 0x0100
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#define GIC_SH_POL_95_64_OFS 0x010c
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#define GIC_SH_POL_127_96_OFS 0x0108
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#define GIC_SH_POL_159_128_OFS 0x0114
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#define GIC_SH_POL_191_160_OFS 0x0110
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#define GIC_SH_POL_223_192_OFS 0x011c
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#define GIC_SH_POL_255_224_OFS 0x0118
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/* Edge/Level Triggering */
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#define GIC_SH_TRIG_31_0_OFS 0x0184
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#define GIC_SH_TRIG_63_32_OFS 0x0180
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#define GIC_SH_TRIG_95_64_OFS 0x018c
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#define GIC_SH_TRIG_127_96_OFS 0x0188
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#define GIC_SH_TRIG_159_128_OFS 0x0194
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#define GIC_SH_TRIG_191_160_OFS 0x0190
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#define GIC_SH_TRIG_223_192_OFS 0x019c
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#define GIC_SH_TRIG_255_224_OFS 0x0198
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/* Dual Edge Triggering */
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#define GIC_SH_DUAL_31_0_OFS 0x0204
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#define GIC_SH_DUAL_63_32_OFS 0x0200
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#define GIC_SH_DUAL_95_64_OFS 0x020c
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#define GIC_SH_DUAL_127_96_OFS 0x0208
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#define GIC_SH_DUAL_159_128_OFS 0x0214
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#define GIC_SH_DUAL_191_160_OFS 0x0210
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#define GIC_SH_DUAL_223_192_OFS 0x021c
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#define GIC_SH_DUAL_255_224_OFS 0x0218
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Reset Mask - Disables Interrupt */
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#define GIC_SH_RMASK_31_0_OFS 0x0304
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#define GIC_SH_RMASK_63_32_OFS 0x0300
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#define GIC_SH_RMASK_95_64_OFS 0x030c
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#define GIC_SH_RMASK_127_96_OFS 0x0308
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#define GIC_SH_RMASK_159_128_OFS 0x0314
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#define GIC_SH_RMASK_191_160_OFS 0x0310
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#define GIC_SH_RMASK_223_192_OFS 0x031c
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#define GIC_SH_RMASK_255_224_OFS 0x0318
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/* Set Mask (WO) - Enables Interrupt */
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#define GIC_SH_SMASK_31_0_OFS 0x0384
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#define GIC_SH_SMASK_63_32_OFS 0x0380
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#define GIC_SH_SMASK_95_64_OFS 0x038c
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#define GIC_SH_SMASK_127_96_OFS 0x0388
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#define GIC_SH_SMASK_159_128_OFS 0x0394
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#define GIC_SH_SMASK_191_160_OFS 0x0390
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#define GIC_SH_SMASK_223_192_OFS 0x039c
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#define GIC_SH_SMASK_255_224_OFS 0x0398
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_31_0_OFS 0x0404
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#define GIC_SH_MASK_63_32_OFS 0x0400
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#define GIC_SH_MASK_95_64_OFS 0x040c
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#define GIC_SH_MASK_127_96_OFS 0x0408
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#define GIC_SH_MASK_159_128_OFS 0x0414
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#define GIC_SH_MASK_191_160_OFS 0x0410
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#define GIC_SH_MASK_223_192_OFS 0x041c
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#define GIC_SH_MASK_255_224_OFS 0x0418
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_31_0_OFS 0x0484
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#define GIC_SH_PEND_63_32_OFS 0x0480
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#define GIC_SH_PEND_95_64_OFS 0x048c
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#define GIC_SH_PEND_127_96_OFS 0x0488
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#define GIC_SH_PEND_159_128_OFS 0x0494
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#define GIC_SH_PEND_191_160_OFS 0x0490
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#define GIC_SH_PEND_223_192_OFS 0x049c
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#define GIC_SH_PEND_255_224_OFS 0x0498
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#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
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/* Maps Interrupt X to a Pin */
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#define GIC_SH_MAP_TO_PIN(intr) \
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(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
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#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
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/*
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* Maps Interrupt X to a VPE. This is more complex than the LE case, as
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* odd and even registers need to be transposed. It does work - trust me!
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*/
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#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
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(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
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(((((vpe) / 32) ^ 1) - 1) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Polarity */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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#define GIC_SET_POLARITY(intr, pol) \
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
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/* Triggering */
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#define GIC_SH_SET_TRIGGER_OFS 0x0180
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#define GIC_SET_TRIGGER(intr, trig) \
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GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
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/* Mask manipulation */
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#define GIC_SH_SMASK_OFS 0x0380
|
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#define GIC_SET_INTR_MASK(intr, val) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
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#define GIC_SH_RMASK_OFS 0x0300
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#define GIC_CLR_INTR_MASK(intr, val) \
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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#define GIC_VPE_PEND_OFS 0x0004
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#define GIC_VPE_MASK_OFS 0x0008
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#define GIC_VPE_RMASK_OFS 0x000c
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#define GIC_VPE_SMASK_OFS 0x0010
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#define GIC_VPE_WD_MAP_OFS 0x0040
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#define GIC_VPE_COMPARE_MAP_OFS 0x0044
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#define GIC_VPE_TIMER_MAP_OFS 0x0048
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#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
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#define GIC_VPE_SWINT0_MAP_OFS 0x0054
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#define GIC_VPE_SWINT1_MAP_OFS 0x0058
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#define GIC_VPE_OTHER_ADDR_OFS 0x0080
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#define GIC_VPE_WD_CONFIG0_OFS 0x0090
|
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#define GIC_VPE_WD_COUNT0_OFS 0x0094
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#define GIC_VPE_WD_INITIAL0_OFS 0x0098
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#define GIC_VPE_COMPARE_LO_OFS 0x00a4
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#define GIC_VPE_COMPARE_HI_OFS 0x00a0
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#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
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#define GIC_VPE_EIC_SS(intr) \
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(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
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#define GIC_VPE_EIC_VEC_BASE 0x0800
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#define GIC_VPE_EIC_VEC(intr) \
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(GIC_VPE_EIC_VEC_BASE + (4 * intr))
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#define GIC_VPE_TENABLE_NMI_OFS 0x1000
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#define GIC_VPE_TENABLE_YQ_OFS 0x1004
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#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
|
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#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
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|
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/* User Mode Visible Section Register Map */
|
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#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
|
||||
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
|
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|
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#endif /* !LE */
|
||||
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||||
/* Masks */
|
||||
#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
|
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#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
|
||||
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
|
||||
* in building ipi_map.
|
||||
*/
|
||||
struct gic_intr_map {
|
||||
unsigned int intrnum; /* Ext Intr Num */
|
||||
unsigned int cpunum; /* Directed to this CPU */
|
||||
unsigned int pin; /* Directed to this Pin */
|
||||
unsigned int polarity; /* Polarity : +/- */
|
||||
unsigned int trigtype; /* Trigger : Edge/Levl */
|
||||
unsigned int ipiflag; /* Is used for IPI ? */
|
||||
unsigned int flags; /* Misc flags */
|
||||
#define GIC_FLAG_IPI 0x01
|
||||
#define GIC_FLAG_TRANSPARENT 0x02
|
||||
};
|
||||
|
||||
extern void gic_init(unsigned long gic_base_addr,
|
||||
|
||||
@@ -78,6 +78,9 @@
|
||||
#define AR7_REF_CLOCK 25000000
|
||||
#define AR7_XTAL_CLOCK 24000000
|
||||
|
||||
/* DCL */
|
||||
#define AR7_WDT_HW_ENA 0x10
|
||||
|
||||
struct plat_cpmac_data {
|
||||
int reset_bit;
|
||||
int power_bit;
|
||||
|
||||
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio)
|
||||
|
||||
if ((gpio >= 8) && (gpio <= 15))
|
||||
return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
|
||||
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef BCM63XX_DEV_UART_H_
|
||||
#define BCM63XX_DEV_UART_H_
|
||||
|
||||
int bcm63xx_uart_register(void);
|
||||
|
||||
#endif /* BCM63XX_DEV_UART_H_ */
|
||||
@@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
|
||||
.busy_factor = 32, \
|
||||
.imbalance_pct = 125, \
|
||||
.cache_nice_tries = 1, \
|
||||
.flags = SD_LOAD_BALANCE \
|
||||
| SD_BALANCE_EXEC \
|
||||
.flags = SD_LOAD_BALANCE | \
|
||||
SD_BALANCE_EXEC, \
|
||||
.last_balance = jiffies, \
|
||||
.balance_interval = 1, \
|
||||
.nr_balance_failed = 0, \
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_counter 1
|
||||
#define cpu_has_dc_aliases 1
|
||||
#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_ejtag 0
|
||||
@@ -54,6 +54,5 @@
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_icache_snoops_remote_store 1
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
|
||||
|
||||
@@ -75,6 +75,7 @@
|
||||
|
||||
#define MADV_MERGEABLE 12 /* KSM may merge identical pages */
|
||||
#define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages */
|
||||
#define MADV_HWPOISON 100 /* poison a page for testing */
|
||||
|
||||
/* compatibility flags */
|
||||
#define MAP_FILE 0
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hazards.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
#include <asm/mipsmtregs.h>
|
||||
@@ -36,11 +37,13 @@ extern unsigned long pgd_current[];
|
||||
#ifdef CONFIG_32BIT
|
||||
#define TLBMISS_HANDLER_SETUP() \
|
||||
write_c0_context((unsigned long) smp_processor_id() << 25); \
|
||||
back_to_back_c0_hazard(); \
|
||||
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
|
||||
#endif
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TLBMISS_HANDLER_SETUP() \
|
||||
write_c0_context((unsigned long) smp_processor_id() << 26); \
|
||||
back_to_back_c0_hazard(); \
|
||||
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
|
||||
#endif
|
||||
|
||||
@@ -165,12 +168,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
* having ASID_MASK smaller than the hardware maximum,
|
||||
* make sure no "soft" bits become "hard"...
|
||||
*/
|
||||
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
|
||||
| (cpu_context(cpu, next) & ASID_MASK));
|
||||
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
|
||||
cpu_asid(cpu, next));
|
||||
ehb(); /* Make sure it propagates to TCStatus */
|
||||
evpe(mtflags);
|
||||
#else
|
||||
write_c0_entryhi(cpu_context(cpu, next));
|
||||
write_c0_entryhi(cpu_asid(cpu, next));
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
|
||||
|
||||
@@ -226,11 +229,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
|
||||
}
|
||||
/* See comments for similar code above */
|
||||
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
|
||||
(cpu_context(cpu, next) & ASID_MASK));
|
||||
cpu_asid(cpu, next));
|
||||
ehb(); /* Make sure it propagates to TCStatus */
|
||||
evpe(mtflags);
|
||||
#else
|
||||
write_c0_entryhi(cpu_context(cpu, next));
|
||||
write_c0_entryhi(cpu_asid(cpu, next));
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef _MIPS_SETUP_H
|
||||
#define _MIPS_SETUP_H
|
||||
|
||||
#define COMMAND_LINE_SIZE 256
|
||||
#define COMMAND_LINE_SIZE 4096
|
||||
|
||||
#ifdef __KERNEL__
|
||||
extern void setup_early_printk(void);
|
||||
|
||||
@@ -45,6 +45,7 @@ struct smtc_ipi_q {
|
||||
spinlock_t lock;
|
||||
struct smtc_ipi *tail;
|
||||
int depth;
|
||||
int resched_flag; /* reschedule already queued */
|
||||
};
|
||||
|
||||
static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
|
||||
|
||||
10
arch/mips/include/asm/spram.h
Normal file
10
arch/mips/include/asm/spram.h
Normal file
@@ -0,0 +1,10 @@
|
||||
#ifndef _MIPS_SPRAM_H
|
||||
#define _MIPS_SPRAM_H
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
extern __init void spram_config(void);
|
||||
#else
|
||||
static inline void spram_config(void) { };
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
|
||||
#endif /* _MIPS_SPRAM_H */
|
||||
@@ -12,6 +12,7 @@
|
||||
#ifndef _ASM_SYSTEM_H
|
||||
#define _ASM_SYSTEM_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
@@ -193,10 +194,6 @@ extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 v
|
||||
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
|
||||
#endif
|
||||
|
||||
/* This function doesn't exist, so you'll get a linker error
|
||||
if something tries to do an invalid xchg(). */
|
||||
extern void __xchg_called_with_bad_pointer(void);
|
||||
|
||||
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
|
||||
{
|
||||
switch (size) {
|
||||
@@ -205,11 +202,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
|
||||
case 8:
|
||||
return __xchg_u64(ptr, x);
|
||||
}
|
||||
__xchg_called_with_bad_pointer();
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
|
||||
#define xchg(ptr, x) \
|
||||
({ \
|
||||
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
|
||||
\
|
||||
((__typeof__(*(ptr))) \
|
||||
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
|
||||
})
|
||||
|
||||
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
|
||||
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
|
||||
|
||||
@@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
|
||||
#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
|
||||
|
||||
#ifdef CONFIG_DEBUG_STACK_USAGE
|
||||
#define alloc_thread_info(tsk) \
|
||||
({ \
|
||||
struct thread_info *ret; \
|
||||
\
|
||||
ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
|
||||
\
|
||||
ret; \
|
||||
})
|
||||
#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
|
||||
#else
|
||||
#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user