clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:

committed by
Stephen Boyd

parent
2a8e44dffb
commit
22039d150f
@@ -450,5 +450,7 @@
|
||||
#define IMX7D_CLK_ARM 437
|
||||
#define IMX7D_CKIL 438
|
||||
#define IMX7D_OCOTP_CLK 439
|
||||
#define IMX7D_CLK_END 440
|
||||
#define IMX7D_NAND_RAWNAND_CLK 440
|
||||
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
|
||||
#define IMX7D_CLK_END 442
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
Reference in New Issue
Block a user