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powerpc/eeh: Remove VF config space restoration

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There's a bunch of strange things about this code. First up is that none of
the fields being written to are functional for a VF. The SR-IOV
specification lists then as "Reserved, but OS should preserve" so writing
new values to them doesn't do anything and is clearly wrong from a
correctness perspective.

However, since VFs are designed to be managed by the OS there is an
argument to be made that we should be saving and restoring some parts of
config space. We already sort of do that by saving the first 64 bytes of
config space in the eeh_dev (see eeh_dev->config_space[]). This is
inadequate since it doesn't even consider saving and restoring the PCI
capability structures. However, this is a problem with EEH in general and
that needs to be fixed for non-VF devices too.

There's no real reason to keep around this around so delete it.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200725081231.39076-6-oohall@gmail.com
This commit is contained in:
Oliver O'Halloran
2020-07-25 18:12:23 +10:00
committed by Michael Ellerman
parent a40db93431
commit 21b43bd59c
4 changed files with 7 additions and 99 deletions
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59
arch/powerpc/kernel/eeh.c
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@@ -742,65 +742,6 @@ static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
pci_restore_state(pdev);
}
int eeh_restore_vf_config(struct pci_dn *pdn)
{
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
u32 devctl, cmd, cap2, aer_capctl;
int old_mps;
if (edev->pcie_cap) {
/* Restore MPS */
old_mps = (ffs(pdn->mps) - 8) << 5;
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
2, &devctl);
devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
devctl |= old_mps;
eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
2, devctl);
/* Disable Completion Timeout if possible */
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
4, &cap2);
if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) {
eeh_ops->read_config(pdn,
edev->pcie_cap + PCI_EXP_DEVCTL2,
4, &cap2);
cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS;
eeh_ops->write_config(pdn,
edev->pcie_cap + PCI_EXP_DEVCTL2,
4, cap2);
}
}
/* Enable SERR and parity checking */
eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
/* Enable report various errors */
if (edev->pcie_cap) {
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
2, &devctl);
devctl &= ~PCI_EXP_DEVCTL_CERE;
devctl |= (PCI_EXP_DEVCTL_NFERE |
PCI_EXP_DEVCTL_FERE |
PCI_EXP_DEVCTL_URRE);
eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
2, devctl);
}
/* Enable ECRC generation and check */
if (edev->pcie_cap && edev->aer_cap) {
eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
4, &aer_capctl);
aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
4, aer_capctl);
}
return 0;
}
/**
* pcibios_set_pcie_reset_state - Set PCI-E reset state
* @dev: pci device struct