xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branch 'topic/workq-update' into topic/asoc

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Conflicts:
	sound/soc/codecs/wm8350.c
	sound/soc/codecs/wm8753.c
	sound/soc/sh/fsi.c
	sound/soc/soc-core.c
This commit is contained in:
Takashi Iwai
2010-12-13 09:28:43 +01:00
parent 07a9e2b2fb 5b84ba26a9
commit 20aeeb356b
944 changed files with 16575 additions and 7947 deletions
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47
arch/sh/boards/mach-se/7724/setup.c
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@@ -283,31 +283,6 @@ static struct platform_device ceu1_device = {
};
/* FSI */
/*
* FSI-A use external clock which came from ak464x.
* So, we should change parent of fsi
*/
#define FCLKACR 0xa4150008
static void fsimck_init(struct clk *clk)
{
u32 status = __raw_readl(clk->enable_reg);
/* use external clock */
status &= ~0x000000ff;
status |= 0x00000080;
__raw_writel(status, clk->enable_reg);
}
static struct clk_ops fsimck_clk_ops = {
.init = fsimck_init,
};
static struct clk fsimcka_clk = {
.ops = &fsimck_clk_ops,
.enable_reg = (void __iomem *)FCLKACR,
.rate = 0, /* unknown */
};
/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
static struct sh_fsi_platform_info fsi_info = {
.porta_flags = SH_FSI_BRS_INV |
@@ -857,37 +832,29 @@ static int __init devices_setup(void)
gpio_request(GPIO_FN_KEYOUT0, NULL);
/* enable FSI */
gpio_request(GPIO_FN_FSIMCKB, NULL);
gpio_request(GPIO_FN_FSIMCKA, NULL);
gpio_request(GPIO_FN_FSIIASD, NULL);
gpio_request(GPIO_FN_FSIOASD, NULL);
gpio_request(GPIO_FN_FSIIABCK, NULL);
gpio_request(GPIO_FN_FSIIALRCK, NULL);
gpio_request(GPIO_FN_FSIOABCK, NULL);
gpio_request(GPIO_FN_FSIOALRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
gpio_request(GPIO_FN_FSIIBSD, NULL);
gpio_request(GPIO_FN_FSIOBSD, NULL);
gpio_request(GPIO_FN_FSIIBBCK, NULL);
gpio_request(GPIO_FN_FSIIBLRCK, NULL);
gpio_request(GPIO_FN_FSIOBBCK, NULL);
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
gpio_request(GPIO_FN_FSIIASD, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (clk) {
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI A */
clk = clk_get(NULL, "fsia_clk");
if (clk) {
clk_register(&fsimcka_clk);
clk_set_parent(clk, &fsimcka_clk);
clk_set_rate(clk, 11000);
clk_set_rate(&fsimcka_clk, 11000);
if (!IS_ERR(clk)) {
/* 48kHz dummy clock was used to make sure 1/1 divide */
clk_set_rate(&sh7724_fsimcka_clk, 48000);
clk_set_parent(clk, &sh7724_fsimcka_clk);
clk_set_rate(clk, 48000);
clk_put(clk);
}