Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"This is the main drm pull request for 3.10.
Wierd bits:
- OMAP drm changes required OMAP dss changes, in drivers/video, so I
took them in here.
- one more fbcon fix for font handover
- VT switch avoidance in pm code
- scatterlist helpers for gpu drivers - have acks from akpm
Highlights:
- qxl kms driver - driver for the spice qxl virtual GPU
Nouveau:
- fermi/kepler VRAM compression
- GK110/nvf0 modesetting support.
Tegra:
- host1x core merged with 2D engine support
i915:
- vt switchless resume
- more valleyview support
- vblank fixes
- modesetting pipe config rework
radeon:
- UVD engine support
- SI chip tiling support
- GPU registers initialisation from golden values.
exynos:
- device tree changes
- fimc block support
Otherwise:
- bunches of fixes all over the place."
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (513 commits)
qxl: update to new idr interfaces.
drm/nouveau: fix build with nv50->nvc0
drm/radeon: fix handling of v6 power tables
drm/radeon: clarify family checks in pm table parsing
drm/radeon: consolidate UVD clock programming
drm/radeon: fix UPLL_REF_DIV_MASK definition
radeon: add bo tracking debugfs
drm/radeon: add new richland pci ids
drm/radeon: add some new SI PCI ids
drm/radeon: fix scratch reg handling for UVD fence
drm/radeon: allocate SA bo in the requested domain
drm/radeon: fix possible segfault when parsing pm tables
drm/radeon: fix endian bugs in atom_allocate_fb_scratch()
OMAPDSS: TFP410: return EPROBE_DEFER if the i2c adapter not found
OMAPDSS: VENC: Add error handling for venc_probe_pdata
OMAPDSS: HDMI: Add error handling for hdmi_probe_pdata
OMAPDSS: RFBI: Add error handling for rfbi_probe_pdata
OMAPDSS: DSI: Add error handling for dsi_probe_pdata
OMAPDSS: SDI: Add error handling for sdi_probe_pdata
OMAPDSS: DPI: Add error handling for dpi_probe_pdata
...
This commit is contained in:
Linus Torvalds
@@ -8,9 +8,11 @@ header-y += i810_drm.h
|
||||
header-y += i915_drm.h
|
||||
header-y += mga_drm.h
|
||||
header-y += nouveau_drm.h
|
||||
header-y += qxl_drm.h
|
||||
header-y += r128_drm.h
|
||||
header-y += radeon_drm.h
|
||||
header-y += savage_drm.h
|
||||
header-y += sis_drm.h
|
||||
header-y += tegra_drm.h
|
||||
header-y += via_drm.h
|
||||
header-y += vmwgfx_drm.h
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
#ifndef _DRM_H_
|
||||
#define _DRM_H_
|
||||
|
||||
#if defined(__linux__)
|
||||
#if defined(__KERNEL__) || defined(__linux__)
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/ioctl.h>
|
||||
@@ -711,8 +711,8 @@ struct drm_prime_handle {
|
||||
#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
|
||||
#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
|
||||
#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
|
||||
#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
|
||||
#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
|
||||
#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
|
||||
#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
|
||||
|
||||
#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
|
||||
#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
|
||||
|
||||
@@ -367,13 +367,13 @@ struct drm_mode_mode_cmd {
|
||||
* depending on the value in flags different members are used.
|
||||
*
|
||||
* CURSOR_BO uses
|
||||
* crtc
|
||||
* crtc_id
|
||||
* width
|
||||
* height
|
||||
* handle - if 0 turns the cursor of
|
||||
* handle - if 0 turns the cursor off
|
||||
*
|
||||
* CURSOR_MOVE uses
|
||||
* crtc
|
||||
* crtc_id
|
||||
* x
|
||||
* y
|
||||
*/
|
||||
|
||||
152
include/uapi/drm/qxl_drm.h
Normal file
152
include/uapi/drm/qxl_drm.h
Normal file
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* Copyright 2013 Red Hat
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef QXL_DRM_H
|
||||
#define QXL_DRM_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include "drm/drm.h"
|
||||
|
||||
/* Please note that modifications to all structs defined here are
|
||||
* subject to backwards-compatibility constraints.
|
||||
*
|
||||
* Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
|
||||
* compatibility Keep fields aligned to their size
|
||||
*/
|
||||
|
||||
#define QXL_GEM_DOMAIN_CPU 0
|
||||
#define QXL_GEM_DOMAIN_VRAM 1
|
||||
#define QXL_GEM_DOMAIN_SURFACE 2
|
||||
|
||||
#define DRM_QXL_ALLOC 0x00
|
||||
#define DRM_QXL_MAP 0x01
|
||||
#define DRM_QXL_EXECBUFFER 0x02
|
||||
#define DRM_QXL_UPDATE_AREA 0x03
|
||||
#define DRM_QXL_GETPARAM 0x04
|
||||
#define DRM_QXL_CLIENTCAP 0x05
|
||||
|
||||
#define DRM_QXL_ALLOC_SURF 0x06
|
||||
|
||||
struct drm_qxl_alloc {
|
||||
uint32_t size;
|
||||
uint32_t handle; /* 0 is an invalid handle */
|
||||
};
|
||||
|
||||
struct drm_qxl_map {
|
||||
uint64_t offset; /* use for mmap system call */
|
||||
uint32_t handle;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* dest is the bo we are writing the relocation into
|
||||
* src is bo we are relocating.
|
||||
* *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
|
||||
* src_offset)
|
||||
*/
|
||||
#define QXL_RELOC_TYPE_BO 1
|
||||
#define QXL_RELOC_TYPE_SURF 2
|
||||
|
||||
struct drm_qxl_reloc {
|
||||
uint64_t src_offset; /* offset into src_handle or src buffer */
|
||||
uint64_t dst_offset; /* offset in dest handle */
|
||||
uint32_t src_handle; /* dest handle to compute address from */
|
||||
uint32_t dst_handle; /* 0 if to command buffer */
|
||||
uint32_t reloc_type;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
struct drm_qxl_command {
|
||||
uint64_t __user command; /* void* */
|
||||
uint64_t __user relocs; /* struct drm_qxl_reloc* */
|
||||
uint32_t type;
|
||||
uint32_t command_size;
|
||||
uint32_t relocs_num;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
/* XXX: call it drm_qxl_commands? */
|
||||
struct drm_qxl_execbuffer {
|
||||
uint32_t flags; /* for future use */
|
||||
uint32_t commands_num;
|
||||
uint64_t __user commands; /* struct drm_qxl_command* */
|
||||
};
|
||||
|
||||
struct drm_qxl_update_area {
|
||||
uint32_t handle;
|
||||
uint32_t top;
|
||||
uint32_t left;
|
||||
uint32_t bottom;
|
||||
uint32_t right;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
|
||||
#define QXL_PARAM_MAX_RELOCS 2
|
||||
struct drm_qxl_getparam {
|
||||
uint64_t param;
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
/* these are one bit values */
|
||||
struct drm_qxl_clientcap {
|
||||
uint32_t index;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
struct drm_qxl_alloc_surf {
|
||||
uint32_t format;
|
||||
uint32_t width;
|
||||
uint32_t height;
|
||||
int32_t stride;
|
||||
uint32_t handle;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
#define DRM_IOCTL_QXL_ALLOC \
|
||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
|
||||
|
||||
#define DRM_IOCTL_QXL_MAP \
|
||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
|
||||
|
||||
#define DRM_IOCTL_QXL_EXECBUFFER \
|
||||
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
|
||||
struct drm_qxl_execbuffer)
|
||||
|
||||
#define DRM_IOCTL_QXL_UPDATE_AREA \
|
||||
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
|
||||
struct drm_qxl_update_area)
|
||||
|
||||
#define DRM_IOCTL_QXL_GETPARAM \
|
||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
|
||||
struct drm_qxl_getparam)
|
||||
|
||||
#define DRM_IOCTL_QXL_CLIENTCAP \
|
||||
DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
|
||||
struct drm_qxl_clientcap)
|
||||
|
||||
#define DRM_IOCTL_QXL_ALLOC_SURF \
|
||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
|
||||
struct drm_qxl_alloc_surf)
|
||||
|
||||
#endif
|
||||
@@ -918,6 +918,7 @@ struct drm_radeon_gem_va {
|
||||
#define RADEON_CS_RING_GFX 0
|
||||
#define RADEON_CS_RING_COMPUTE 1
|
||||
#define RADEON_CS_RING_DMA 2
|
||||
#define RADEON_CS_RING_UVD 3
|
||||
/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
|
||||
/* 0 = normal, + = higher priority, - = lower priority */
|
||||
|
||||
@@ -972,6 +973,13 @@ struct drm_radeon_cs {
|
||||
#define RADEON_INFO_MAX_SE 0x12
|
||||
/* max SH per SE */
|
||||
#define RADEON_INFO_MAX_SH_PER_SE 0x13
|
||||
/* fast fb access is enabled */
|
||||
#define RADEON_INFO_FASTFB_WORKING 0x14
|
||||
/* query if a RADEON_CS_RING_* submission is supported */
|
||||
#define RADEON_INFO_RING_WORKING 0x15
|
||||
/* SI tile mode array */
|
||||
#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
|
||||
|
||||
|
||||
struct drm_radeon_info {
|
||||
uint32_t request;
|
||||
@@ -979,4 +987,22 @@ struct drm_radeon_info {
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
/* Those correspond to the tile index to use, this is to explicitly state
|
||||
* the API that is implicitly defined by the tile mode array.
|
||||
*/
|
||||
#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
|
||||
#define SI_TILE_MODE_COLOR_1D 13
|
||||
#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
|
||||
#define SI_TILE_MODE_COLOR_2D_8BPP 14
|
||||
#define SI_TILE_MODE_COLOR_2D_16BPP 15
|
||||
#define SI_TILE_MODE_COLOR_2D_32BPP 16
|
||||
#define SI_TILE_MODE_COLOR_2D_64BPP 17
|
||||
#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
|
||||
#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
|
||||
#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
|
||||
#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
|
||||
#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
|
||||
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
|
||||
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
|
||||
|
||||
#endif
|
||||
|
||||
136
include/uapi/drm/tegra_drm.h
Normal file
136
include/uapi/drm/tegra_drm.h
Normal file
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_TEGRA_DRM_H_
|
||||
#define _UAPI_TEGRA_DRM_H_
|
||||
|
||||
struct drm_tegra_gem_create {
|
||||
__u64 size;
|
||||
__u32 flags;
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_tegra_gem_mmap {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
};
|
||||
|
||||
struct drm_tegra_syncpt_read {
|
||||
__u32 id;
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
struct drm_tegra_syncpt_incr {
|
||||
__u32 id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_tegra_syncpt_wait {
|
||||
__u32 id;
|
||||
__u32 thresh;
|
||||
__u32 timeout;
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
|
||||
|
||||
struct drm_tegra_open_channel {
|
||||
__u32 client;
|
||||
__u32 pad;
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
struct drm_tegra_close_channel {
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
struct drm_tegra_get_syncpt {
|
||||
__u64 context;
|
||||
__u32 index;
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
struct drm_tegra_syncpt {
|
||||
__u32 id;
|
||||
__u32 incrs;
|
||||
};
|
||||
|
||||
struct drm_tegra_cmdbuf {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
__u32 words;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_tegra_reloc {
|
||||
struct {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
} cmdbuf;
|
||||
struct {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
} target;
|
||||
__u32 shift;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_tegra_waitchk {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
__u32 syncpt;
|
||||
__u32 thresh;
|
||||
};
|
||||
|
||||
struct drm_tegra_submit {
|
||||
__u64 context;
|
||||
__u32 num_syncpts;
|
||||
__u32 num_cmdbufs;
|
||||
__u32 num_relocs;
|
||||
__u32 num_waitchks;
|
||||
__u32 waitchk_mask;
|
||||
__u32 timeout;
|
||||
__u32 pad;
|
||||
__u64 syncpts;
|
||||
__u64 cmdbufs;
|
||||
__u64 relocs;
|
||||
__u64 waitchks;
|
||||
__u32 fence; /* Return value */
|
||||
|
||||
__u32 reserved[5]; /* future expansion */
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_CREATE 0x00
|
||||
#define DRM_TEGRA_GEM_MMAP 0x01
|
||||
#define DRM_TEGRA_SYNCPT_READ 0x02
|
||||
#define DRM_TEGRA_SYNCPT_INCR 0x03
|
||||
#define DRM_TEGRA_SYNCPT_WAIT 0x04
|
||||
#define DRM_TEGRA_OPEN_CHANNEL 0x05
|
||||
#define DRM_TEGRA_CLOSE_CHANNEL 0x06
|
||||
#define DRM_TEGRA_GET_SYNCPT 0x07
|
||||
#define DRM_TEGRA_SUBMIT 0x08
|
||||
|
||||
#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
|
||||
#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
|
||||
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
|
||||
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user