Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next
This commit is contained in:
Russell King
@@ -21,6 +21,7 @@ generic-y += parport.h
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generic-y += poll.h
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generic-y += preempt.h
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generic-y += resource.h
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generic-y += rwsem.h
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generic-y += sections.h
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generic-y += segment.h
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generic-y += sembuf.h
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@@ -312,7 +312,7 @@
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* you cannot return to the original mode.
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*/
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.macro safe_svcmode_maskall reg:req
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#if __LINUX_ARM_ARCH__ >= 6
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#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
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mrs \reg , cpsr
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eor \reg, \reg, #HYP_MODE
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tst \reg, #MODE_MASK
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@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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static inline void __flush_icache_all(void)
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{
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__flush_icache_preferred();
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dsb();
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dsb(ishst);
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}
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/*
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@@ -487,4 +487,6 @@ int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
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int set_memory_nx(unsigned long addr, int numpages);
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void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
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void *kaddr, unsigned long len);
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#endif
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@@ -72,6 +72,7 @@
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#define ARM_CPU_PART_CORTEX_A15 0xC0F0
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#define ARM_CPU_PART_CORTEX_A7 0xC070
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#define ARM_CPU_PART_CORTEX_A12 0xC0D0
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#define ARM_CPU_PART_CORTEX_A17 0xC0E0
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#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
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#define ARM_CPU_XSCALE_ARCH_V1 0x2000
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@@ -1,24 +1,11 @@
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#ifndef _ASM_FIXMAP_H
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#define _ASM_FIXMAP_H
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/*
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* Nothing too fancy for now.
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*
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* On ARM we already have well known fixed virtual addresses imposed by
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* the architecture such as the vector page which is located at 0xffff0000,
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* therefore a second level page table is already allocated covering
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* 0xfff00000 upwards.
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*
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* The cache flushing code in proc-xscale.S uses the virtual area between
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* 0xfffe0000 and 0xfffeffff.
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*/
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#define FIXADDR_START 0xfff00000UL
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#define FIXADDR_TOP 0xfffe0000UL
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#define FIXADDR_START 0xffc00000UL
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#define FIXADDR_TOP 0xffe00000UL
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#define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START)
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#define FIX_KMAP_BEGIN 0
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#define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT)
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#define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT)
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#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT))
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#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT)
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@@ -27,7 +14,7 @@ extern void __this_fixmap_does_not_exist(void);
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static inline unsigned long fix_to_virt(const unsigned int idx)
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{
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if (idx >= FIX_KMAP_END)
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if (idx >= FIX_KMAP_NR_PTES)
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__this_fixmap_does_not_exist();
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return __fix_to_virt(idx);
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}
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@@ -31,14 +31,6 @@
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#undef CPU_DABORT_HANDLER
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#undef MULTI_DABORT
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#if defined(CONFIG_CPU_ARM710)
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# ifdef CPU_DABORT_HANDLER
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# define MULTI_DABORT 1
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# else
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# define CPU_DABORT_HANDLER cpu_arm7_data_abort
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# endif
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#endif
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#ifdef CONFIG_CPU_ABRT_EV4
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# ifdef CPU_DABORT_HANDLER
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# define MULTI_DABORT 1
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@@ -26,8 +26,8 @@
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#define L2X0_CACHE_TYPE 0x004
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#define L2X0_CTRL 0x100
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#define L2X0_AUX_CTRL 0x104
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#define L2X0_TAG_LATENCY_CTRL 0x108
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#define L2X0_DATA_LATENCY_CTRL 0x10C
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#define L310_TAG_LATENCY_CTRL 0x108
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#define L310_DATA_LATENCY_CTRL 0x10C
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#define L2X0_EVENT_CNT_CTRL 0x200
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#define L2X0_EVENT_CNT1_CFG 0x204
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#define L2X0_EVENT_CNT0_CFG 0x208
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@@ -54,53 +54,93 @@
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#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
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#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
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#define L2X0_LOCKDOWN_STRIDE 0x08
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#define L2X0_ADDR_FILTER_START 0xC00
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#define L2X0_ADDR_FILTER_END 0xC04
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#define L310_ADDR_FILTER_START 0xC00
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#define L310_ADDR_FILTER_END 0xC04
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#define L2X0_TEST_OPERATION 0xF00
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#define L2X0_LINE_DATA 0xF10
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#define L2X0_LINE_TAG 0xF30
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#define L2X0_DEBUG_CTRL 0xF40
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#define L2X0_PREFETCH_CTRL 0xF60
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#define L2X0_POWER_CTRL 0xF80
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#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
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#define L2X0_STNDBY_MODE_EN (1 << 0)
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#define L310_PREFETCH_CTRL 0xF60
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#define L310_POWER_CTRL 0xF80
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#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
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#define L310_STNDBY_MODE_EN (1 << 0)
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/* Registers shifts and masks */
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#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
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#define L2X0_CACHE_ID_PART_L210 (1 << 6)
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#define L2X0_CACHE_ID_PART_L220 (2 << 6)
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#define L2X0_CACHE_ID_PART_L310 (3 << 6)
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#define L2X0_CACHE_ID_RTL_MASK 0x3f
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#define L2X0_CACHE_ID_RTL_R0P0 0x0
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#define L2X0_CACHE_ID_RTL_R1P0 0x2
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#define L2X0_CACHE_ID_RTL_R2P0 0x4
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#define L2X0_CACHE_ID_RTL_R3P0 0x5
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#define L2X0_CACHE_ID_RTL_R3P1 0x6
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#define L2X0_CACHE_ID_RTL_R3P2 0x8
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#define L210_CACHE_ID_RTL_R0P2_02 0x00
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#define L210_CACHE_ID_RTL_R0P1 0x01
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#define L210_CACHE_ID_RTL_R0P2_01 0x02
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#define L210_CACHE_ID_RTL_R0P3 0x03
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#define L210_CACHE_ID_RTL_R0P4 0x0b
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#define L210_CACHE_ID_RTL_R0P5 0x0f
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#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
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#define L310_CACHE_ID_RTL_R0P0 0x00
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#define L310_CACHE_ID_RTL_R1P0 0x02
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#define L310_CACHE_ID_RTL_R2P0 0x04
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#define L310_CACHE_ID_RTL_R3P0 0x05
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#define L310_CACHE_ID_RTL_R3P1 0x06
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#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
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#define L310_CACHE_ID_RTL_R3P2 0x08
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#define L310_CACHE_ID_RTL_R3P3 0x09
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#define L2X0_AUX_CTRL_MASK 0xc0000fff
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/* L2C auxiliary control register - bits common to L2C-210/220/310 */
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#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
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#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
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#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
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#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
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#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
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#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
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/* L2C-210/220 common bits */
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
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#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
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#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
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#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
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#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
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#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
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#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
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#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
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#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
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#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
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#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
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#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
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#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
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#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
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#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
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/* L2C-210 specific bits */
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#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
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#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
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#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
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/* L2C-220 specific bits */
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#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
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#define L220_AUX_CTRL_FWA_SHIFT 23
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#define L220_AUX_CTRL_FWA_MASK (3 << 23)
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#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
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#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
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/* L2C-310 specific bits */
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#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
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#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
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#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
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#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
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#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
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#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
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#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
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#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
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#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
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#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
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#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
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#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
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#define L2X0_LATENCY_CTRL_RD_SHIFT 4
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#define L2X0_LATENCY_CTRL_WR_SHIFT 8
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#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
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#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
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#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
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#define L2X0_ADDR_FILTER_EN 1
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#define L310_ADDR_FILTER_EN 1
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#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
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#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
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#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
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#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
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#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
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#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
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#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
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#define L2X0_CTRL_EN 1
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@@ -18,6 +18,7 @@
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} while (0)
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extern pte_t *pkmap_page_table;
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extern pte_t *fixmap_page_table;
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extern void *kmap_high(struct page *page);
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extern void kunmap_high(struct page *page);
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@@ -179,6 +179,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
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/* PCI fixed i/o mapping */
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#define PCI_IO_VIRT_BASE 0xfee00000
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#if defined(CONFIG_PCI)
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void pci_ioremap_set_mem_type(int mem_type);
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#else
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static inline void pci_ioremap_set_mem_type(int mem_type) {}
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#endif
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extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
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/*
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@@ -14,7 +14,6 @@
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#include <linux/reboot.h>
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struct tag;
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struct meminfo;
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struct pt_regs;
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struct smp_operations;
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#ifdef CONFIG_SMP
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@@ -45,10 +44,12 @@ struct machine_desc {
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unsigned char reserve_lp1 :1; /* never has lp1 */
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unsigned char reserve_lp2 :1; /* never has lp2 */
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enum reboot_mode reboot_mode; /* default restart mode */
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unsigned l2c_aux_val; /* L2 cache aux value */
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unsigned l2c_aux_mask; /* L2 cache aux mask */
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void (*l2c_write_sec)(unsigned long, unsigned);
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struct smp_operations *smp; /* SMP operations */
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bool (*smp_init)(void);
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void (*fixup)(struct tag *, char **,
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struct meminfo *);
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void (*fixup)(struct tag *, char **);
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void (*init_meminfo)(void);
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void (*reserve)(void);/* reserve mem blocks */
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void (*map_io)(void);/* IO mapping function */
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|
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@@ -98,14 +98,14 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
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* previously in which case the caller should take appropriate action.
|
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*
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* On success, the CPU is not guaranteed to be truly halted until
|
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* mcpm_cpu_power_down_finish() subsequently returns non-zero for the
|
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* mcpm_wait_for_cpu_powerdown() subsequently returns non-zero for the
|
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* specified cpu. Until then, other CPUs should make sure they do not
|
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* trash memory the target CPU might be executing/accessing.
|
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*/
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void mcpm_cpu_power_down(void);
|
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|
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/**
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* mcpm_cpu_power_down_finish - wait for a specified CPU to halt, and
|
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* mcpm_wait_for_cpu_powerdown - wait for a specified CPU to halt, and
|
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* make sure it is powered off
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*
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* @cpu: CPU number within given cluster
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@@ -127,7 +127,7 @@ void mcpm_cpu_power_down(void);
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* - zero if the CPU is in a safely parked state
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* - nonzero otherwise (e.g., timeout)
|
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*/
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int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster);
|
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int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster);
|
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|
||||
/**
|
||||
* mcpm_cpu_suspend - bring the calling CPU in a suspended state
|
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@@ -171,7 +171,7 @@ int mcpm_cpu_powered_up(void);
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struct mcpm_platform_ops {
|
||||
int (*power_up)(unsigned int cpu, unsigned int cluster);
|
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void (*power_down)(void);
|
||||
int (*power_down_finish)(unsigned int cpu, unsigned int cluster);
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int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
|
||||
void (*suspend)(u64);
|
||||
void (*powered_up)(void);
|
||||
};
|
||||
|
||||
@@ -1,10 +1,9 @@
|
||||
#ifndef _ASM_ARM_MEMBLOCK_H
|
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#define _ASM_ARM_MEMBLOCK_H
|
||||
|
||||
struct meminfo;
|
||||
struct machine_desc;
|
||||
|
||||
void arm_memblock_init(struct meminfo *, const struct machine_desc *);
|
||||
void arm_memblock_init(const struct machine_desc *);
|
||||
phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
|
||||
|
||||
#endif
|
||||
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||||
@@ -83,8 +83,6 @@
|
||||
*/
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||||
#define IOREMAP_MAX_ORDER 24
|
||||
|
||||
#define CONSISTENT_END (0xffe00000UL)
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
/*
|
||||
|
||||
@@ -28,53 +28,84 @@ struct outer_cache_fns {
|
||||
void (*clean_range)(unsigned long, unsigned long);
|
||||
void (*flush_range)(unsigned long, unsigned long);
|
||||
void (*flush_all)(void);
|
||||
void (*inv_all)(void);
|
||||
void (*disable)(void);
|
||||
#ifdef CONFIG_OUTER_CACHE_SYNC
|
||||
void (*sync)(void);
|
||||
#endif
|
||||
void (*set_debug)(unsigned long);
|
||||
void (*resume)(void);
|
||||
|
||||
/* This is an ARM L2C thing */
|
||||
void (*write_sec)(unsigned long, unsigned);
|
||||
};
|
||||
|
||||
extern struct outer_cache_fns outer_cache;
|
||||
|
||||
#ifdef CONFIG_OUTER_CACHE
|
||||
|
||||
/**
|
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* outer_inv_range - invalidate range of outer cache lines
|
||||
* @start: starting physical address, inclusive
|
||||
* @end: end physical address, exclusive
|
||||
*/
|
||||
static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
|
||||
{
|
||||
if (outer_cache.inv_range)
|
||||
outer_cache.inv_range(start, end);
|
||||
}
|
||||
|
||||
/**
|
||||
* outer_clean_range - clean dirty outer cache lines
|
||||
* @start: starting physical address, inclusive
|
||||
* @end: end physical address, exclusive
|
||||
*/
|
||||
static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
|
||||
{
|
||||
if (outer_cache.clean_range)
|
||||
outer_cache.clean_range(start, end);
|
||||
}
|
||||
|
||||
/**
|
||||
* outer_flush_range - clean and invalidate outer cache lines
|
||||
* @start: starting physical address, inclusive
|
||||
* @end: end physical address, exclusive
|
||||
*/
|
||||
static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
|
||||
{
|
||||
if (outer_cache.flush_range)
|
||||
outer_cache.flush_range(start, end);
|
||||
}
|
||||
|
||||
/**
|
||||
* outer_flush_all - clean and invalidate all cache lines in the outer cache
|
||||
*
|
||||
* Note: depending on implementation, this may not be atomic - it must
|
||||
* only be called with interrupts disabled and no other active outer
|
||||
* cache masters.
|
||||
*
|
||||
* It is intended that this function is only used by implementations
|
||||
* needing to override the outer_cache.disable() method due to security.
|
||||
* (Some implementations perform this as a clean followed by an invalidate.)
|
||||
*/
|
||||
static inline void outer_flush_all(void)
|
||||
{
|
||||
if (outer_cache.flush_all)
|
||||
outer_cache.flush_all();
|
||||
}
|
||||
|
||||
static inline void outer_inv_all(void)
|
||||
{
|
||||
if (outer_cache.inv_all)
|
||||
outer_cache.inv_all();
|
||||
}
|
||||
|
||||
static inline void outer_disable(void)
|
||||
{
|
||||
if (outer_cache.disable)
|
||||
outer_cache.disable();
|
||||
}
|
||||
/**
|
||||
* outer_disable - clean, invalidate and disable the outer cache
|
||||
*
|
||||
* Disable the outer cache, ensuring that any data contained in the outer
|
||||
* cache is pushed out to lower levels of system memory. The note and
|
||||
* conditions above concerning outer_flush_all() applies here.
|
||||
*/
|
||||
extern void outer_disable(void);
|
||||
|
||||
/**
|
||||
* outer_resume - restore the cache configuration and re-enable outer cache
|
||||
*
|
||||
* Restore any configuration that the cache had when previously enabled,
|
||||
* and re-enable the outer cache.
|
||||
*/
|
||||
static inline void outer_resume(void)
|
||||
{
|
||||
if (outer_cache.resume)
|
||||
@@ -90,13 +121,18 @@ static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
|
||||
static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
|
||||
{ }
|
||||
static inline void outer_flush_all(void) { }
|
||||
static inline void outer_inv_all(void) { }
|
||||
static inline void outer_disable(void) { }
|
||||
static inline void outer_resume(void) { }
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OUTER_CACHE_SYNC
|
||||
/**
|
||||
* outer_sync - perform a sync point for outer cache
|
||||
*
|
||||
* Ensure that all outer cache operations are complete and any store
|
||||
* buffers are drained.
|
||||
*/
|
||||
static inline void outer_sync(void)
|
||||
{
|
||||
if (outer_cache.sync)
|
||||
|
||||
@@ -21,34 +21,6 @@
|
||||
#define __tagtable(tag, fn) \
|
||||
static const struct tagtable __tagtable_##fn __tag = { tag, fn }
|
||||
|
||||
/*
|
||||
* Memory map description
|
||||
*/
|
||||
#define NR_BANKS CONFIG_ARM_NR_BANKS
|
||||
|
||||
struct membank {
|
||||
phys_addr_t start;
|
||||
phys_addr_t size;
|
||||
unsigned int highmem;
|
||||
};
|
||||
|
||||
struct meminfo {
|
||||
int nr_banks;
|
||||
struct membank bank[NR_BANKS];
|
||||
};
|
||||
|
||||
extern struct meminfo meminfo;
|
||||
|
||||
#define for_each_bank(iter,mi) \
|
||||
for (iter = 0; iter < (mi)->nr_banks; iter++)
|
||||
|
||||
#define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
|
||||
#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)
|
||||
#define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT)
|
||||
#define bank_phys_start(bank) (bank)->start
|
||||
#define bank_phys_end(bank) ((bank)->start + (bank)->size)
|
||||
#define bank_phys_size(bank) (bank)->size
|
||||
|
||||
extern int arm_add_memory(u64 start, u64 size);
|
||||
extern void early_print(const char *str, ...);
|
||||
extern void dump_machine_table(void);
|
||||
|
||||
@@ -171,8 +171,9 @@ extern int __put_user_8(void *, unsigned long long);
|
||||
#define __put_user_check(x,p) \
|
||||
({ \
|
||||
unsigned long __limit = current_thread_info()->addr_limit - 1; \
|
||||
const typeof(*(p)) __user *__tmp_p = (p); \
|
||||
register const typeof(*(p)) __r2 asm("r2") = (x); \
|
||||
register const typeof(*(p)) __user *__p asm("r0") = (p);\
|
||||
register const typeof(*(p)) __user *__p asm("r0") = __tmp_p; \
|
||||
register unsigned long __l asm("r1") = __limit; \
|
||||
register int __e asm("r0"); \
|
||||
switch (sizeof(*(__p))) { \
|
||||
|
||||
Reference in New Issue
Block a user