drm/i915: clear up wedged transitions
We have two important transitions of the wedged state in the current code: - 0 -> 1: This means a hang has been detected, and signals to everyone that they please get of any locks, so that the reset work item can do its job. - 1 -> 0: The reset handler has completed. Now the last transition mixes up two states: "Reset completed and successful" and "Reset failed". To distinguish these two we do some tricks with the reset completion, but I simply could not convince myself that this doesn't race under odd circumstances. Hence split this up, and add a new terminal state indicating that the hw is gone for good. Also add explicit #defines for both states, update comments. v2: Split out the reset handling bugfix for the throttle ioctl. v3: s/tmp/wedged/ sugested by Chris Wilson. Also fixup up a rebase error which prevented this patch from actually compiling. v4: To unify the wedged state with the reset counter, keep the reset-in-progress state just as a flag. The terminally-wedged state is now denoted with a big number. v5: Add a comment to the reset_counter special values explaining that WEDGED & RESET_IN_PROGRESS needs to be true for the code to be correct. v6: Fixup logic errors introduced with the wedged+reset_counter unification. Since WEDGED implies reset-in-progress (in a way we're terminally stuck in the dead-but-reset-not-completed state), we need ensure that we check for this everywhere. The specific bug was in wait_for_error, which would simply have timed out. v7: Extract an inline i915_reset_in_progress helper to make the code more readable. Also annote the reset-in-progress case with an unlikely, to help the compiler optimize the fastpath. Do the same for the terminally wedged case with i915_terminally_wedged. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@@ -89,36 +89,32 @@ static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
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struct completion *x = &error->completion;
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unsigned long flags;
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int ret;
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if (!atomic_read(&error->wedged))
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#define EXIT_COND (!i915_reset_in_progress(error))
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if (EXIT_COND)
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return 0;
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/* GPU is already declared terminally dead, give up. */
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if (i915_terminally_wedged(error))
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return -EIO;
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/*
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* Only wait 10 seconds for the gpu reset to complete to avoid hanging
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* userspace. If it takes that long something really bad is going on and
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* we should simply try to bail out and fail as gracefully as possible.
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*/
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ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
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ret = wait_event_interruptible_timeout(error->reset_queue,
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EXIT_COND,
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10*HZ);
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if (ret == 0) {
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DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
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return -EIO;
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} else if (ret < 0) {
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return ret;
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}
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#undef EXIT_COND
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if (atomic_read(&error->wedged)) {
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/* GPU is hung, bump the completion count to account for
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* the token we just consumed so that we never hit zero and
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* end up waiting upon a subsequent completion event that
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* will never happen.
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*/
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spin_lock_irqsave(&x->wait.lock, flags);
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x->done++;
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spin_unlock_irqrestore(&x->wait.lock, flags);
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}
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return 0;
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}
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@@ -942,23 +938,14 @@ int
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i915_gem_check_wedge(struct i915_gpu_error *error,
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bool interruptible)
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{
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if (atomic_read(&error->wedged)) {
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struct completion *x = &error->completion;
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bool recovery_complete;
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unsigned long flags;
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/* Give the error handler a chance to run. */
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spin_lock_irqsave(&x->wait.lock, flags);
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recovery_complete = x->done > 0;
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spin_unlock_irqrestore(&x->wait.lock, flags);
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if (i915_reset_in_progress(error)) {
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/* Non-interruptible callers can't handle -EAGAIN, hence return
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* -EIO unconditionally for these. */
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if (!interruptible)
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return -EIO;
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/* Recovery complete, but still wedged means reset failure. */
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if (recovery_complete)
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/* Recovery complete, but the reset failed ... */
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if (i915_terminally_wedged(error))
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return -EIO;
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return -EAGAIN;
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@@ -1025,7 +1012,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
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#define EXIT_COND \
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(i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
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atomic_read(&dev_priv->gpu_error.wedged))
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i915_reset_in_progress(&dev_priv->gpu_error))
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do {
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if (interruptible)
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end = wait_event_interruptible_timeout(ring->irq_queue,
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@@ -1379,7 +1366,7 @@ out:
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/* If this -EIO is due to a gpu hang, give the reset code a
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* chance to clean up the mess. Otherwise return the proper
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* SIGBUS. */
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if (!atomic_read(&dev_priv->gpu_error.wedged))
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if (i915_terminally_wedged(&dev_priv->gpu_error))
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return VM_FAULT_SIGBUS;
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case -EAGAIN:
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/* Give the error handler a chance to run and move the
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@@ -3983,9 +3970,9 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return 0;
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if (atomic_read(&dev_priv->gpu_error.wedged)) {
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if (i915_reset_in_progress(&dev_priv->gpu_error)) {
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DRM_ERROR("Reenabling wedged hardware, good luck\n");
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atomic_set(&dev_priv->gpu_error.wedged, 0);
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atomic_set(&dev_priv->gpu_error.reset_counter, 0);
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}
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mutex_lock(&dev->struct_mutex);
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@@ -4069,7 +4056,7 @@ i915_gem_load(struct drm_device *dev)
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INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
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INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
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i915_gem_retire_work_handler);
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init_completion(&dev_priv->gpu_error.completion);
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init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
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/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
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if (IS_GEN3(dev)) {
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