Merge a45ad71e89 ("Merge tag 'rproc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc") into android-mainline
Another "small" merge point to handle conflicts in a sane way. Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I5dc2f5f11275b29f3c9b5b8d4dd59864ceb6faf9
This commit is contained in:
Greg Kroah-Hartman
@@ -191,8 +191,14 @@ struct clk_duty {
|
||||
*
|
||||
* @init: Perform platform-specific initialization magic.
|
||||
* This is not not used by any of the basic clock types.
|
||||
* Please consider other ways of solving initialization problems
|
||||
* before using this callback, as its use is discouraged.
|
||||
* This callback exist for HW which needs to perform some
|
||||
* initialisation magic for CCF to get an accurate view of the
|
||||
* clock. It may also be used dynamic resource allocation is
|
||||
* required. It shall not used to deal with clock parameters,
|
||||
* such as rate or parents.
|
||||
* Returns 0 on success, -EERROR otherwise.
|
||||
*
|
||||
* @terminate: Free any resource allocated by init.
|
||||
*
|
||||
* @debug_init: Set up type-specific debugfs entries for this clock. This
|
||||
* is called once, after the debugfs directory entry for this
|
||||
@@ -251,7 +257,8 @@ struct clk_ops {
|
||||
struct clk_duty *duty);
|
||||
int (*set_duty_cycle)(struct clk_hw *hw,
|
||||
struct clk_duty *duty);
|
||||
void (*init)(struct clk_hw *hw);
|
||||
int (*init)(struct clk_hw *hw);
|
||||
void (*terminate)(struct clk_hw *hw);
|
||||
void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
|
||||
int (*pre_rate_change)(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
@@ -335,29 +342,119 @@ struct clk_hw {
|
||||
* struct clk_fixed_rate - fixed-rate clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @fixed_rate: constant frequency of clock
|
||||
* @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
|
||||
* @flags: hardware specific flags
|
||||
*
|
||||
* Flags:
|
||||
* * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
|
||||
* instead of what's set in @fixed_accuracy.
|
||||
*/
|
||||
struct clk_fixed_rate {
|
||||
struct clk_hw hw;
|
||||
unsigned long fixed_rate;
|
||||
unsigned long fixed_accuracy;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
|
||||
|
||||
extern const struct clk_ops clk_fixed_rate_ops;
|
||||
struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
unsigned long fixed_rate, unsigned long fixed_accuracy,
|
||||
unsigned long clk_fixed_flags);
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate);
|
||||
struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate);
|
||||
struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate, unsigned long fixed_accuracy);
|
||||
/**
|
||||
* clk_hw_register_fixed_rate - register fixed-rate clock with the clock
|
||||
* framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (fixed_rate), 0, 0)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
|
||||
* the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
|
||||
fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
|
||||
NULL, (flags), (fixed_rate), 0, 0)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
|
||||
* the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
|
||||
fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (fixed_rate), 0, \
|
||||
0)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
|
||||
* the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
* @fixed_accuracy: non-adjustable clock accuracy
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
|
||||
flags, fixed_rate, \
|
||||
fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
|
||||
NULL, NULL, (flags), (fixed_rate), \
|
||||
(fixed_accuracy), 0)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
|
||||
* clock with the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
* @fixed_accuracy: non-adjustable clock accuracy
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
|
||||
parent_hw, flags, fixed_rate, fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
|
||||
NULL, NULL, (flags), (fixed_rate), \
|
||||
(fixed_accuracy), 0)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
|
||||
* clock with the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
* @fixed_accuracy: non-adjustable clock accuracy
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
|
||||
parent_data, flags, fixed_rate, fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), NULL, (flags), \
|
||||
(fixed_rate), (fixed_accuracy), 0)
|
||||
|
||||
void clk_unregister_fixed_rate(struct clk *clk);
|
||||
struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate, unsigned long fixed_accuracy);
|
||||
void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
|
||||
|
||||
void of_fixed_clk_setup(struct device_node *np);
|
||||
@@ -400,14 +497,67 @@ struct clk_gate {
|
||||
#define CLK_GATE_BIG_ENDIAN BIT(2)
|
||||
|
||||
extern const struct clk_ops clk_gate_ops;
|
||||
struct clk_hw *__clk_hw_register_gate(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
/**
|
||||
* clk_hw_register_gate - register a gate clock with the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of this clock's parent
|
||||
* @flags: framework-specific flags for this clock
|
||||
* @reg: register address to control gating of this clock
|
||||
* @bit_idx: which bit in the register controls gating of this clock
|
||||
* @clk_gate_flags: gate-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
|
||||
clk_gate_flags, lock) \
|
||||
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (bit_idx), \
|
||||
(clk_gate_flags), (lock))
|
||||
/**
|
||||
* clk_hw_register_gate_parent_hw - register a gate clock with the clock
|
||||
* framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags for this clock
|
||||
* @reg: register address to control gating of this clock
|
||||
* @bit_idx: which bit in the register controls gating of this clock
|
||||
* @clk_gate_flags: gate-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_gate_parent_hw(dev, name, parent_name, flags, reg, \
|
||||
bit_idx, clk_gate_flags, lock) \
|
||||
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (bit_idx), \
|
||||
(clk_gate_flags), (lock))
|
||||
/**
|
||||
* clk_hw_register_gate_parent_data - register a gate clock with the clock
|
||||
* framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags for this clock
|
||||
* @reg: register address to control gating of this clock
|
||||
* @bit_idx: which bit in the register controls gating of this clock
|
||||
* @clk_gate_flags: gate-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_gate_parent_data(dev, name, parent_name, flags, reg, \
|
||||
bit_idx, clk_gate_flags, lock) \
|
||||
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (bit_idx), \
|
||||
(clk_gate_flags), (lock))
|
||||
void clk_unregister_gate(struct clk *clk);
|
||||
void clk_hw_unregister_gate(struct clk_hw *hw);
|
||||
int clk_gate_is_enabled(struct clk_hw *hw);
|
||||
@@ -497,24 +647,153 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
|
||||
const struct clk_div_table *table, u8 width,
|
||||
unsigned long flags);
|
||||
|
||||
struct clk *clk_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, spinlock_t *lock);
|
||||
struct clk_hw *__clk_hw_register_divider(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
|
||||
const struct clk_div_table *table, spinlock_t *lock);
|
||||
struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, const struct clk_div_table *table,
|
||||
spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_divider_table(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, const struct clk_div_table *table,
|
||||
spinlock_t *lock);
|
||||
/**
|
||||
* clk_register_divider - register a divider clock with the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
|
||||
clk_divider_flags, lock) \
|
||||
clk_register_divider_table((dev), (name), (parent_name), (flags), \
|
||||
(reg), (shift), (width), \
|
||||
(clk_divider_flags), NULL, (lock))
|
||||
/**
|
||||
* clk_hw_register_divider - register a divider clock with the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
|
||||
width, clk_divider_flags, lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (shift), (width), \
|
||||
(clk_divider_flags), NULL, (lock))
|
||||
/**
|
||||
* clk_hw_register_divider_parent_hw - register a divider clock with the clock
|
||||
* framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
|
||||
shift, width, clk_divider_flags, \
|
||||
lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
|
||||
NULL, (flags), (reg), (shift), (width), \
|
||||
(clk_divider_flags), NULL, (lock))
|
||||
/**
|
||||
* clk_hw_register_divider_parent_data - register a divider clock with the clock
|
||||
* framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
|
||||
reg, shift, width, \
|
||||
clk_divider_flags, lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (reg), (shift), \
|
||||
(width), (clk_divider_flags), NULL, (lock))
|
||||
/**
|
||||
* clk_hw_register_divider_table - register a table based divider clock with
|
||||
* the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @table: array of divider/value pairs ending with a div set to 0
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
|
||||
shift, width, clk_divider_flags, table, \
|
||||
lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (shift), (width), \
|
||||
(clk_divider_flags), (table), (lock))
|
||||
/**
|
||||
* clk_hw_register_divider_table_parent_hw - register a table based divider
|
||||
* clock with the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @table: array of divider/value pairs ending with a div set to 0
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
|
||||
reg, shift, width, \
|
||||
clk_divider_flags, table, \
|
||||
lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
|
||||
NULL, (flags), (reg), (shift), (width), \
|
||||
(clk_divider_flags), (table), (lock))
|
||||
/**
|
||||
* clk_hw_register_divider_table_parent_data - register a table based divider
|
||||
* clock with the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @table: array of divider/value pairs ending with a div set to 0
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
|
||||
flags, reg, shift, width, \
|
||||
clk_divider_flags, table, \
|
||||
lock) \
|
||||
__clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (reg), (shift), \
|
||||
(width), (clk_divider_flags), (table), \
|
||||
(lock))
|
||||
|
||||
void clk_unregister_divider(struct clk *clk);
|
||||
void clk_hw_unregister_divider(struct clk_hw *hw);
|
||||
|
||||
@@ -569,28 +848,48 @@ struct clk_mux {
|
||||
extern const struct clk_ops clk_mux_ops;
|
||||
extern const struct clk_ops clk_mux_ro_ops;
|
||||
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock);
|
||||
|
||||
struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
|
||||
const char *name, u8 num_parents,
|
||||
const char * const *parent_names,
|
||||
const struct clk_hw **parent_hws,
|
||||
const struct clk_parent_data *parent_data,
|
||||
unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
|
||||
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
||||
struct clk *clk_register_mux_table(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
|
||||
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
||||
|
||||
#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
|
||||
shift, width, clk_mux_flags, lock) \
|
||||
clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
|
||||
(flags), (reg), (shift), BIT((width)) - 1, \
|
||||
(clk_mux_flags), NULL, (lock))
|
||||
#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
|
||||
flags, reg, shift, mask, clk_mux_flags, \
|
||||
table, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), \
|
||||
(parent_names), NULL, NULL, (flags), (reg), \
|
||||
(shift), (mask), (clk_mux_flags), (table), \
|
||||
(lock))
|
||||
#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
|
||||
shift, width, clk_mux_flags, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), \
|
||||
(parent_names), NULL, NULL, (flags), (reg), \
|
||||
(shift), BIT((width)) - 1, (clk_mux_flags), \
|
||||
NULL, (lock))
|
||||
#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
|
||||
reg, shift, width, clk_mux_flags, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
|
||||
(parent_hws), NULL, (flags), (reg), (shift), \
|
||||
BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
|
||||
#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
|
||||
flags, reg, shift, width, \
|
||||
clk_mux_flags, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
|
||||
(parent_data), (flags), (reg), (shift), \
|
||||
BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
|
||||
|
||||
int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
|
||||
unsigned int val);
|
||||
unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
|
||||
@@ -757,6 +1056,12 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
|
||||
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
||||
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
||||
unsigned long flags);
|
||||
struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
|
||||
const struct clk_parent_data *parent_data, int num_parents,
|
||||
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
||||
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
||||
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
||||
unsigned long flags);
|
||||
void clk_unregister_composite(struct clk *clk);
|
||||
struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
||||
const char * const *parent_names, int num_parents,
|
||||
@@ -764,46 +1069,15 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
||||
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
||||
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
||||
unsigned long flags);
|
||||
struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
|
||||
const char *name,
|
||||
const struct clk_parent_data *parent_data, int num_parents,
|
||||
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
||||
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
||||
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
||||
unsigned long flags);
|
||||
void clk_hw_unregister_composite(struct clk_hw *hw);
|
||||
|
||||
/**
|
||||
* struct clk_gpio - gpio gated clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @gpiod: gpio descriptor
|
||||
*
|
||||
* Clock with a gpio control for enabling and disabling the parent clock
|
||||
* or switching between two parents by asserting or deasserting the gpio.
|
||||
*
|
||||
* Implements .enable, .disable and .is_enabled or
|
||||
* .get_parent, .set_parent and .determine_rate depending on which clk_ops
|
||||
* is used.
|
||||
*/
|
||||
struct clk_gpio {
|
||||
struct clk_hw hw;
|
||||
struct gpio_desc *gpiod;
|
||||
};
|
||||
|
||||
#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
|
||||
|
||||
extern const struct clk_ops clk_gpio_gate_ops;
|
||||
struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, struct gpio_desc *gpiod,
|
||||
unsigned long flags);
|
||||
struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, struct gpio_desc *gpiod,
|
||||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
|
||||
|
||||
extern const struct clk_ops clk_gpio_mux_ops;
|
||||
struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
|
||||
unsigned long flags);
|
||||
struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
|
||||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
|
||||
|
||||
struct clk *clk_register(struct device *dev, struct clk_hw *hw);
|
||||
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user