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ARCv2: Support for ARCv2 ISA and HS38x cores

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The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
2013-05-13 18:30:41 +05:30
parent 820970a5aa
commit 1f6ccfff63
22 changed files with 737 additions and 33 deletions
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2
arch/arc/kernel/head.S
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@@ -49,8 +49,6 @@
1:
.endm
.cpu A7
.section .init.text, "ax",@progbits
.type stext, @function
.globl stext