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ARCv2: Support for ARCv2 ISA and HS38x cores

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The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
2013-05-13 18:30:41 +05:30
parent 820970a5aa
commit 1f6ccfff63
22 changed files with 737 additions and 33 deletions
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53
arch/arc/include/asm/arcregs.h
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@@ -16,6 +16,7 @@
#define ARC_REG_PERIBASE_BCR 0x69
#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
#define ARC_REG_TIMERS_BCR 0x75
#define ARC_REG_AP_BCR 0x76
@@ -52,6 +53,7 @@
* [15: 8] = Exception Cause Code
* [ 7: 0] = Exception Parameters (for certain types only)
*/
#ifdef CONFIG_ISA_ARCOMPACT
#define ECR_V_MEM_ERR 0x01
#define ECR_V_INSN_ERR 0x02
#define ECR_V_MACH_CHK 0x20
@@ -59,6 +61,15 @@
#define ECR_V_DTLB_MISS 0x22
#define ECR_V_PROTV 0x23
#define ECR_V_TRAP 0x25
#else
#define ECR_V_MEM_ERR 0x01
#define ECR_V_INSN_ERR 0x02
#define ECR_V_MACH_CHK 0x03
#define ECR_V_ITLB_MISS 0x04
#define ECR_V_DTLB_MISS 0x05
#define ECR_V_PROTV 0x06
#define ECR_V_TRAP 0x09
#endif
/* DTLB Miss and Protection Violation Cause Codes */
@@ -202,9 +213,11 @@ struct bcr_identity {
struct bcr_isa {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad1:23, atomic1:1, ver:8;
unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
pad1:11, atomic1:1, ver:8;
#else
unsigned int ver:8, atomic1:1, pad1:23;
unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
ldd:1, pad2:4, div_rem:4;
#endif
};
@@ -267,11 +280,19 @@ struct bcr_fp_arcompact {
#endif
};
struct bcr_fp_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
#else
unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
#endif
};
struct bcr_timer {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:15, rtsc:1, pad1:6, t1:1, t0:1, ver:8;
unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
#else
unsigned int ver:8, t0:1, t1:1, pad1:6, rtsc:1, pad2:15;
unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
#endif
};
@@ -283,6 +304,14 @@ struct bcr_bpu_arcompact {
#endif
};
struct bcr_bpu_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
#else
unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
#endif
};
struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:24, ver:8;
@@ -334,6 +363,22 @@ struct cpuinfo_arc {
extern struct cpuinfo_arc cpuinfo_arc700[];
static inline int is_isa_arcv2(void)
{
return IS_ENABLED(CONFIG_ISA_ARCV2);
}
static inline int is_isa_arcompact(void)
{
return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
}
#if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7)
#error "Toolchain not configured for ARCompact builds"
#elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS)
#error "Toolchain not configured for ARCv2 builds"
#endif
#endif /* __ASEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */