Merge branch '2_6_32_for_next' of git://git.pwsan.com/linux-2.6 into for-next
此提交包含在：
Tony Lindgren
@@ -0,0 +1,301 @@
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/*
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* omap-pm.h - OMAP power management interface
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*
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||||
* Copyright (C) 2008-2009 Texas Instruments, Inc.
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* Copyright (C) 2008-2009 Nokia Corporation
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* Paul Walmsley
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||||
*
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* Interface developed by (in alphabetical order): Karthik Dasu, Jouni
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* Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
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* Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
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* Richard Woodruff
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||||
*/
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#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
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#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
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#include <linux/device.h>
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#include <linux/cpufreq.h>
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#include "powerdomain.h"
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/**
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* struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
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* @rate: target clock rate
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* @opp_id: OPP ID
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* @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
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*
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* Operating performance point data. Can vary by OMAP chip and board.
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*/
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struct omap_opp {
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unsigned long rate;
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u8 opp_id;
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u16 min_vdd;
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};
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extern struct omap_opp *mpu_opps;
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extern struct omap_opp *dsp_opps;
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extern struct omap_opp *l3_opps;
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/*
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* agent_id values for use with omap_pm_set_min_bus_tput():
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*
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* OCP_INITIATOR_AGENT is only valid for devices that can act as
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* initiators -- it represents the device's L3 interconnect
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* connection. OCP_TARGET_AGENT represents the device's L4
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* interconnect connection.
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*/
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#define OCP_TARGET_AGENT 1
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#define OCP_INITIATOR_AGENT 2
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/**
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* omap_pm_if_early_init - OMAP PM init code called before clock fw init
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* @mpu_opp_table: array ptr to struct omap_opp for MPU
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* @dsp_opp_table: array ptr to struct omap_opp for DSP
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* @l3_opp_table : array ptr to struct omap_opp for CORE
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*
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* Initialize anything that must be configured before the clock
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* framework starts. The "_if_" is to avoid name collisions with the
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* PM idle-loop code.
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*/
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int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
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struct omap_opp *dsp_opp_table,
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struct omap_opp *l3_opp_table);
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/**
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* omap_pm_if_init - OMAP PM init code called after clock fw init
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*
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* The main initialization code. OPP tables are passed in here. The
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* "_if_" is to avoid name collisions with the PM idle-loop code.
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*/
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int __init omap_pm_if_init(void);
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/**
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* omap_pm_if_exit - OMAP PM exit code
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*
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* Exit code; currently unused. The "_if_" is to avoid name
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* collisions with the PM idle-loop code.
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*/
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void omap_pm_if_exit(void);
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/*
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* Device-driver-originated constraints (via board-*.c files, platform_data)
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*/
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/**
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* omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
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* @dev: struct device * requesting the constraint
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* @t: maximum MPU wakeup latency in microseconds
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*
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* Request that the maximum interrupt latency for the MPU to be no
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* greater than 't' microseconds. "Interrupt latency" in this case is
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* defined as the elapsed time from the occurrence of a hardware or
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* timer interrupt to the time when the device driver's interrupt
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* service routine has been entered by the MPU.
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*
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* It is intended that underlying PM code will use this information to
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* determine what power state to put the MPU powerdomain into, and
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* possibly the CORE powerdomain as well, since interrupt handling
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* code currently runs from SDRAM. Advanced PM or board*.c code may
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* also configure interrupt controller priorities, OCP bus priorities,
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* CPU speed(s), etc.
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*
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* This function will not affect device wakeup latency, e.g., time
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* elapsed from when a device driver enables a hardware device with
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* clk_enable(), to when the device is ready for register access or
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* other use. To control this device wakeup latency, use
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* set_max_dev_wakeup_lat()
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*
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* Multiple calls to set_max_mpu_wakeup_lat() will replace the
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* previous t value. To remove the latency target for the MPU, call
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* with t = -1.
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*
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* No return value.
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*/
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void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
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/**
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* omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
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* @dev: struct device * requesting the constraint
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* @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
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* @r: minimum throughput (in KiB/s)
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*
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* Request that the minimum data throughput on the OCP interconnect
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* attached to device 'dev' interconnect agent 'tbus_id' be no less
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* than 'r' KiB/s.
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*
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* It is expected that the OMAP PM or bus code will use this
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* information to set the interconnect clock to run at the lowest
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* possible speed that satisfies all current system users. The PM or
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* bus code will adjust the estimate based on its model of the bus, so
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* device driver authors should attempt to specify an accurate
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* quantity for their device use case, and let the PM or bus code
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* overestimate the numbers as necessary to handle request/response
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* latency, other competing users on the system, etc. On OMAP2/3, if
|
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* a driver requests a minimum L4 interconnect speed constraint, the
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* code will also need to add an minimum L3 interconnect speed
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* constraint,
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*
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* Multiple calls to set_min_bus_tput() will replace the previous rate
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* value for this device. To remove the interconnect throughput
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* restriction for this device, call with r = 0.
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*
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* No return value.
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*/
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void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
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/**
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* omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
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* @dev: struct device *
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* @t: maximum device wakeup latency in microseconds
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*
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* Request that the maximum amount of time necessary for a device to
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* become accessible after its clocks are enabled should be no greater
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* than 't' microseconds. Specifically, this represents the time from
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* when a device driver enables device clocks with clk_enable(), to
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* when the register reads and writes on the device will succeed.
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* This function should be called before clk_disable() is called,
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* since the power state transition decision may be made during
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* clk_disable().
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*
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* It is intended that underlying PM code will use this information to
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* determine what power state to put the powerdomain enclosing this
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* device into.
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*
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||||
* Multiple calls to set_max_dev_wakeup_lat() will replace the
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* previous wakeup latency values for this device. To remove the wakeup
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* latency restriction for this device, call with t = -1.
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*
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* No return value.
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*/
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void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
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/**
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* omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
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* @dev: struct device *
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* @t: maximum DMA transfer start latency in microseconds
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*
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* Request that the maximum system DMA transfer start latency for this
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* device 'dev' should be no greater than 't' microseconds. "DMA
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* transfer start latency" here is defined as the elapsed time from
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* when a device (e.g., McBSP) requests that a system DMA transfer
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* start or continue, to the time at which data starts to flow into
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* that device from the system DMA controller.
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*
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* It is intended that underlying PM code will use this information to
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* determine what power state to put the CORE powerdomain into.
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*
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* Since system DMA transfers may not involve the MPU, this function
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* will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
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* so. Similarly, this function will not affect device wakeup latency
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* -- use set_max_dev_wakeup_lat() to affect that.
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*
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* Multiple calls to set_max_sdma_lat() will replace the previous t
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* value for this device. To remove the maximum DMA latency for this
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* device, call with t = -1.
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*
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* No return value.
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*/
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void omap_pm_set_max_sdma_lat(struct device *dev, long t);
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/*
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* DSP Bridge-specific constraints
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*/
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/**
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* omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
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*
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* Intended for use by DSPBridge. Returns an array of OPP->DSP clock
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* frequency entries. The final item in the array should have .rate =
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* .opp_id = 0.
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*/
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const struct omap_opp *omap_pm_dsp_get_opp_table(void);
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/**
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* omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
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* @opp_id: target DSP OPP ID
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*
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* Set a minimum OPP ID for the DSP. This is intended to be called
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* only from the DSP Bridge MPU-side driver. Unfortunately, the only
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* information that code receives from the DSP/BIOS load estimator is the
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* target OPP ID; hence, this interface. No return value.
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*/
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void omap_pm_dsp_set_min_opp(u8 opp_id);
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/**
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* omap_pm_dsp_get_opp - report the current DSP OPP ID
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*
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* Report the current OPP for the DSP. Since on OMAP3, the DSP and
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* MPU share a single voltage domain, the OPP ID returned back may
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* represent a higher DSP speed than the OPP requested via
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* omap_pm_dsp_set_min_opp().
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*
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* Returns the current VDD1 OPP ID, or 0 upon error.
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*/
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u8 omap_pm_dsp_get_opp(void);
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/*
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* CPUFreq-originated constraint
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*
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* In the future, this should be handled by custom OPP clocktype
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* functions.
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*/
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/**
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* omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
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*
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* Provide a frequency table usable by CPUFreq for the current chip/board.
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* Returns a pointer to a struct cpufreq_frequency_table array or NULL
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* upon error.
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*/
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struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
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|
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/**
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* omap_pm_cpu_set_freq - set the current minimum MPU frequency
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* @f: MPU frequency in Hz
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*
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* Set the current minimum CPU frequency. The actual CPU frequency
|
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* used could end up higher if the DSP requested a higher OPP.
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* Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
|
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* return value.
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*/
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void omap_pm_cpu_set_freq(unsigned long f);
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/**
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* omap_pm_cpu_get_freq - report the current CPU frequency
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*
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* Returns the current MPU frequency, or 0 upon error.
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*/
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unsigned long omap_pm_cpu_get_freq(void);
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/*
|
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* Device context loss tracking
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*/
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/**
|
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* omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
|
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* @dev: struct device *
|
||||
*
|
||||
* This function returns the number of times that the device @dev has
|
||||
* lost its internal context. This generally occurs on a powerdomain
|
||||
* transition to OFF. Drivers use this as an optimization to avoid restoring
|
||||
* context if the device hasn't lost it. To use, drivers should initially
|
||||
* call this in their context save functions and store the result. Early in
|
||||
* the driver's context restore function, the driver should call this function
|
||||
* again, and compare the result to the stored counter. If they differ, the
|
||||
* driver must restore device context. If the number of context losses
|
||||
* exceeds the maximum positive integer, the function will wrap to 0 and
|
||||
* continue counting. Returns the number of context losses for this device,
|
||||
* or -EINVAL upon error.
|
||||
*/
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int omap_pm_get_dev_context_loss_count(struct device *dev);
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||||
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#endif
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@@ -0,0 +1,141 @@
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/*
|
||||
* omap_device headers
|
||||
*
|
||||
* Copyright (C) 2009 Nokia Corporation
|
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* Paul Walmsley
|
||||
*
|
||||
* Developed in collaboration with (alphabetical order): Benoit
|
||||
* Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
|
||||
* Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
|
||||
* Woodruff
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Eventually this type of functionality should either be
|
||||
* a) implemented via arch-specific pointers in platform_device
|
||||
* or
|
||||
* b) implemented as a proper omap_bus/omap_device in Linux, no more
|
||||
* platform_device
|
||||
*
|
||||
* omap_device differs from omap_hwmod in that it includes external
|
||||
* (e.g., board- and system-level) integration details. omap_hwmod
|
||||
* stores hardware data that is invariant for a given OMAP chip.
|
||||
*
|
||||
* To do:
|
||||
* - GPIO integration
|
||||
* - regulator integration
|
||||
*
|
||||
*/
|
||||
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
|
||||
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/omap_hwmod.h>
|
||||
|
||||
/* omap_device._state values */
|
||||
#define OMAP_DEVICE_STATE_UNKNOWN 0
|
||||
#define OMAP_DEVICE_STATE_ENABLED 1
|
||||
#define OMAP_DEVICE_STATE_IDLE 2
|
||||
#define OMAP_DEVICE_STATE_SHUTDOWN 3
|
||||
|
||||
/**
|
||||
* struct omap_device - omap_device wrapper for platform_devices
|
||||
* @pdev: platform_device
|
||||
* @hwmods: (one .. many per omap_device)
|
||||
* @hwmods_cnt: ARRAY_SIZE() of @hwmods
|
||||
* @pm_lats: ptr to an omap_device_pm_latency table
|
||||
* @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
|
||||
* @pm_lat_level: array index of the last odpl entry executed - -1 if never
|
||||
* @dev_wakeup_lat: dev wakeup latency in microseconds
|
||||
* @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
|
||||
* @_state: one of OMAP_DEVICE_STATE_* (see above)
|
||||
* @flags: device flags
|
||||
*
|
||||
* Integrates omap_hwmod data into Linux platform_device.
|
||||
*
|
||||
* Field names beginning with underscores are for the internal use of
|
||||
* the omap_device code.
|
||||
*
|
||||
*/
|
||||
struct omap_device {
|
||||
struct platform_device pdev;
|
||||
struct omap_hwmod **hwmods;
|
||||
struct omap_device_pm_latency *pm_lats;
|
||||
u32 dev_wakeup_lat;
|
||||
u32 _dev_wakeup_lat_limit;
|
||||
u8 pm_lats_cnt;
|
||||
s8 pm_lat_level;
|
||||
u8 hwmods_cnt;
|
||||
u8 _state;
|
||||
};
|
||||
|
||||
/* Device driver interface (call via platform_data fn ptrs) */
|
||||
|
||||
int omap_device_enable(struct platform_device *pdev);
|
||||
int omap_device_idle(struct platform_device *pdev);
|
||||
int omap_device_shutdown(struct platform_device *pdev);
|
||||
|
||||
/* Core code interface */
|
||||
|
||||
int omap_device_count_resources(struct omap_device *od);
|
||||
int omap_device_fill_resources(struct omap_device *od, struct resource *res);
|
||||
|
||||
struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
|
||||
struct omap_hwmod *oh, void *pdata,
|
||||
int pdata_len,
|
||||
struct omap_device_pm_latency *pm_lats,
|
||||
int pm_lats_cnt);
|
||||
|
||||
struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
|
||||
struct omap_hwmod **oh, int oh_cnt,
|
||||
void *pdata, int pdata_len,
|
||||
struct omap_device_pm_latency *pm_lats,
|
||||
int pm_lats_cnt);
|
||||
|
||||
int omap_device_register(struct omap_device *od);
|
||||
|
||||
/* OMAP PM interface */
|
||||
int omap_device_align_pm_lat(struct platform_device *pdev,
|
||||
u32 new_wakeup_lat_limit);
|
||||
struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
|
||||
|
||||
/* Other */
|
||||
|
||||
int omap_device_idle_hwmods(struct omap_device *od);
|
||||
int omap_device_enable_hwmods(struct omap_device *od);
|
||||
|
||||
int omap_device_disable_clocks(struct omap_device *od);
|
||||
int omap_device_enable_clocks(struct omap_device *od);
|
||||
|
||||
|
||||
/*
|
||||
* Entries should be kept in latency order ascending
|
||||
*
|
||||
* deact_lat is the maximum number of microseconds required to complete
|
||||
* deactivate_func() at the device's slowest OPP.
|
||||
*
|
||||
* act_lat is the maximum number of microseconds required to complete
|
||||
* activate_func() at the device's slowest OPP.
|
||||
*
|
||||
* This will result in some suboptimal power management decisions at fast
|
||||
* OPPs, but avoids having to recompute all device power management decisions
|
||||
* if the system shifts from a fast OPP to a slow OPP (in order to meet
|
||||
* latency requirements).
|
||||
*
|
||||
* XXX should deactivate_func/activate_func() take platform_device pointers
|
||||
* rather than omap_device pointers?
|
||||
*/
|
||||
struct omap_device_pm_latency {
|
||||
u32 deactivate_lat;
|
||||
int (*deactivate_func)(struct omap_device *od);
|
||||
u32 activate_lat;
|
||||
int (*activate_func)(struct omap_device *od);
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,447 @@
|
||||
/*
|
||||
* omap_hwmod macros, structures
|
||||
*
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* Created in collaboration with (alphabetical order): Benoit Cousson,
|
||||
* Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
|
||||
* Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* These headers and macros are used to define OMAP on-chip module
|
||||
* data and their integration with other OMAP modules and Linux.
|
||||
*
|
||||
* References:
|
||||
* - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
|
||||
* - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
|
||||
* - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
|
||||
* - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
|
||||
* - Open Core Protocol Specification 2.2
|
||||
*
|
||||
* To do:
|
||||
* - add interconnect error log structures
|
||||
* - add pinmuxing
|
||||
* - init_conn_id_bit (CONNID_BIT_VECTOR)
|
||||
* - implement default hwmod SMS/SDRC flags?
|
||||
*
|
||||
*/
|
||||
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
|
||||
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <mach/cpu.h>
|
||||
|
||||
struct omap_device;
|
||||
|
||||
/* OCP SYSCONFIG bit shifts/masks */
|
||||
#define SYSC_MIDLEMODE_SHIFT 12
|
||||
#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
|
||||
#define SYSC_CLOCKACTIVITY_SHIFT 8
|
||||
#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
|
||||
#define SYSC_SIDLEMODE_SHIFT 3
|
||||
#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
|
||||
#define SYSC_ENAWAKEUP_SHIFT 2
|
||||
#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
|
||||
#define SYSC_SOFTRESET_SHIFT 1
|
||||
#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
|
||||
|
||||
/* OCP SYSSTATUS bit shifts/masks */
|
||||
#define SYSS_RESETDONE_SHIFT 0
|
||||
#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
|
||||
|
||||
/* Master standby/slave idle mode flags */
|
||||
#define HWMOD_IDLEMODE_FORCE (1 << 0)
|
||||
#define HWMOD_IDLEMODE_NO (1 << 1)
|
||||
#define HWMOD_IDLEMODE_SMART (1 << 2)
|
||||
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_dma_info - MPU address space handled by the hwmod
|
||||
* @name: name of the DMA channel (module local name)
|
||||
* @dma_ch: DMA channel ID
|
||||
*
|
||||
* @name should be something short, e.g., "tx" or "rx". It is for use
|
||||
* by platform_get_resource_byname(). It is defined locally to the
|
||||
* hwmod.
|
||||
*/
|
||||
struct omap_hwmod_dma_info {
|
||||
const char *name;
|
||||
u16 dma_ch;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_opt_clk - optional clocks used by this hwmod
|
||||
* @role: "sys", "32k", "tv", etc -- for use in clk_get()
|
||||
* @clkdev_dev_id: opt clock: clkdev dev_id string
|
||||
* @clkdev_con_id: opt clock: clkdev con_id string
|
||||
* @_clk: pointer to the struct clk (filled in at runtime)
|
||||
*
|
||||
* The module's interface clock and main functional clock should not
|
||||
* be added as optional clocks.
|
||||
*/
|
||||
struct omap_hwmod_opt_clk {
|
||||
const char *role;
|
||||
const char *clkdev_dev_id;
|
||||
const char *clkdev_con_id;
|
||||
struct clk *_clk;
|
||||
};
|
||||
|
||||
|
||||
/* omap_hwmod_omap2_firewall.flags bits */
|
||||
#define OMAP_FIREWALL_L3 (1 << 0)
|
||||
#define OMAP_FIREWALL_L4 (1 << 1)
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
|
||||
* @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
|
||||
* @l4_fw_region: L4 firewall region ID
|
||||
* @l4_prot_group: L4 protection group ID
|
||||
* @flags: (see omap_hwmod_omap2_firewall.flags macros above)
|
||||
*/
|
||||
struct omap_hwmod_omap2_firewall {
|
||||
u8 l3_perm_bit;
|
||||
u8 l4_fw_region;
|
||||
u8 l4_prot_group;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* omap_hwmod_addr_space.flags bits
|
||||
*
|
||||
* ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
|
||||
* ADDR_TYPE_RT: Address space contains module register target data.
|
||||
*/
|
||||
#define ADDR_MAP_ON_INIT (1 << 0)
|
||||
#define ADDR_TYPE_RT (1 << 1)
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_addr_space - MPU address space handled by the hwmod
|
||||
* @pa_start: starting physical address
|
||||
* @pa_end: ending physical address
|
||||
* @flags: (see omap_hwmod_addr_space.flags macros above)
|
||||
*
|
||||
* Address space doesn't necessarily follow physical interconnect
|
||||
* structure. GPMC is one example.
|
||||
*/
|
||||
struct omap_hwmod_addr_space {
|
||||
u32 pa_start;
|
||||
u32 pa_end;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
|
||||
* interface to interact with the hwmod. Used to add sleep dependencies
|
||||
* when the module is enabled or disabled.
|
||||
*/
|
||||
#define OCP_USER_MPU (1 << 0)
|
||||
#define OCP_USER_SDMA (1 << 1)
|
||||
|
||||
/* omap_hwmod_ocp_if.flags bits */
|
||||
#define OCPIF_HAS_IDLEST (1 << 0)
|
||||
#define OCPIF_SWSUP_IDLE (1 << 1)
|
||||
#define OCPIF_CAN_BURST (1 << 2)
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_ocp_if - OCP interface data
|
||||
* @master: struct omap_hwmod that initiates OCP transactions on this link
|
||||
* @slave: struct omap_hwmod that responds to OCP transactions on this link
|
||||
* @addr: address space associated with this link
|
||||
* @clkdev_dev_id: interface clock: clkdev dev_id string
|
||||
* @clkdev_con_id: interface clock: clkdev con_id string
|
||||
* @_clk: pointer to the interface struct clk (filled in at runtime)
|
||||
* @fw: interface firewall data
|
||||
* @addr_cnt: ARRAY_SIZE(@addr)
|
||||
* @width: OCP data width
|
||||
* @thread_cnt: number of threads
|
||||
* @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
|
||||
* @user: initiators using this interface (see OCP_USER_* macros above)
|
||||
* @flags: OCP interface flags (see OCPIF_* macros above)
|
||||
*
|
||||
* It may also be useful to add a tag_cnt field for OCP2.x devices.
|
||||
*
|
||||
* Parameter names beginning with an underscore are managed internally by
|
||||
* the omap_hwmod code and should not be set during initialization.
|
||||
*/
|
||||
struct omap_hwmod_ocp_if {
|
||||
struct omap_hwmod *master;
|
||||
struct omap_hwmod *slave;
|
||||
struct omap_hwmod_addr_space *addr;
|
||||
const char *clkdev_dev_id;
|
||||
const char *clkdev_con_id;
|
||||
struct clk *_clk;
|
||||
union {
|
||||
struct omap_hwmod_omap2_firewall omap2;
|
||||
} fw;
|
||||
u8 addr_cnt;
|
||||
u8 width;
|
||||
u8 thread_cnt;
|
||||
u8 max_burst_len;
|
||||
u8 user;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
|
||||
/* Macros for use in struct omap_hwmod_sysconfig */
|
||||
|
||||
/* Flags for use in omap_hwmod_sysconfig.idlemodes */
|
||||
#define MASTER_STANDBY_SHIFT 2
|
||||
#define SLAVE_IDLE_SHIFT 0
|
||||
#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
|
||||
#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
|
||||
#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
|
||||
#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
|
||||
#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
|
||||
#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
|
||||
|
||||
/* omap_hwmod_sysconfig.sysc_flags capability flags */
|
||||
#define SYSC_HAS_AUTOIDLE (1 << 0)
|
||||
#define SYSC_HAS_SOFTRESET (1 << 1)
|
||||
#define SYSC_HAS_ENAWAKEUP (1 << 2)
|
||||
#define SYSC_HAS_EMUFREE (1 << 3)
|
||||
#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
|
||||
#define SYSC_HAS_SIDLEMODE (1 << 5)
|
||||
#define SYSC_HAS_MIDLEMODE (1 << 6)
|
||||
#define SYSS_MISSING (1 << 7)
|
||||
|
||||
/* omap_hwmod_sysconfig.clockact flags */
|
||||
#define CLOCKACT_TEST_BOTH 0x0
|
||||
#define CLOCKACT_TEST_MAIN 0x1
|
||||
#define CLOCKACT_TEST_ICLK 0x2
|
||||
#define CLOCKACT_TEST_NONE 0x3
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
|
||||
* @rev_offs: IP block revision register offset (from module base addr)
|
||||
* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
|
||||
* @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
|
||||
* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
|
||||
* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
|
||||
* @clockact: the default value of the module CLOCKACTIVITY bits
|
||||
*
|
||||
* @clockact describes to the module which clocks are likely to be
|
||||
* disabled when the PRCM issues its idle request to the module. Some
|
||||
* modules have separate clockdomains for the interface clock and main
|
||||
* functional clock, and can check whether they should acknowledge the
|
||||
* idle request based on the internal module functionality that has
|
||||
* been associated with the clocks marked in @clockact. This field is
|
||||
* only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
|
||||
*
|
||||
*/
|
||||
struct omap_hwmod_sysconfig {
|
||||
u16 rev_offs;
|
||||
u16 sysc_offs;
|
||||
u16 syss_offs;
|
||||
u8 idlemodes;
|
||||
u8 sysc_flags;
|
||||
u8 clockact;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
|
||||
* @module_offs: PRCM submodule offset from the start of the PRM/CM
|
||||
* @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
|
||||
* @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
|
||||
* @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
|
||||
* @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
|
||||
* @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
|
||||
*
|
||||
* @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
|
||||
* WKEN, GRPSEL registers. In an ideal world, no extra information
|
||||
* would be needed for IDLEST information, but alas, there are some
|
||||
* exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
|
||||
* are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
|
||||
*/
|
||||
struct omap_hwmod_omap2_prcm {
|
||||
s16 module_offs;
|
||||
u8 prcm_reg_id;
|
||||
u8 module_bit;
|
||||
u8 idlest_reg_id;
|
||||
u8 idlest_idle_bit;
|
||||
u8 idlest_stdby_bit;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
|
||||
* @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
|
||||
* @device_offs: device register offset from @module_offs
|
||||
* @submodule_wkdep_bit: bit shift of the WKDEP range
|
||||
*/
|
||||
struct omap_hwmod_omap4_prcm {
|
||||
u32 module_offs;
|
||||
u16 device_offs;
|
||||
u8 submodule_wkdep_bit;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* omap_hwmod.flags definitions
|
||||
*
|
||||
* HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
|
||||
* of idle, rather than relying on module smart-idle
|
||||
* HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
|
||||
* of standby, rather than relying on module smart-standby
|
||||
* HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
|
||||
* SDRAM controller, etc.
|
||||
* HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
|
||||
* controller, etc.
|
||||
* HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
|
||||
*/
|
||||
#define HWMOD_SWSUP_SIDLE (1 << 0)
|
||||
#define HWMOD_SWSUP_MSTANDBY (1 << 1)
|
||||
#define HWMOD_INIT_NO_RESET (1 << 2)
|
||||
#define HWMOD_INIT_NO_IDLE (1 << 3)
|
||||
#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4)
|
||||
|
||||
/*
|
||||
* omap_hwmod._int_flags definitions
|
||||
* These are for internal use only and are managed by the omap_hwmod code.
|
||||
*
|
||||
* _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
|
||||
* _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
|
||||
* _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
|
||||
*/
|
||||
#define _HWMOD_NO_MPU_PORT (1 << 0)
|
||||
#define _HWMOD_WAKEUP_ENABLED (1 << 1)
|
||||
#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
|
||||
|
||||
/*
|
||||
* omap_hwmod._state definitions
|
||||
*
|
||||
* INITIALIZED: reset (optionally), initialized, enabled, disabled
|
||||
* (optionally)
|
||||
*
|
||||
*
|
||||
*/
|
||||
#define _HWMOD_STATE_UNKNOWN 0
|
||||
#define _HWMOD_STATE_REGISTERED 1
|
||||
#define _HWMOD_STATE_CLKS_INITED 2
|
||||
#define _HWMOD_STATE_INITIALIZED 3
|
||||
#define _HWMOD_STATE_ENABLED 4
|
||||
#define _HWMOD_STATE_IDLE 5
|
||||
#define _HWMOD_STATE_DISABLED 6
|
||||
|
||||
/**
|
||||
* struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
|
||||
* @name: name of the hwmod
|
||||
* @od: struct omap_device currently associated with this hwmod (internal use)
|
||||
* @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
|
||||
* @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
|
||||
* @prcm: PRCM data pertaining to this hwmod
|
||||
* @clkdev_dev_id: main clock: clkdev dev_id string
|
||||
* @clkdev_con_id: main clock: clkdev con_id string
|
||||
* @_clk: pointer to the main struct clk (filled in at runtime)
|
||||
* @opt_clks: other device clocks that drivers can request (0..*)
|
||||
* @masters: ptr to array of OCP ifs that this hwmod can initiate on
|
||||
* @slaves: ptr to array of OCP ifs that this hwmod can respond on
|
||||
* @sysconfig: device SYSCONFIG/SYSSTATUS register data
|
||||
* @dev_attr: arbitrary device attributes that can be passed to the driver
|
||||
* @_sysc_cache: internal-use hwmod flags
|
||||
* @_rt_va: cached register target start address (internal use)
|
||||
* @_mpu_port_index: cached MPU register target slave ID (internal use)
|
||||
* @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
|
||||
* @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
|
||||
* @mpu_irqs_cnt: number of @mpu_irqs
|
||||
* @sdma_chs_cnt: number of @sdma_chs
|
||||
* @opt_clks_cnt: number of @opt_clks
|
||||
* @master_cnt: number of @master entries
|
||||
* @slaves_cnt: number of @slave entries
|
||||
* @response_lat: device OCP response latency (in interface clock cycles)
|
||||
* @_int_flags: internal-use hwmod flags
|
||||
* @_state: internal-use hwmod state
|
||||
* @flags: hwmod flags (documented below)
|
||||
* @omap_chip: OMAP chips this hwmod is present on
|
||||
* @node: list node for hwmod list (internal use)
|
||||
*
|
||||
* @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
|
||||
* clock," which for our purposes is defined as "the functional clock needed
|
||||
* for register accesses to complete." Modules may not have a main clock if
|
||||
* the interface clock also serves as a main clock.
|
||||
*
|
||||
* Parameter names beginning with an underscore are managed internally by
|
||||
* the omap_hwmod code and should not be set during initialization.
|
||||
*/
|
||||
struct omap_hwmod {
|
||||
const char *name;
|
||||
struct omap_device *od;
|
||||
u8 *mpu_irqs;
|
||||
struct omap_hwmod_dma_info *sdma_chs;
|
||||
union {
|
||||
struct omap_hwmod_omap2_prcm omap2;
|
||||
struct omap_hwmod_omap4_prcm omap4;
|
||||
} prcm;
|
||||
const char *clkdev_dev_id;
|
||||
const char *clkdev_con_id;
|
||||
struct clk *_clk;
|
||||
struct omap_hwmod_opt_clk *opt_clks;
|
||||
struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
|
||||
struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
|
||||
struct omap_hwmod_sysconfig *sysconfig;
|
||||
void *dev_attr;
|
||||
u32 _sysc_cache;
|
||||
void __iomem *_rt_va;
|
||||
struct list_head node;
|
||||
u16 flags;
|
||||
u8 _mpu_port_index;
|
||||
u8 msuspendmux_reg_id;
|
||||
u8 msuspendmux_shift;
|
||||
u8 response_lat;
|
||||
u8 mpu_irqs_cnt;
|
||||
u8 sdma_chs_cnt;
|
||||
u8 opt_clks_cnt;
|
||||
u8 masters_cnt;
|
||||
u8 slaves_cnt;
|
||||
u8 hwmods_cnt;
|
||||
u8 _int_flags;
|
||||
u8 _state;
|
||||
const struct omap_chip_id omap_chip;
|
||||
};
|
||||
|
||||
int omap_hwmod_init(struct omap_hwmod **ohs);
|
||||
int omap_hwmod_register(struct omap_hwmod *oh);
|
||||
int omap_hwmod_unregister(struct omap_hwmod *oh);
|
||||
struct omap_hwmod *omap_hwmod_lookup(const char *name);
|
||||
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
|
||||
int omap_hwmod_late_init(void);
|
||||
|
||||
int omap_hwmod_enable(struct omap_hwmod *oh);
|
||||
int omap_hwmod_idle(struct omap_hwmod *oh);
|
||||
int omap_hwmod_shutdown(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
|
||||
int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_reset(struct omap_hwmod *oh);
|
||||
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
|
||||
|
||||
void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
|
||||
u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
|
||||
|
||||
int omap_hwmod_count_resources(struct omap_hwmod *oh);
|
||||
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
|
||||
|
||||
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
|
||||
struct omap_hwmod *init_oh);
|
||||
int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
|
||||
struct omap_hwmod *init_oh);
|
||||
|
||||
int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
|
||||
int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
|
||||
int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
|
||||
int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
|
||||
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
|
||||
|
||||
#endif
|
||||
@@ -21,19 +21,28 @@
|
||||
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
|
||||
|
||||
#define SDRC_SYSCONFIG 0x010
|
||||
#define SDRC_CS_CFG 0x040
|
||||
#define SDRC_SHARING 0x044
|
||||
#define SDRC_ERR_TYPE 0x04C
|
||||
#define SDRC_DLLA_CTRL 0x060
|
||||
#define SDRC_DLLA_STATUS 0x064
|
||||
#define SDRC_DLLB_CTRL 0x068
|
||||
#define SDRC_DLLB_STATUS 0x06C
|
||||
#define SDRC_POWER 0x070
|
||||
#define SDRC_MCFG_0 0x080
|
||||
#define SDRC_MR_0 0x084
|
||||
#define SDRC_EMR2_0 0x08c
|
||||
#define SDRC_ACTIM_CTRL_A_0 0x09c
|
||||
#define SDRC_ACTIM_CTRL_B_0 0x0a0
|
||||
#define SDRC_RFR_CTRL_0 0x0a4
|
||||
#define SDRC_MANUAL_0 0x0a8
|
||||
#define SDRC_MCFG_1 0x0B0
|
||||
#define SDRC_MR_1 0x0B4
|
||||
#define SDRC_EMR2_1 0x0BC
|
||||
#define SDRC_ACTIM_CTRL_A_1 0x0C4
|
||||
#define SDRC_ACTIM_CTRL_B_1 0x0C8
|
||||
#define SDRC_RFR_CTRL_1 0x0D4
|
||||
#define SDRC_MANUAL_1 0x0D8
|
||||
|
||||
/*
|
||||
* These values represent the number of memory clock cycles between
|
||||
|
||||
@@ -13,6 +13,8 @@
|
||||
#ifndef __ASM_ARCH_SERIAL_H
|
||||
#define __ASM_ARCH_SERIAL_H
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP1)
|
||||
/* OMAP1 serial ports */
|
||||
#define OMAP_UART1_BASE 0xfffb0000
|
||||
@@ -53,6 +55,7 @@
|
||||
})
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
extern void __init omap_serial_early_init(void);
|
||||
extern void omap_serial_init(void);
|
||||
extern int omap_uart_can_sleep(void);
|
||||
extern void omap_uart_check_wakeup(void);
|
||||
|
||||
新增問題並參考
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