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Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next

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* clk-qcom-gdsc-warn:
  clk: qcom: gdsc: WARN when failing to toggle

* clk-ingenic:
  MIPS: Remove dead code
  clk: ingenic: Remove unused functions
  MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode
  clk: ingenic: Handle setting the Low-Power Mode bit
  clk: ingenic: Add missing header in cgu.h
  clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly
  clk: ingenic/jz4725b: Fix incorrect dividers for main clocks
  clk: ingenic/jz4770: Fix incorrect dividers for main clocks
  clk: ingenic/jz4740: Fix incorrect dividers for main clocks
  clk: ingenic: Add support for divider tables

* clk-qcom-qcs404-reset:
  clk: gcc-qcs404: Add PCIe resets

* clk-xgene-limit:
  clk: xgene: Don't build COMMON_CLK_XGENE by default

* clk-meson:
  clk: meson: g12a: mark fclk_div3 as critical
  clk: meson: g12a: Add support for G12B CPUB clocks
  dt-bindings: clk: meson: add g12b periph clock controller bindings
  clk: meson-g12a: add temperature sensor clocks
  dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
  clk: meson: meson8b: add the cts_i958 clock
  clk: meson: meson8b: add the cts_mclk_i958 clocks
  clk: meson: meson8b: add the cts_amclk clocks
  dt-bindings: clock: meson8b: add the audio clocks
  clk: meson: g12a: add controller register init
  clk: meson: eeclk: add init regs
  clk: meson: g12a: add mpll register init sequences
  clk: meson: mpll: add init callback and regs
  clk: meson: axg: spread spectrum is on mpll2
  clk: meson: gxbb: no spread spectrum on mpll0
  clk: meson: mpll: properly handle spread spectrum
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
This commit is contained in:
Stephen Boyd
2019-07-12 11:10:52 -07:00
parent b6bb2bc2fd f02fba3aa8 4abf9adc12 e5bbbff5b7 ce9a104643 afa88bdbf1
commit 1f5d580cab
31 changed files with 1298 additions and 208 deletions
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3
include/dt-bindings/clock/g12a-clkc.h
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@@ -130,11 +130,12 @@
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212
#endif /* __G12A_CLKC_H */

3
include/dt-bindings/clock/meson8b-clkc.h
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@@ -112,5 +112,8 @@
#define CLKID_VDEC_HCODEC 199
#define CLKID_VDEC_2 202
#define CLKID_VDEC_HEVC 206
#define CLKID_CTS_AMCLK 209
#define CLKID_CTS_MCLK_I958 212
#define CLKID_CTS_I958 213
#endif /* __MESON8B_CLKC_H */

7
include/dt-bindings/clock/qcom,gcc-qcs404.h
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@@ -166,5 +166,12 @@
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#define GCC_CDSP_RESTART 14
#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
#define GCC_PCIE_0_AHB_ARES 16
#define GCC_PCIE_0_AXI_SLAVE_ARES 17
#define GCC_PCIE_0_AXI_MASTER_ARES 18
#define GCC_PCIE_0_CORE_STICKY_ARES 19
#define GCC_PCIE_0_SLEEP_ARES 20
#define GCC_PCIE_0_PIPE_ARES 21
#endif