arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards
- enable USB for g12a boards

* tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits)
  arm64: dts: meson-g12a-u200: Add support for Video Display
  arm64: dts: meson-g12a-sei510: Add support for Video Display
  arm64: dts: meson-g12a-x96-max: Add support for Video Display
  arm64: dts: meson-g12a: Add AO-CEC nodes
  arm64: dts: meson-g12a: Add VPU and HDMI related nodes
  arm64: dts: meson-g12a-x96-max: Enable USB
  arm64: dts: meson-g12a-u200: Enable USB
  arm64: dts: meson-g12a-sei510: Enable USB
  arm64: dts: meson-g12a-sei510: Add ADC Key and BT support
  arm64: dts: meson-g12a-u200: add regulators
  arm64: dts: meson: g12a: Add mali-g31 gpu node
  arm64: dts: meson: g12a: Add G12A USB nodes
  arm64: dts: meson: g12a: Add SAR ADC node
  dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible
  arm64: dts: meson-gxm: Add Mali-T820 node
  dt-bindings: gpu: mali-midgard: Add resets property
  dt-bindings: clock: meson8b: export the video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2019-04-28 12:50:02 -07:00
14 changed files with 654 additions and 25 deletions

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@@ -7,26 +7,6 @@
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31

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@@ -26,7 +26,9 @@
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28

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@@ -131,5 +131,10 @@
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#endif /* __G12A_CLKC_H */

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@@ -103,10 +103,14 @@
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
#define CLKID_ABP 124
#define CLKID_APB 124
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
#define CLKID_VPU 190
#define CLKID_VDEC_1 196
#define CLKID_VDEC_HCODEC 199
#define CLKID_VDEC_2 202
#define CLKID_VDEC_HEVC 206
#endif /* __MESON8B_CLKC_H */