Merge tag 'iommu-updates-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: - Conversion of the AMD IOMMU driver to use the dma-iommu code for imlementing the DMA-API. This gets rid of quite some code in the driver itself, but also has some potential for regressions (non are known at the moment). - Support for the Qualcomm SMMUv2 implementation in the SDM845 SoC. This also includes some firmware interface changes, but those are acked by the respective maintainers. - Preparatory work to support two distinct page-tables per domain in the ARM-SMMU driver - Power management improvements for the ARM SMMUv2 - Custom PASID allocator support - Multiple PCI DMA alias support for the AMD IOMMU driver - Adaption of the Mediatek driver to the changed IO/TLB flush interface of the IOMMU core code. - Preparatory patches for the Renesas IOMMU driver to support future hardware. * tag 'iommu-updates-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (62 commits) iommu/rockchip: Don't provoke WARN for harmless IRQs iommu/vt-d: Turn off translations at shutdown iommu/vt-d: Check VT-d RMRR region in BIOS is reported as reserved iommu/arm-smmu: Remove duplicate error message iommu/arm-smmu-v3: Don't display an error when IRQ lines are missing iommu/ipmmu-vmsa: Add utlb_offset_base iommu/ipmmu-vmsa: Add helper functions for "uTLB" registers iommu/ipmmu-vmsa: Calculate context registers' offset instead of a macro iommu/ipmmu-vmsa: Add helper functions for MMU "context" registers iommu/ipmmu-vmsa: tidyup register definitions iommu/ipmmu-vmsa: Remove all unused register definitions iommu/mediatek: Reduce the tlb flush timeout value iommu/mediatek: Get rid of the pgtlock iommu/mediatek: Move the tlb_sync into tlb_flush iommu/mediatek: Delete the leaf in the tlb_flush iommu/mediatek: Use gather to achieve the tlb range flush iommu/mediatek: Add a new tlb_lock for tlb_flush iommu/mediatek: Correct the flush_iotlb_all callback iommu/io-pgtable-arm: Rename IOMMU_QCOM_SYS_CACHE and improve doc iommu/io-pgtable-arm: Rationalise MAIR handling ...
This commit is contained in:
Linus Torvalds
@@ -152,4 +152,173 @@ struct iommu_page_response {
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__u32 code;
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};
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/* defines the granularity of the invalidation */
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enum iommu_inv_granularity {
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IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */
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IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */
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IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */
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IOMMU_INV_GRANU_NR, /* number of invalidation granularities */
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};
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/**
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* struct iommu_inv_addr_info - Address Selective Invalidation Structure
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*
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* @flags: indicates the granularity of the address-selective invalidation
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* - If the PASID bit is set, the @pasid field is populated and the invalidation
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* relates to cache entries tagged with this PASID and matching the address
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* range.
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* - If ARCHID bit is set, @archid is populated and the invalidation relates
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* to cache entries tagged with this architecture specific ID and matching
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* the address range.
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* - Both PASID and ARCHID can be set as they may tag different caches.
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* - If neither PASID or ARCHID is set, global addr invalidation applies.
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* - The LEAF flag indicates whether only the leaf PTE caching needs to be
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* invalidated and other paging structure caches can be preserved.
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* @pasid: process address space ID
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* @archid: architecture-specific ID
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* @addr: first stage/level input address
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* @granule_size: page/block size of the mapping in bytes
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* @nb_granules: number of contiguous granules to be invalidated
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*/
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struct iommu_inv_addr_info {
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#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0)
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#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1)
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#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2)
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__u32 flags;
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__u32 archid;
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__u64 pasid;
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__u64 addr;
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__u64 granule_size;
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__u64 nb_granules;
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};
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/**
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* struct iommu_inv_pasid_info - PASID Selective Invalidation Structure
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*
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* @flags: indicates the granularity of the PASID-selective invalidation
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* - If the PASID bit is set, the @pasid field is populated and the invalidation
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* relates to cache entries tagged with this PASID and matching the address
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* range.
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* - If the ARCHID bit is set, the @archid is populated and the invalidation
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* relates to cache entries tagged with this architecture specific ID and
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* matching the address range.
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* - Both PASID and ARCHID can be set as they may tag different caches.
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* - At least one of PASID or ARCHID must be set.
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* @pasid: process address space ID
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* @archid: architecture-specific ID
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*/
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struct iommu_inv_pasid_info {
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#define IOMMU_INV_PASID_FLAGS_PASID (1 << 0)
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#define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1)
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__u32 flags;
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__u32 archid;
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__u64 pasid;
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};
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/**
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* struct iommu_cache_invalidate_info - First level/stage invalidation
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* information
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* @version: API version of this structure
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* @cache: bitfield that allows to select which caches to invalidate
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* @granularity: defines the lowest granularity used for the invalidation:
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* domain > PASID > addr
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* @padding: reserved for future use (should be zero)
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* @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID
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* @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR
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*
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* Not all the combinations of cache/granularity are valid:
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*
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* +--------------+---------------+---------------+---------------+
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* | type / | DEV_IOTLB | IOTLB | PASID |
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* | granularity | | | cache |
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* +==============+===============+===============+===============+
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* | DOMAIN | N/A | Y | Y |
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* +--------------+---------------+---------------+---------------+
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* | PASID | Y | Y | Y |
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* +--------------+---------------+---------------+---------------+
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* | ADDR | Y | Y | N/A |
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* +--------------+---------------+---------------+---------------+
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*
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* Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than
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* @version and @cache.
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*
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* If multiple cache types are invalidated simultaneously, they all
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* must support the used granularity.
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*/
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struct iommu_cache_invalidate_info {
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#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1
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__u32 version;
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/* IOMMU paging structure cache */
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#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */
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#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */
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#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */
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#define IOMMU_CACHE_INV_TYPE_NR (3)
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__u8 cache;
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__u8 granularity;
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__u8 padding[2];
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union {
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struct iommu_inv_pasid_info pasid_info;
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struct iommu_inv_addr_info addr_info;
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};
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};
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/**
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* struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest
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* SVA binding.
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*
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* @flags: VT-d PASID table entry attributes
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* @pat: Page attribute table data to compute effective memory type
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* @emt: Extended memory type
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*
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* Only guest vIOMMU selectable and effective options are passed down to
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* the host IOMMU.
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*/
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struct iommu_gpasid_bind_data_vtd {
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#define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */
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#define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */
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#define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */
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#define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */
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#define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */
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#define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */
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__u64 flags;
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__u32 pat;
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__u32 emt;
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};
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/**
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* struct iommu_gpasid_bind_data - Information about device and guest PASID binding
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* @version: Version of this data structure
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* @format: PASID table entry format
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* @flags: Additional information on guest bind request
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* @gpgd: Guest page directory base of the guest mm to bind
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* @hpasid: Process address space ID used for the guest mm in host IOMMU
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* @gpasid: Process address space ID used for the guest mm in guest IOMMU
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* @addr_width: Guest virtual address width
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* @padding: Reserved for future use (should be zero)
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* @vtd: Intel VT-d specific data
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*
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* Guest to host PASID mapping can be an identity or non-identity, where guest
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* has its own PASID space. For non-identify mapping, guest to host PASID lookup
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* is needed when VM programs guest PASID into an assigned device. VMM may
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* trap such PASID programming then request host IOMMU driver to convert guest
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* PASID to host PASID based on this bind data.
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*/
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struct iommu_gpasid_bind_data {
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#define IOMMU_GPASID_BIND_VERSION_1 1
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__u32 version;
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#define IOMMU_PASID_FORMAT_INTEL_VTD 1
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__u32 format;
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#define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */
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__u64 flags;
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__u64 gpgd;
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__u64 hpasid;
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__u64 gpasid;
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__u32 addr_width;
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__u8 padding[12];
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/* Vendor specific data */
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union {
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struct iommu_gpasid_bind_data_vtd vtd;
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};
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};
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#endif /* _UAPI_IOMMU_H */
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