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Linux-2.6.12-rc2

瀏覽代碼 
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
當前提交 1da177e4c3
共有 17291 個文件被更改，包括 6718755 次插入 和 0 次删除
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12
sound/pci/ice1712/Makefile Normal file
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@@ -0,0 +1,12 @@
#
# Makefile for ALSA
# Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz>
#
snd-ice17xx-ak4xxx-objs := ak4xxx.o
snd-ice1712-objs := ice1712.o delta.o hoontech.o ews.o
snd-ice1724-objs := ice1724.o amp.o revo.o aureon.o vt1720_mobo.o pontis.o prodigy192.o juli.o phase.o
# Toplevel Module Dependency
obj-$(CONFIG_SND_ICE1712) += snd-ice1712.o snd-ice17xx-ak4xxx.o
obj-$(CONFIG_SND_ICE1724) += snd-ice1724.o snd-ice17xx-ak4xxx.o

194
sound/pci/ice1712/ak4xxx.c Normal file
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@@ -0,0 +1,194 @@
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* AK4524 / AK4528 / AK4529 / AK4355 / AK4381 interface
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <sound/core.h>
#include <sound/initval.h>
#include "ice1712.h"
MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
MODULE_DESCRIPTION("ICEnsemble ICE17xx <-> AK4xxx AD/DA chip interface");
MODULE_LICENSE("GPL");
static void snd_ice1712_akm4xxx_lock(akm4xxx_t *ak, int chip)
{
ice1712_t *ice = ak->private_data[0];
snd_ice1712_save_gpio_status(ice);
}
static void snd_ice1712_akm4xxx_unlock(akm4xxx_t *ak, int chip)
{
ice1712_t *ice = ak->private_data[0];
snd_ice1712_restore_gpio_status(ice);
}
/*
* write AK4xxx register
*/
static void snd_ice1712_akm4xxx_write(akm4xxx_t *ak, int chip,
unsigned char addr, unsigned char data)
{
unsigned int tmp;
int idx;
unsigned int addrdata;
struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
ice1712_t *ice = ak->private_data[0];
snd_assert(chip >= 0 && chip < 4, return);
tmp = snd_ice1712_gpio_read(ice);
tmp |= priv->add_flags;
tmp &= ~priv->mask_flags;
if (priv->cs_mask == priv->cs_addr) {
if (priv->cif) {
tmp |= priv->cs_mask; /* start without chip select */
} else {
tmp &= ~priv->cs_mask; /* chip select low */
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
}
} else {
/* doesn't handle cf=1 yet */
tmp &= ~priv->cs_mask;
tmp |= priv->cs_addr;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
}
/* build I2C address + data byte */
addrdata = (priv->caddr << 6) | 0x20 | (addr & 0x1f);
addrdata = (addrdata << 8) | data;
for (idx = 15; idx >= 0; idx--) {
/* drop clock */
tmp &= ~priv->clk_mask;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
/* set data */
if (addrdata & (1 << idx))
tmp |= priv->data_mask;
else
tmp &= ~priv->data_mask;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
/* raise clock */
tmp |= priv->clk_mask;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
}
if (priv->cs_mask == priv->cs_addr) {
if (priv->cif) {
/* assert a cs pulse to trigger */
tmp &= ~priv->cs_mask;
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
}
tmp |= priv->cs_mask; /* chip select high to trigger */
} else {
tmp &= ~priv->cs_mask;
tmp |= priv->cs_none; /* deselect address */
}
snd_ice1712_gpio_write(ice, tmp);
udelay(1);
}
/*
* initialize the akm4xxx_t record with the template
*/
int snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *temp,
const struct snd_ak4xxx_private *_priv, ice1712_t *ice)
{
struct snd_ak4xxx_private *priv;
if (_priv != NULL) {
priv = kmalloc(sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
*priv = *_priv;
} else {
priv = NULL;
}
*ak = *temp;
ak->card = ice->card;
ak->private_value[0] = (unsigned long)priv;
ak->private_data[0] = ice;
if (ak->ops.lock == NULL)
ak->ops.lock = snd_ice1712_akm4xxx_lock;
if (ak->ops.unlock == NULL)
ak->ops.unlock = snd_ice1712_akm4xxx_unlock;
if (ak->ops.write == NULL)
ak->ops.write = snd_ice1712_akm4xxx_write;
snd_akm4xxx_init(ak);
return 0;
}
void snd_ice1712_akm4xxx_free(ice1712_t *ice)
{
unsigned int akidx;
if (ice->akm == NULL)
return;
for (akidx = 0; akidx < ice->akm_codecs; akidx++) {
akm4xxx_t *ak = &ice->akm[akidx];
kfree((void*)ak->private_value[0]);
}
kfree(ice->akm);
}
/*
* build AK4xxx controls
*/
int snd_ice1712_akm4xxx_build_controls(ice1712_t *ice)
{
unsigned int akidx;
int err;
for (akidx = 0; akidx < ice->akm_codecs; akidx++) {
akm4xxx_t *ak = &ice->akm[akidx];
err = snd_akm4xxx_build_controls(ak);
if (err < 0)
return err;
}
return 0;
}
static int __init alsa_ice1712_akm4xxx_module_init(void)
{
return 0;
}
static void __exit alsa_ice1712_akm4xxx_module_exit(void)
{
}
module_init(alsa_ice1712_akm4xxx_module_init)
module_exit(alsa_ice1712_akm4xxx_module_exit)
EXPORT_SYMBOL(snd_ice1712_akm4xxx_init);
EXPORT_SYMBOL(snd_ice1712_akm4xxx_free);
EXPORT_SYMBOL(snd_ice1712_akm4xxx_build_controls);

65
sound/pci/ice1712/amp.c Normal file
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/*
* ALSA driver for ICEnsemble VT1724 (Envy24HT)
*
* Lowlevel functions for Advanced Micro Peripherals Ltd AUDIO2000
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "amp.h"
static int __devinit snd_vt1724_amp_init(ice1712_t *ice)
{
/* only use basic functionality for now */
ice->num_total_dacs = 2; /* only PSDOUT0 is connected */
ice->num_total_adcs = 2;
return 0;
}
static int __devinit snd_vt1724_amp_add_controls(ice1712_t *ice)
{
/* we use pins 39 and 41 of the VT1616 for left and right read outputs */
snd_ac97_write_cache(ice->ac97, 0x5a, snd_ac97_read(ice->ac97, 0x5a) & ~0x8000);
return 0;
}
/* entry point */
struct snd_ice1712_card_info snd_vt1724_amp_cards[] __devinitdata = {
{
.subvendor = VT1724_SUBDEVICE_AUDIO2000,
.name = "AMP Ltd AUDIO2000",
.model = "amp2000",
.chip_init = snd_vt1724_amp_init,
.build_controls = snd_vt1724_amp_add_controls,
},
{ } /* terminator */
};

34
sound/pci/ice1712/amp.h Normal file
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@@ -0,0 +1,34 @@
#ifndef __SOUND_AMP_H
#define __SOUND_AMP_H
/*
* ALSA driver for VIA VT1724 (Envy24HT)
*
* Lowlevel functions for Advanced Micro Peripherals Ltd AUDIO2000
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define AMP_AUDIO2000_DEVICE_DESC "{AMP Ltd,AUDIO2000},"
#define VT1724_SUBDEVICE_AUDIO2000 0x12142417 /* Advanced Micro Peripherals Ltd AUDIO2000 */
extern struct snd_ice1712_card_info snd_vt1724_amp_cards[];
#endif /* __SOUND_AMP_H */

1948
sound/pci/ice1712/aureon.c Normal file
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文件差異過大導致無法顯示 Load Diff

56
sound/pci/ice1712/aureon.h Normal file
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@@ -0,0 +1,56 @@
#ifndef __SOUND_AUREON_H
#define __SOUND_AUREON_H
/*
* ALSA driver for VIA VT1724 (Envy24HT)
*
* Lowlevel functions for Terratec Aureon cards
*
* Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define AUREON_DEVICE_DESC "{Terratec,Aureon 5.1 Sky},"\
"{Terratec,Aureon 7.1 Space},"\
"{Terratec,Aureon 7.1 Universe}," \
"{AudioTrak,Prodigy 7.1},"
#define VT1724_SUBDEVICE_AUREON51_SKY 0x3b154711 /* Aureon 5.1 Sky */
#define VT1724_SUBDEVICE_AUREON71_SPACE 0x3b154511 /* Aureon 7.1 Space */
#define VT1724_SUBDEVICE_AUREON71_UNIVERSE 0x3b155311 /* Aureon 7.1 Universe */
#define VT1724_SUBDEVICE_PRODIGY71 0x33495345 /* PRODIGY 7.1 */
extern struct snd_ice1712_card_info snd_vt1724_aureon_cards[];
/* GPIO bits */
#define AUREON_CS8415_CS (1 << 22)
#define AUREON_SPI_MISO (1 << 21)
#define AUREON_WM_RESET (1 << 20)
#define AUREON_SPI_CLK (1 << 19)
#define AUREON_SPI_MOSI (1 << 18)
#define AUREON_WM_RW (1 << 17)
#define AUREON_AC97_RESET (1 << 16)
#define AUREON_DIGITAL_SEL1 (1 << 15)
#define AUREON_HP_SEL (1 << 14)
#define AUREON_WM_CS (1 << 12)
#define AUREON_AC97_COMMIT (1 << 11)
#define AUREON_AC97_ADDR (1 << 10)
#define AUREON_AC97_DATA_LOW (1 << 9)
#define AUREON_AC97_DATA_HIGH (1 << 8)
#define AUREON_AC97_DATA_MASK 0xFF
#endif /* __SOUND_AUREON_H */

771
sound/pci/ice1712/delta.c Normal file
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@@ -0,0 +1,771 @@
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for M-Audio Delta 1010, 44, 66, Dio2496, Audiophile
* Digigram VX442
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/cs8427.h>
#include <sound/asoundef.h>
#include "ice1712.h"
#include "delta.h"
#define SND_CS8403
#include <sound/cs8403.h>
/*
* CS8427 via SPI mode (for Audiophile), emulated I2C
*/
/* send 8 bits */
static void ap_cs8427_write_byte(ice1712_t *ice, unsigned char data, unsigned char tmp)
{
int idx;
for (idx = 7; idx >= 0; idx--) {
tmp &= ~(ICE1712_DELTA_AP_DOUT|ICE1712_DELTA_AP_CCLK);
if (data & (1 << idx))
tmp |= ICE1712_DELTA_AP_DOUT;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(5);
tmp |= ICE1712_DELTA_AP_CCLK;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(5);
}
}
/* read 8 bits */
static unsigned char ap_cs8427_read_byte(ice1712_t *ice, unsigned char tmp)
{
unsigned char data = 0;
int idx;
for (idx = 7; idx >= 0; idx--) {
tmp &= ~ICE1712_DELTA_AP_CCLK;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(5);
if (snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ICE1712_DELTA_AP_DIN)
data |= 1 << idx;
tmp |= ICE1712_DELTA_AP_CCLK;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(5);
}
return data;
}
/* assert chip select */
static unsigned char ap_cs8427_codec_select(ice1712_t *ice)
{
unsigned char tmp;
tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010LT:
tmp &= ~ICE1712_DELTA_1010LT_CS;
tmp |= ICE1712_DELTA_1010LT_CCLK | ICE1712_DELTA_1010LT_CS_CS8427;
break;
case ICE1712_SUBDEVICE_AUDIOPHILE:
case ICE1712_SUBDEVICE_DELTA410:
tmp |= ICE1712_DELTA_AP_CCLK | ICE1712_DELTA_AP_CS_CODEC;
tmp &= ~ICE1712_DELTA_AP_CS_DIGITAL;
break;
case ICE1712_SUBDEVICE_VX442:
tmp |= ICE1712_VX442_CCLK | ICE1712_VX442_CODEC_CHIP_A | ICE1712_VX442_CODEC_CHIP_B;
tmp &= ~ICE1712_VX442_CS_DIGITAL;
break;
}
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(5);
return tmp;
}
/* deassert chip select */
static void ap_cs8427_codec_deassert(ice1712_t *ice, unsigned char tmp)
{
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010LT:
tmp &= ~ICE1712_DELTA_1010LT_CS;
tmp |= ICE1712_DELTA_1010LT_CS_NONE;
break;
case ICE1712_SUBDEVICE_AUDIOPHILE:
case ICE1712_SUBDEVICE_DELTA410:
tmp |= ICE1712_DELTA_AP_CS_DIGITAL;
break;
case ICE1712_SUBDEVICE_VX442:
tmp |= ICE1712_VX442_CS_DIGITAL;
break;
}
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
}
/* sequential write */
static int ap_cs8427_sendbytes(snd_i2c_device_t *device, unsigned char *bytes, int count)
{
ice1712_t *ice = device->bus->private_data;
int res = count;
unsigned char tmp;
down(&ice->gpio_mutex);
tmp = ap_cs8427_codec_select(ice);
ap_cs8427_write_byte(ice, (device->addr << 1) | 0, tmp); /* address + write mode */
while (count-- > 0)
ap_cs8427_write_byte(ice, *bytes++, tmp);
ap_cs8427_codec_deassert(ice, tmp);
up(&ice->gpio_mutex);
return res;
}
/* sequential read */
static int ap_cs8427_readbytes(snd_i2c_device_t *device, unsigned char *bytes, int count)
{
ice1712_t *ice = device->bus->private_data;
int res = count;
unsigned char tmp;
down(&ice->gpio_mutex);
tmp = ap_cs8427_codec_select(ice);
ap_cs8427_write_byte(ice, (device->addr << 1) | 1, tmp); /* address + read mode */
while (count-- > 0)
*bytes++ = ap_cs8427_read_byte(ice, tmp);
ap_cs8427_codec_deassert(ice, tmp);
up(&ice->gpio_mutex);
return res;
}
static int ap_cs8427_probeaddr(snd_i2c_bus_t *bus, unsigned short addr)
{
if (addr == 0x10)
return 1;
return -ENOENT;
}
static snd_i2c_ops_t ap_cs8427_i2c_ops = {
.sendbytes = ap_cs8427_sendbytes,
.readbytes = ap_cs8427_readbytes,
.probeaddr = ap_cs8427_probeaddr,
};
/*
*/
static void snd_ice1712_delta_cs8403_spdif_write(ice1712_t *ice, unsigned char bits)
{
unsigned char tmp, mask1, mask2;
int idx;
/* send byte to transmitter */
mask1 = ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK;
mask2 = ICE1712_DELTA_SPDIF_OUT_STAT_DATA;
down(&ice->gpio_mutex);
tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
for (idx = 7; idx >= 0; idx--) {
tmp &= ~(mask1 | mask2);
if (bits & (1 << idx))
tmp |= mask2;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(100);
tmp |= mask1;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
udelay(100);
}
tmp &= ~mask1;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
up(&ice->gpio_mutex);
}
static void delta_spdif_default_get(ice1712_t *ice, snd_ctl_elem_value_t * ucontrol)
{
snd_cs8403_decode_spdif_bits(&ucontrol->value.iec958, ice->spdif.cs8403_bits);
}
static int delta_spdif_default_put(ice1712_t *ice, snd_ctl_elem_value_t * ucontrol)
{
unsigned int val;
int change;
val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958);
spin_lock_irq(&ice->reg_lock);
change = ice->spdif.cs8403_bits != val;
ice->spdif.cs8403_bits = val;
if (change && ice->playback_pro_substream == NULL) {
spin_unlock_irq(&ice->reg_lock);
snd_ice1712_delta_cs8403_spdif_write(ice, val);
} else {
spin_unlock_irq(&ice->reg_lock);
}
return change;
}
static void delta_spdif_stream_get(ice1712_t *ice, snd_ctl_elem_value_t * ucontrol)
{
snd_cs8403_decode_spdif_bits(&ucontrol->value.iec958, ice->spdif.cs8403_stream_bits);
}
static int delta_spdif_stream_put(ice1712_t *ice, snd_ctl_elem_value_t * ucontrol)
{
unsigned int val;
int change;
val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958);
spin_lock_irq(&ice->reg_lock);
change = ice->spdif.cs8403_stream_bits != val;
ice->spdif.cs8403_stream_bits = val;
if (change && ice->playback_pro_substream != NULL) {
spin_unlock_irq(&ice->reg_lock);
snd_ice1712_delta_cs8403_spdif_write(ice, val);
} else {
spin_unlock_irq(&ice->reg_lock);
}
return change;
}
/*
* AK4524 on Delta 44 and 66 to choose the chip mask
*/
static void delta_ak4524_lock(akm4xxx_t *ak, int chip)
{
struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
ice1712_t *ice = ak->private_data[0];
snd_ice1712_save_gpio_status(ice);
priv->cs_mask =
priv->cs_addr = chip == 0 ? ICE1712_DELTA_CODEC_CHIP_A :
ICE1712_DELTA_CODEC_CHIP_B;
}
/*
* AK4524 on Delta1010LT to choose the chip address
*/
static void delta1010lt_ak4524_lock(akm4xxx_t *ak, int chip)
{
struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
ice1712_t *ice = ak->private_data[0];
snd_ice1712_save_gpio_status(ice);
priv->cs_mask = ICE1712_DELTA_1010LT_CS;
priv->cs_addr = chip << 4;
}
/*
* AK4528 on VX442 to choose the chip mask
*/
static void vx442_ak4524_lock(akm4xxx_t *ak, int chip)
{
struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
ice1712_t *ice = ak->private_data[0];
snd_ice1712_save_gpio_status(ice);
priv->cs_mask =
priv->cs_addr = chip == 0 ? ICE1712_VX442_CODEC_CHIP_A :
ICE1712_VX442_CODEC_CHIP_B;
}
/*
* change the DFS bit according rate for Delta1010
*/
static void delta_1010_set_rate_val(ice1712_t *ice, unsigned int rate)
{
unsigned char tmp, tmp2;
if (rate == 0) /* no hint - S/PDIF input is master, simply return */
return;
down(&ice->gpio_mutex);
tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
tmp2 = tmp & ~ICE1712_DELTA_DFS;
if (rate > 48000)
tmp2 |= ICE1712_DELTA_DFS;
if (tmp != tmp2)
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp2);
up(&ice->gpio_mutex);
}
/*
* change the rate of AK4524 on Delta 44/66, AP, 1010LT
*/
static void delta_ak4524_set_rate_val(akm4xxx_t *ak, unsigned int rate)
{
unsigned char tmp, tmp2;
ice1712_t *ice = ak->private_data[0];
if (rate == 0) /* no hint - S/PDIF input is master, simply return */
return;
/* check before reset ak4524 to avoid unnecessary clicks */
down(&ice->gpio_mutex);
tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
up(&ice->gpio_mutex);
tmp2 = tmp & ~ICE1712_DELTA_DFS;
if (rate > 48000)
tmp2 |= ICE1712_DELTA_DFS;
if (tmp == tmp2)
return;
/* do it again */
snd_akm4xxx_reset(ak, 1);
down(&ice->gpio_mutex);
tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ~ICE1712_DELTA_DFS;
if (rate > 48000)
tmp |= ICE1712_DELTA_DFS;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
up(&ice->gpio_mutex);
snd_akm4xxx_reset(ak, 0);
}
/*
* change the rate of AK4524 on VX442
*/
static void vx442_ak4524_set_rate_val(akm4xxx_t *ak, unsigned int rate)
{
unsigned char val;
val = (rate > 48000) ? 0x65 : 0x60;
if (snd_akm4xxx_get(ak, 0, 0x02) != val ||
snd_akm4xxx_get(ak, 1, 0x02) != val) {
snd_akm4xxx_reset(ak, 1);
snd_akm4xxx_write(ak, 0, 0x02, val);
snd_akm4xxx_write(ak, 1, 0x02, val);
snd_akm4xxx_reset(ak, 0);
}
}
/*
* SPDIF ops for Delta 1010, Dio, 66
*/
/* open callback */
static void delta_open_spdif(ice1712_t *ice, snd_pcm_substream_t * substream)
{
ice->spdif.cs8403_stream_bits = ice->spdif.cs8403_bits;
}
/* set up */
static void delta_setup_spdif(ice1712_t *ice, int rate)
{
unsigned long flags;
unsigned int tmp;
int change;
spin_lock_irqsave(&ice->reg_lock, flags);
tmp = ice->spdif.cs8403_stream_bits;
if (tmp & 0x01) /* consumer */
tmp &= (tmp & 0x01) ? ~0x06 : ~0x18;
switch (rate) {
case 32000: tmp |= (tmp & 0x01) ? 0x04 : 0x00; break;
case 44100: tmp |= (tmp & 0x01) ? 0x00 : 0x10; break;
case 48000: tmp |= (tmp & 0x01) ? 0x02 : 0x08; break;
default: tmp |= (tmp & 0x01) ? 0x00 : 0x18; break;
}
change = ice->spdif.cs8403_stream_bits != tmp;
ice->spdif.cs8403_stream_bits = tmp;
spin_unlock_irqrestore(&ice->reg_lock, flags);
if (change)
snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &ice->spdif.stream_ctl->id);
snd_ice1712_delta_cs8403_spdif_write(ice, tmp);
}
/*
* initialize the chips on M-Audio cards
*/
static akm4xxx_t akm_audiophile __devinitdata = {
.type = SND_AK4528,
.num_adcs = 2,
.num_dacs = 2,
.ops = {
.set_rate_val = delta_ak4524_set_rate_val
}
};
static struct snd_ak4xxx_private akm_audiophile_priv __devinitdata = {
.caddr = 2,
.cif = 0,
.data_mask = ICE1712_DELTA_AP_DOUT,
.clk_mask = ICE1712_DELTA_AP_CCLK,
.cs_mask = ICE1712_DELTA_AP_CS_CODEC,
.cs_addr = ICE1712_DELTA_AP_CS_CODEC,
.cs_none = 0,
.add_flags = ICE1712_DELTA_AP_CS_DIGITAL,
.mask_flags = 0,
};
static akm4xxx_t akm_delta410 __devinitdata = {
.type = SND_AK4529,
.num_adcs = 2,
.num_dacs = 8,
.ops = {
.set_rate_val = delta_ak4524_set_rate_val
}
};
static struct snd_ak4xxx_private akm_delta410_priv __devinitdata = {
.caddr = 0,
.cif = 0,
.data_mask = ICE1712_DELTA_AP_DOUT,
.clk_mask = ICE1712_DELTA_AP_CCLK,
.cs_mask = ICE1712_DELTA_AP_CS_CODEC,
.cs_addr = ICE1712_DELTA_AP_CS_CODEC,
.cs_none = 0,
.add_flags = ICE1712_DELTA_AP_CS_DIGITAL,
.mask_flags = 0,
};
static akm4xxx_t akm_delta1010lt __devinitdata = {
.type = SND_AK4524,
.num_adcs = 8,
.num_dacs = 8,
.ops = {
.lock = delta1010lt_ak4524_lock,
.set_rate_val = delta_ak4524_set_rate_val
}
};
static struct snd_ak4xxx_private akm_delta1010lt_priv __devinitdata = {
.caddr = 2,
.cif = 0, /* the default level of the CIF pin from AK4524 */
.data_mask = ICE1712_DELTA_1010LT_DOUT,
.clk_mask = ICE1712_DELTA_1010LT_CCLK,
.cs_mask = 0,
.cs_addr = 0, /* set later */
.cs_none = ICE1712_DELTA_1010LT_CS_NONE,
.add_flags = 0,
.mask_flags = 0,
};
static akm4xxx_t akm_delta44 __devinitdata = {
.type = SND_AK4524,
.num_adcs = 4,
.num_dacs = 4,
.ops = {
.lock = delta_ak4524_lock,
.set_rate_val = delta_ak4524_set_rate_val
}
};
static struct snd_ak4xxx_private akm_delta44_priv __devinitdata = {
.caddr = 2,
.cif = 0, /* the default level of the CIF pin from AK4524 */
.data_mask = ICE1712_DELTA_CODEC_SERIAL_DATA,
.clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK,
.cs_mask = 0,
.cs_addr = 0, /* set later */
.cs_none = 0,
.add_flags = 0,
.mask_flags = 0,
};
static akm4xxx_t akm_vx442 __devinitdata = {
.type = SND_AK4524,
.num_adcs = 4,
.num_dacs = 4,
.ops = {
.lock = vx442_ak4524_lock,
.set_rate_val = vx442_ak4524_set_rate_val
}
};
static struct snd_ak4xxx_private akm_vx442_priv __devinitdata = {
.caddr = 2,
.cif = 0,
.data_mask = ICE1712_VX442_DOUT,
.clk_mask = ICE1712_VX442_CCLK,
.cs_mask = 0,
.cs_addr = 0, /* set later */
.cs_none = 0,
.add_flags = 0,
.mask_flags = 0,
};
static int __devinit snd_ice1712_delta_init(ice1712_t *ice)
{
int err;
akm4xxx_t *ak;
/* determine I2C, DACs and ADCs */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_AUDIOPHILE:
ice->num_total_dacs = 2;
ice->num_total_adcs = 2;
break;
case ICE1712_SUBDEVICE_DELTA410:
ice->num_total_dacs = 8;
ice->num_total_adcs = 2;
break;
case ICE1712_SUBDEVICE_DELTA44:
case ICE1712_SUBDEVICE_DELTA66:
ice->num_total_dacs = ice->omni ? 8 : 4;
ice->num_total_adcs = ice->omni ? 8 : 4;
break;
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTA1010LT:
case ICE1712_SUBDEVICE_MEDIASTATION:
ice->num_total_dacs = 8;
ice->num_total_adcs = 8;
break;
case ICE1712_SUBDEVICE_DELTADIO2496:
ice->num_total_dacs = 4; /* two AK4324 codecs */
break;
case ICE1712_SUBDEVICE_VX442:
ice->num_total_dacs = 4;
ice->num_total_adcs = 4;
break;
}
/* initialize spdif */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_AUDIOPHILE:
case ICE1712_SUBDEVICE_DELTA410:
case ICE1712_SUBDEVICE_DELTA1010LT:
case ICE1712_SUBDEVICE_VX442:
if ((err = snd_i2c_bus_create(ice->card, "ICE1712 GPIO 1", NULL, &ice->i2c)) < 0) {
snd_printk("unable to create I2C bus\n");
return err;
}
ice->i2c->private_data = ice;
ice->i2c->ops = &ap_cs8427_i2c_ops;
if ((err = snd_ice1712_init_cs8427(ice, CS8427_BASE_ADDR)) < 0)
return err;
break;
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_MEDIASTATION:
ice->gpio.set_pro_rate = delta_1010_set_rate_val;
break;
case ICE1712_SUBDEVICE_DELTADIO2496:
ice->gpio.set_pro_rate = delta_1010_set_rate_val;
/* fall thru */
case ICE1712_SUBDEVICE_DELTA66:
ice->spdif.ops.open = delta_open_spdif;
ice->spdif.ops.setup_rate = delta_setup_spdif;
ice->spdif.ops.default_get = delta_spdif_default_get;
ice->spdif.ops.default_put = delta_spdif_default_put;
ice->spdif.ops.stream_get = delta_spdif_stream_get;
ice->spdif.ops.stream_put = delta_spdif_stream_put;
/* Set spdif defaults */
snd_ice1712_delta_cs8403_spdif_write(ice, ice->spdif.cs8403_bits);
break;
}
/* no analog? */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTADIO2496:
case ICE1712_SUBDEVICE_MEDIASTATION:
return 0;
}
/* second stage of initialization, analog parts and others */
ak = ice->akm = kmalloc(sizeof(akm4xxx_t), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 1;
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_AUDIOPHILE:
err = snd_ice1712_akm4xxx_init(ak, &akm_audiophile, &akm_audiophile_priv, ice);
break;
case ICE1712_SUBDEVICE_DELTA410:
err = snd_ice1712_akm4xxx_init(ak, &akm_delta410, &akm_delta410_priv, ice);
break;
case ICE1712_SUBDEVICE_DELTA1010LT:
err = snd_ice1712_akm4xxx_init(ak, &akm_delta1010lt, &akm_delta1010lt_priv, ice);
break;
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_DELTA44:
err = snd_ice1712_akm4xxx_init(ak, &akm_delta44, &akm_delta44_priv, ice);
break;
case ICE1712_SUBDEVICE_VX442:
err = snd_ice1712_akm4xxx_init(ak, &akm_vx442, &akm_vx442_priv, ice);
break;
default:
snd_BUG();
return -EINVAL;
}
return err;
}
/*
* additional controls for M-Audio cards
*/
static snd_kcontrol_new_t snd_ice1712_delta1010_wordclock_select __devinitdata =
ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Word Clock Sync", 0, ICE1712_DELTA_WORD_CLOCK_SELECT, 1, 0);
static snd_kcontrol_new_t snd_ice1712_delta1010lt_wordclock_select __devinitdata =
ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Word Clock Sync", 0, ICE1712_DELTA_1010LT_WORDCLOCK, 1, 0);
static snd_kcontrol_new_t snd_ice1712_delta1010_wordclock_status __devinitdata =
ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Word Clock Status", 0, ICE1712_DELTA_WORD_CLOCK_STATUS, 1, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
static snd_kcontrol_new_t snd_ice1712_deltadio2496_spdif_in_select __devinitdata =
ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "IEC958 Input Optical", 0, ICE1712_DELTA_SPDIF_INPUT_SELECT, 0, 0);
static snd_kcontrol_new_t snd_ice1712_delta_spdif_in_status __devinitdata =
ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Delta IEC958 Input Status", 0, ICE1712_DELTA_SPDIF_IN_STAT, 1, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
static int __devinit snd_ice1712_delta_add_controls(ice1712_t *ice)
{
int err;
/* 1010 and dio specific controls */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_MEDIASTATION:
err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_select, ice));
if (err < 0)
return err;
err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_status, ice));
if (err < 0)
return err;
break;
case ICE1712_SUBDEVICE_DELTADIO2496:
err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_deltadio2496_spdif_in_select, ice));
if (err < 0)
return err;
break;
case ICE1712_SUBDEVICE_DELTA1010LT:
err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010lt_wordclock_select, ice));
if (err < 0)
return err;
break;
}
/* normal spdif controls */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTADIO2496:
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_MEDIASTATION:
err = snd_ice1712_spdif_build_controls(ice);
if (err < 0)
return err;
break;
}
/* spdif status in */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTADIO2496:
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_MEDIASTATION:
err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta_spdif_in_status, ice));
if (err < 0)
return err;
break;
}
/* ak4524 controls */
switch (ice->eeprom.subvendor) {
case ICE1712_SUBDEVICE_DELTA1010LT:
case ICE1712_SUBDEVICE_AUDIOPHILE:
case ICE1712_SUBDEVICE_DELTA410:
case ICE1712_SUBDEVICE_DELTA44:
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_VX442:
err = snd_ice1712_akm4xxx_build_controls(ice);
if (err < 0)
return err;
break;
}
return 0;
}
/* entry point */
struct snd_ice1712_card_info snd_ice1712_delta_cards[] __devinitdata = {
{
.subvendor = ICE1712_SUBDEVICE_DELTA1010,
.name = "M Audio Delta 1010",
.model = "delta1010",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
},
{
.subvendor = ICE1712_SUBDEVICE_DELTADIO2496,
.name = "M Audio Delta DiO 2496",
.model = "dio2496",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
.no_mpu401 = 1,
},
{
.subvendor = ICE1712_SUBDEVICE_DELTA66,
.name = "M Audio Delta 66",
.model = "delta66",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
.no_mpu401 = 1,
},
{
.subvendor = ICE1712_SUBDEVICE_DELTA44,
.name = "M Audio Delta 44",
.model = "delta44",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
.no_mpu401 = 1,
},
{
.subvendor = ICE1712_SUBDEVICE_AUDIOPHILE,
.name = "M Audio Audiophile 24/96",
.model = "audiophile",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
},
{
.subvendor = ICE1712_SUBDEVICE_DELTA410,
.name = "M Audio Delta 410",
.model = "delta410",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
},
{
.subvendor = ICE1712_SUBDEVICE_DELTA1010LT,
.name = "M Audio Delta 1010LT",
.model = "delta1010lt",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
},
{
.subvendor = ICE1712_SUBDEVICE_VX442,
.name = "Digigram VX442",
.model = "vx442",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
.no_mpu401 = 1,
},
{
.subvendor = ICE1712_SUBDEVICE_MEDIASTATION,
.name = "Lionstracs Mediastation",
.model = "mediastation",
.chip_init = snd_ice1712_delta_init,
.build_controls = snd_ice1712_delta_add_controls,
},
{ } /* terminator */
};

150
sound/pci/ice1712/delta.h Normal file
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#ifndef __SOUND_DELTA_H
#define __SOUND_DELTA_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for M-Audio Delta 1010, 44, 66, Dio2496, Audiophile
* Digigram VX442
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define DELTA_DEVICE_DESC \
"{MidiMan M Audio,Delta 1010},"\
"{MidiMan M Audio,Delta 1010LT},"\
"{MidiMan M Audio,Delta DiO 2496},"\
"{MidiMan M Audio,Delta 66},"\
"{MidiMan M Audio,Delta 44},"\
"{MidiMan M Audio,Audiophile 24/96},"\
"{Digigram,VX442},"\
"{Lionstracs,Mediastation},"
#define ICE1712_SUBDEVICE_DELTA1010 0x121430d6
#define ICE1712_SUBDEVICE_DELTADIO2496 0x121431d6
#define ICE1712_SUBDEVICE_DELTA66 0x121432d6
#define ICE1712_SUBDEVICE_DELTA44 0x121433d6
#define ICE1712_SUBDEVICE_AUDIOPHILE 0x121434d6
#define ICE1712_SUBDEVICE_DELTA410 0x121438d6
#define ICE1712_SUBDEVICE_DELTA1010LT 0x12143bd6
#define ICE1712_SUBDEVICE_VX442 0x12143cd6
#define ICE1712_SUBDEVICE_MEDIASTATION 0x694c0100
/* entry point */
extern struct snd_ice1712_card_info snd_ice1712_delta_cards[];
/*
* MidiMan M-Audio Delta GPIO definitions
*/
/* MidiMan M-Audio Delta shared pins */
#define ICE1712_DELTA_DFS 0x01 /* fast/slow sample rate mode */
/* (>48kHz must be 1) */
#define ICE1712_DELTA_SPDIF_IN_STAT 0x02
/* S/PDIF input status */
/* 0 = valid signal is present */
/* all except Delta44 */
/* look to CS8414 datasheet */
#define ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK 0x04
/* S/PDIF output status clock */
/* (writting on rising edge - 0->1) */
/* all except Delta44 */
/* look to CS8404A datasheet */
#define ICE1712_DELTA_SPDIF_OUT_STAT_DATA 0x08
/* S/PDIF output status data */
/* all except Delta44 */
/* look to CS8404A datasheet */
/* MidiMan M-Audio DeltaDiO */
/* 0x01 = DFS */
/* 0x02 = SPDIF_IN_STAT */
/* 0x04 = SPDIF_OUT_STAT_CLOCK */
/* 0x08 = SPDIF_OUT_STAT_DATA */
#define ICE1712_DELTA_SPDIF_INPUT_SELECT 0x10
/* coaxial (0), optical (1) */
/* S/PDIF input select*/
/* MidiMan M-Audio Delta1010 */
/* 0x01 = DFS */
/* 0x02 = SPDIF_IN_STAT */
/* 0x04 = SPDIF_OUT_STAT_CLOCK */
/* 0x08 = SPDIF_OUT_STAT_DATA */
#define ICE1712_DELTA_WORD_CLOCK_SELECT 0x10
/* 1 - clock are taken from S/PDIF input */
/* 0 - clock are taken from Word Clock input */
/* affected SPMCLKIN pin of Envy24 */
#define ICE1712_DELTA_WORD_CLOCK_STATUS 0x20
/* 0 = valid word clock signal is present */
/* MidiMan M-Audio Delta66 */
/* 0x01 = DFS */
/* 0x02 = SPDIF_IN_STAT */
/* 0x04 = SPDIF_OUT_STAT_CLOCK */
/* 0x08 = SPDIF_OUT_STAT_DATA */
#define ICE1712_DELTA_CODEC_SERIAL_DATA 0x10
/* AKM4524 serial data */
#define ICE1712_DELTA_CODEC_SERIAL_CLOCK 0x20
/* AKM4524 serial clock */
/* (writting on rising edge - 0->1 */
#define ICE1712_DELTA_CODEC_CHIP_A 0x40
#define ICE1712_DELTA_CODEC_CHIP_B 0x80
/* 1 - select chip A or B */
/* MidiMan M-Audio Delta44 */
/* 0x01 = DFS */
/* 0x10 = CODEC_SERIAL_DATA */
/* 0x20 = CODEC_SERIAL_CLOCK */
/* 0x40 = CODEC_CHIP_A */
/* 0x80 = CODEC_CHIP_B */
/* MidiMan M-Audio Audiophile/Delta410 definitions */
/* thanks to Kristof Pelckmans <Kristof.Pelckmans@antwerpen.be> for Delta410 info */
/* 0x01 = DFS */
#define ICE1712_DELTA_AP_CCLK 0x02 /* SPI clock */
/* (clocking on rising edge - 0->1) */
#define ICE1712_DELTA_AP_DIN 0x04 /* data input */
#define ICE1712_DELTA_AP_DOUT 0x08 /* data output */
#define ICE1712_DELTA_AP_CS_DIGITAL 0x10 /* CS8427 chip select */
/* low signal = select */
#define ICE1712_DELTA_AP_CS_CODEC 0x20 /* AK4528 (audiophile), AK4529 (Delta410) chip select */
/* low signal = select */
/* MidiMan M-Audio Delta1010LT definitions */
/* thanks to Anders Johansson <ajh@watri.uwa.edu.au> */
/* 0x01 = DFS */
#define ICE1712_DELTA_1010LT_CCLK 0x02 /* SPI clock (AK4524 + CS8427) */
#define ICE1712_DELTA_1010LT_DIN 0x04 /* data input (CS8427) */
#define ICE1712_DELTA_1010LT_DOUT 0x08 /* data output (AK4524 + CS8427) */
#define ICE1712_DELTA_1010LT_CS 0x70 /* mask for CS address */
#define ICE1712_DELTA_1010LT_CS_CHIP_A 0x00 /* AK4524 #0 */
#define ICE1712_DELTA_1010LT_CS_CHIP_B 0x10 /* AK4524 #1 */
#define ICE1712_DELTA_1010LT_CS_CHIP_C 0x20 /* AK4524 #2 */
#define ICE1712_DELTA_1010LT_CS_CHIP_D 0x30 /* AK4524 #3 */
#define ICE1712_DELTA_1010LT_CS_CS8427 0x40 /* CS8427 */
#define ICE1712_DELTA_1010LT_CS_NONE 0x50 /* nothing */
#define ICE1712_DELTA_1010LT_WORDCLOCK 0x80 /* sample clock source: 0 = Word Clock Input, 1 = S/PDIF Input ??? */
/* Digigram VX442 definitions */
#define ICE1712_VX442_CCLK 0x02 /* SPI clock */
#define ICE1712_VX442_DIN 0x04 /* data input */
#define ICE1712_VX442_DOUT 0x08 /* data output */
#define ICE1712_VX442_CS_DIGITAL 0x10 /* chip select, low = CS8427 */
#define ICE1712_VX442_CODEC_CHIP_A 0x20 /* select chip A */
#define ICE1712_VX442_CODEC_CHIP_B 0x40 /* select chip B */
#endif /* __SOUND_DELTA_H */

215
sound/pci/ice1712/envy24ht.h Normal file
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@@ -0,0 +1,215 @@
#ifndef __SOUND_VT1724_H
#define __SOUND_VT1724_H
/*
* ALSA driver for ICEnsemble VT1724 (Envy24)
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/control.h>
#include <sound/ac97_codec.h>
#include <sound/rawmidi.h>
#include <sound/i2c.h>
#include <sound/pcm.h>
#include "ice1712.h"
enum {
ICE_EEP2_SYSCONF = 0, /* 06 */
ICE_EEP2_ACLINK, /* 07 */
ICE_EEP2_I2S, /* 08 */
ICE_EEP2_SPDIF, /* 09 */
ICE_EEP2_GPIO_DIR, /* 0a */
ICE_EEP2_GPIO_DIR1, /* 0b */
ICE_EEP2_GPIO_DIR2, /* 0c */
ICE_EEP2_GPIO_MASK, /* 0d */
ICE_EEP2_GPIO_MASK1, /* 0e */
ICE_EEP2_GPIO_MASK2, /* 0f */
ICE_EEP2_GPIO_STATE, /* 10 */
ICE_EEP2_GPIO_STATE1, /* 11 */
ICE_EEP2_GPIO_STATE2 /* 12 */
};
/*
* Direct registers
*/
#define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
#define VT1724_REG_CONTROL 0x00 /* byte */
#define VT1724_RESET 0x80 /* reset whole chip */
#define VT1724_REG_IRQMASK 0x01 /* byte */
#define VT1724_IRQ_MPU_RX 0x80
#define VT1724_IRQ_MPU_TX 0x20
#define VT1724_IRQ_MTPCM 0x10
#define VT1724_REG_IRQSTAT 0x02 /* byte */
/* look to VT1724_IRQ_* */
#define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
#define VT1724_CFG_CLOCK 0xc0
#define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
#define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
#define VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */
#define VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */
#define VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
#define VT1724_REG_AC97_CFG 0x05 /* byte */
#define VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
#define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
#define VT1724_REG_I2S_FEATURES 0x06 /* byte */
#define VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
#define VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
#define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
#define VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */
#define VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */
#define VT1724_REG_SPDIF_CFG 0x07 /* byte */
#define VT1724_CFG_SPDIF_OUT_EN 0x80 /*Internal S/PDIF output is enabled*/
#define VT1724_CFG_SPDIF_OUT_INT 0x40 /*Internal S/PDIF output is implemented*/
#define VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */
#define VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
#define VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */
/*there is no consumer AC97 codec with the VT1724*/
//#define VT1724_REG_AC97_INDEX 0x08 /* byte */
//#define VT1724_REG_AC97_CMD 0x09 /* byte */
#define VT1724_REG_MPU_TXFIFO 0x0a /*byte ro. number of bytes in TX fifo*/
#define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/
//are these 2 the wrong way around? they don't seem to be used yet anyway
#define VT1724_REG_MPU_CTRL 0x0c /* byte */
#define VT1724_REG_MPU_DATA 0x0d /* byte */
#define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/
#define VT1724_MPU_RX_FIFO 0x20 //1=rx fifo watermark 0=tx fifo watermark
#define VT1724_MPU_FIFO_MASK 0x1f
#define VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */
#define VT1724_I2C_WRITE 0x01 /* write direction */
#define VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */
#define VT1724_REG_I2C_DATA 0x12 /* byte */
#define VT1724_REG_I2C_CTRL 0x13 /* byte */
#define VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */
#define VT1724_I2C_BUSY 0x01 /* busy bit */
#define VT1724_REG_GPIO_DATA 0x14 /* word */
#define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */
#define VT1724_REG_GPIO_DIRECTION 0x18 /* dword? (3 bytes) 0=input 1=output.
bit3 - during reset used for Eeprom power-on strapping
if TESTEN# pin active, bit 2 always input*/
#define VT1724_REG_POWERDOWN 0x1c
#define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
#define VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */
/*
* Professional multi-track direct control registers
*/
#define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
#define VT1724_MT_IRQ 0x00 /* byte - interrupt mask */
#define VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */
#define VT1724_MULTI_PDMA3 0x40 /* PDMA3 */
#define VT1724_MULTI_PDMA2 0x20 /* PDMA2 */
#define VT1724_MULTI_PDMA1 0x10 /* PDMA1 */
#define VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */
#define VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */
#define VT1724_MULTI_RDMA0 0x02 /* RMDA0 */
#define VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */
#define VT1724_MT_RATE 0x01 /* byte - sampling rate select */
#define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
#define VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
#define VT1724_MT_I2S_MCLK_128X 0x08
#define VT1724_MT_I2S_FORMAT_MASK 0x03
#define VT1724_MT_I2S_FORMAT_I2S 0x00
#define VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */
/* lool to VT1724_MULTI_* */
#define VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
#define VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
#define VT1724_AC97_COLD 0x80 /* cold reset */
#define VT1724_AC97_WARM 0x40 /* warm reset */
#define VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */
#define VT1724_AC97_READ 0x10 /* W: read, R: read in progress */
#define VT1724_AC97_READY 0x08 /* codec ready status bit */
#define VT1724_AC97_ID_MASK 0x03 /* codec id mask */
#define VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */
#define VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
#define VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */
#define VT1724_MT_DMA_CONTROL 0x18 /* byte - control */
#define VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */
#define VT1724_PDMA3_START 0x40 /* PDMA3 start */
#define VT1724_PDMA2_START 0x20 /* PDMA2 start */
#define VT1724_PDMA1_START 0x10 /* PDMA1 start */
#define VT1724_RDMA1_START 0x04 /* RDMA1 start */
#define VT1724_RDMA0_START 0x02 /* RMDA0 start */
#define VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */
#define VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */
#define VT1724_MT_DMA_FIFO_ERR 0x1a /*Global playback and record DMA FIFO Underrun/Overrun */
#define VT1724_PDMA4_UNDERRUN 0x80
#define VT1724_PDMA2_UNDERRUN 0x40
#define VT1724_PDMA3_UNDERRUN 0x20
#define VT1724_PDMA1_UNDERRUN 0x10
#define VT1724_RDMA1_UNDERRUN 0x04
#define VT1724_RDMA0_UNDERRUN 0x02
#define VT1724_PDMA0_UNDERRUN 0x01
#define VT1724_MT_DMA_PAUSE 0x1b /*Global playback and record DMA FIFO pause/resume */
#define VT1724_PDMA4_PAUSE 0x80
#define VT1724_PDMA3_PAUSE 0x40
#define VT1724_PDMA2_PAUSE 0x20
#define VT1724_PDMA1_PAUSE 0x10
#define VT1724_RDMA1_PAUSE 0x04
#define VT1724_RDMA0_PAUSE 0x02
#define VT1724_PDMA0_PAUSE 0x01
#define VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */
#define VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
#define VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */
#define VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */
#define VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */
#define VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */
#define VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */
#define VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */
#define VT1724_MT_SPDIF_CTRL 0x3c /* word */
#define VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */
#define VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */
/* concurrent stereo channels */
#define VT1724_MT_PDMA4_ADDR 0x40 /* dword */
#define VT1724_MT_PDMA4_SIZE 0x44 /* word */
#define VT1724_MT_PDMA4_COUNT 0x46 /* word */
#define VT1724_MT_PDMA3_ADDR 0x50 /* dword */
#define VT1724_MT_PDMA3_SIZE 0x54 /* word */
#define VT1724_MT_PDMA3_COUNT 0x56 /* word */
#define VT1724_MT_PDMA2_ADDR 0x60 /* dword */
#define VT1724_MT_PDMA2_SIZE 0x64 /* word */
#define VT1724_MT_PDMA2_COUNT 0x66 /* word */
#define VT1724_MT_PDMA1_ADDR 0x70 /* dword */
#define VT1724_MT_PDMA1_SIZE 0x74 /* word */
#define VT1724_MT_PDMA1_COUNT 0x76 /* word */
unsigned char snd_vt1724_read_i2c(ice1712_t *ice, unsigned char dev, unsigned char addr);
void snd_vt1724_write_i2c(ice1712_t *ice, unsigned char dev, unsigned char addr, unsigned char data);
#endif /* __SOUND_VT1724_H */

1036
sound/pci/ice1712/ews.c Normal file
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文件差異過大導致無法顯示 Load Diff

84
sound/pci/ice1712/ews.h Normal file
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#ifndef __SOUND_EWS_H
#define __SOUND_EWS_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for Terratec EWS88MT/D, EWX24/96, DMX 6Fire
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
* 2002 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define EWS_DEVICE_DESC \
"{TerraTec,EWX 24/96},"\
"{TerraTec,EWS 88MT},"\
"{TerraTec,EWS 88D},"\
"{TerraTec,DMX 6Fire},"\
"{TerraTec,Phase 88},"
#define ICE1712_SUBDEVICE_EWX2496 0x3b153011
#define ICE1712_SUBDEVICE_EWS88MT 0x3b151511
#define ICE1712_SUBDEVICE_EWS88MT_NEW 0x3b152511
#define ICE1712_SUBDEVICE_EWS88D 0x3b152b11
#define ICE1712_SUBDEVICE_DMX6FIRE 0x3b153811
#define ICE1712_SUBDEVICE_PHASE88 0x3b155111
/* entry point */
extern struct snd_ice1712_card_info snd_ice1712_ews_cards[];
/* TerraTec EWX 24/96 configuration definitions */
#define ICE1712_EWX2496_AK4524_CS 0x01 /* AK4524 chip select; low = active */
#define ICE1712_EWX2496_AIN_SEL 0x02 /* input sensitivity switch; high = louder */
#define ICE1712_EWX2496_AOUT_SEL 0x04 /* output sensitivity switch; high = louder */
#define ICE1712_EWX2496_RW 0x08 /* read/write switch for i2c; high = write */
#define ICE1712_EWX2496_SERIAL_DATA 0x10 /* i2c & ak4524 data */
#define ICE1712_EWX2496_SERIAL_CLOCK 0x20 /* i2c & ak4524 clock */
#define ICE1712_EWX2496_TX2 0x40 /* MIDI2 (not used) */
#define ICE1712_EWX2496_RX2 0x80 /* MIDI2 (not used) */
/* TerraTec EWS 88MT/D configuration definitions */
/* RW, SDA snd SCLK are identical with EWX24/96 */
#define ICE1712_EWS88_CS8414_RATE 0x07 /* CS8414 sample rate: gpio 0-2 */
#define ICE1712_EWS88_RW 0x08 /* read/write switch for i2c; high = write */
#define ICE1712_EWS88_SERIAL_DATA 0x10 /* i2c & ak4524 data */
#define ICE1712_EWS88_SERIAL_CLOCK 0x20 /* i2c & ak4524 clock */
#define ICE1712_EWS88_TX2 0x40 /* MIDI2 (only on 88D) */
#define ICE1712_EWS88_RX2 0x80 /* MIDI2 (only on 88D) */
/* i2c address */
#define ICE1712_EWS88MT_CS8404_ADDR (0x40>>1)
#define ICE1712_EWS88MT_INPUT_ADDR (0x46>>1)
#define ICE1712_EWS88MT_OUTPUT_ADDR (0x48>>1)
#define ICE1712_EWS88MT_OUTPUT_SENSE 0x40 /* mask */
#define ICE1712_EWS88D_PCF_ADDR (0x40>>1)
/* TerraTec DMX 6Fire configuration definitions */
#define ICE1712_6FIRE_AK4524_CS_MASK 0x07 /* AK4524 chip select #1-#3 */
#define ICE1712_6FIRE_RW 0x08 /* read/write switch for i2c; high = write */
#define ICE1712_6FIRE_SERIAL_DATA 0x10 /* i2c & ak4524 data */
#define ICE1712_6FIRE_SERIAL_CLOCK 0x20 /* i2c & ak4524 clock */
#define ICE1712_6FIRE_TX2 0x40 /* MIDI2 */
#define ICE1712_6FIRE_RX2 0x80 /* MIDI2 */
#define ICE1712_6FIRE_PCF9554_ADDR (0x40>>1)
#define ICE1712_6FIRE_CS8427_ADDR (0x22)
#endif /* __SOUND_EWS_H */

326
sound/pci/ice1712/hoontech.c Normal file
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/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for Hoontech STDSP24
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "hoontech.h"
static void __devinit snd_ice1712_stdsp24_gpio_write(ice1712_t *ice, unsigned char byte)
{
byte |= ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
byte &= ~ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
byte |= ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
}
static void __devinit snd_ice1712_stdsp24_darear(ice1712_t *ice, int activate)
{
down(&ice->gpio_mutex);
ICE1712_STDSP24_0_DAREAR(ice->spec.hoontech.boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[0]);
up(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_mute(ice1712_t *ice, int activate)
{
down(&ice->gpio_mutex);
ICE1712_STDSP24_3_MUTE(ice->spec.hoontech.boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[3]);
up(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_insel(ice1712_t *ice, int activate)
{
down(&ice->gpio_mutex);
ICE1712_STDSP24_3_INSEL(ice->spec.hoontech.boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[3]);
up(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_box_channel(ice1712_t *ice, int box, int chn, int activate)
{
down(&ice->gpio_mutex);
/* select box */
ICE1712_STDSP24_0_BOX(ice->spec.hoontech.boxbits, box);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[0]);
/* prepare for write */
if (chn == 3)
ICE1712_STDSP24_2_CHN4(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_2_MIDI1(ice->spec.hoontech.boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[3]);
ICE1712_STDSP24_1_CHN1(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN2(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN3(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_2_CHN4(ice->spec.hoontech.boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[1]);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
udelay(100);
if (chn == 3) {
ICE1712_STDSP24_2_CHN4(ice->spec.hoontech.boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
} else {
switch (chn) {
case 0: ICE1712_STDSP24_1_CHN1(ice->spec.hoontech.boxbits, 0); break;
case 1: ICE1712_STDSP24_1_CHN2(ice->spec.hoontech.boxbits, 0); break;
case 2: ICE1712_STDSP24_1_CHN3(ice->spec.hoontech.boxbits, 0); break;
}
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[1]);
}
udelay(100);
ICE1712_STDSP24_1_CHN1(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN2(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN3(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_2_CHN4(ice->spec.hoontech.boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[1]);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
udelay(100);
ICE1712_STDSP24_2_MIDI1(ice->spec.hoontech.boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
up(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_box_midi(ice1712_t *ice, int box, int master)
{
down(&ice->gpio_mutex);
/* select box */
ICE1712_STDSP24_0_BOX(ice->spec.hoontech.boxbits, box);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[0]);
ICE1712_STDSP24_2_MIDIIN(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_2_MIDI1(ice->spec.hoontech.boxbits, master);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[3]);
udelay(100);
ICE1712_STDSP24_2_MIDIIN(ice->spec.hoontech.boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
mdelay(10);
ICE1712_STDSP24_2_MIDIIN(ice->spec.hoontech.boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[2]);
up(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_midi2(ice1712_t *ice, int activate)
{
down(&ice->gpio_mutex);
ICE1712_STDSP24_3_MIDI2(ice->spec.hoontech.boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, ice->spec.hoontech.boxbits[3]);
up(&ice->gpio_mutex);
}
static int __devinit snd_ice1712_hoontech_init(ice1712_t *ice)
{
int box, chn;
ice->num_total_dacs = 8;
ice->num_total_adcs = 8;
ice->spec.hoontech.boxbits[0] =
ice->spec.hoontech.boxbits[1] =
ice->spec.hoontech.boxbits[2] =
ice->spec.hoontech.boxbits[3] = 0; /* should be already */
ICE1712_STDSP24_SET_ADDR(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_CLOCK(ice->spec.hoontech.boxbits, 0, 1);
ICE1712_STDSP24_0_BOX(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_0_DAREAR(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_SET_ADDR(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_CLOCK(ice->spec.hoontech.boxbits, 1, 1);
ICE1712_STDSP24_1_CHN1(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN2(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_1_CHN3(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_SET_ADDR(ice->spec.hoontech.boxbits, 2);
ICE1712_STDSP24_CLOCK(ice->spec.hoontech.boxbits, 2, 1);
ICE1712_STDSP24_2_CHN4(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_2_MIDIIN(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_2_MIDI1(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_SET_ADDR(ice->spec.hoontech.boxbits, 3);
ICE1712_STDSP24_CLOCK(ice->spec.hoontech.boxbits, 3, 1);
ICE1712_STDSP24_3_MIDI2(ice->spec.hoontech.boxbits, 0);
ICE1712_STDSP24_3_MUTE(ice->spec.hoontech.boxbits, 1);
ICE1712_STDSP24_3_INSEL(ice->spec.hoontech.boxbits, 0);
/* let's go - activate only functions in first box */
ice->spec.hoontech.config = 0;
/* ICE1712_STDSP24_MUTE |
ICE1712_STDSP24_INSEL |
ICE1712_STDSP24_DAREAR; */
ice->spec.hoontech.boxconfig[0] = ICE1712_STDSP24_BOX_CHN1 |
ICE1712_STDSP24_BOX_CHN2 |
ICE1712_STDSP24_BOX_CHN3 |
ICE1712_STDSP24_BOX_CHN4 |
ICE1712_STDSP24_BOX_MIDI1 |
ICE1712_STDSP24_BOX_MIDI2;
ice->spec.hoontech.boxconfig[1] =
ice->spec.hoontech.boxconfig[2] =
ice->spec.hoontech.boxconfig[3] = 0;
snd_ice1712_stdsp24_darear(ice, (ice->spec.hoontech.config & ICE1712_STDSP24_DAREAR) ? 1 : 0);
snd_ice1712_stdsp24_mute(ice, (ice->spec.hoontech.config & ICE1712_STDSP24_MUTE) ? 1 : 0);
snd_ice1712_stdsp24_insel(ice, (ice->spec.hoontech.config & ICE1712_STDSP24_INSEL) ? 1 : 0);
for (box = 0; box < 4; box++) {
for (chn = 0; chn < 4; chn++)
snd_ice1712_stdsp24_box_channel(ice, box, chn, (ice->spec.hoontech.boxconfig[box] & (1 << chn)) ? 1 : 0);
snd_ice1712_stdsp24_box_midi(ice, box,
(ice->spec.hoontech.boxconfig[box] & ICE1712_STDSP24_BOX_MIDI1) ? 1 : 0);
if (ice->spec.hoontech.boxconfig[box] & ICE1712_STDSP24_BOX_MIDI2)
snd_ice1712_stdsp24_midi2(ice, 1);
}
return 0;
}
/*
* AK4524 access
*/
/* start callback for STDSP24 with modified hardware */
static void stdsp24_ak4524_lock(akm4xxx_t *ak, int chip)
{
ice1712_t *ice = ak->private_data[0];
unsigned char tmp;
snd_ice1712_save_gpio_status(ice);
tmp = ICE1712_STDSP24_SERIAL_DATA |
ICE1712_STDSP24_SERIAL_CLOCK |
ICE1712_STDSP24_AK4524_CS;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
ice->gpio.direction | tmp);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~tmp);
}
static int __devinit snd_ice1712_value_init(ice1712_t *ice)
{
/* Hoontech STDSP24 with modified hardware */
static akm4xxx_t akm_stdsp24_mv __devinitdata = {
.num_adcs = 2,
.num_dacs = 2,
.type = SND_AK4524,
.ops = {
.lock = stdsp24_ak4524_lock
}
};
static struct snd_ak4xxx_private akm_stdsp24_mv_priv __devinitdata = {
.caddr = 2,
.cif = 1, /* CIF high */
.data_mask = ICE1712_STDSP24_SERIAL_DATA,
.clk_mask = ICE1712_STDSP24_SERIAL_CLOCK,
.cs_mask = ICE1712_STDSP24_AK4524_CS,
.cs_addr = ICE1712_STDSP24_AK4524_CS,
.cs_none = 0,
.add_flags = 0,
};
int err;
akm4xxx_t *ak;
/* set the analog DACs */
ice->num_total_dacs = 2;
/* set the analog ADCs */
ice->num_total_adcs = 2;
/* analog section */
ak = ice->akm = kmalloc(sizeof(akm4xxx_t), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 1;
err = snd_ice1712_akm4xxx_init(ak, &akm_stdsp24_mv, &akm_stdsp24_mv_priv, ice);
if (err < 0)
return err;
/* ak4524 controls */
err = snd_ice1712_akm4xxx_build_controls(ice);
if (err < 0)
return err;
return 0;
}
static int __devinit snd_ice1712_ez8_init(ice1712_t *ice)
{
ice->gpio.write_mask = ice->eeprom.gpiomask;
ice->gpio.direction = ice->eeprom.gpiodir;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ice->eeprom.gpiomask);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->eeprom.gpiodir);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, ice->eeprom.gpiostate);
return 0;
}
/* entry point */
struct snd_ice1712_card_info snd_ice1712_hoontech_cards[] __devinitdata = {
{
.subvendor = ICE1712_SUBDEVICE_STDSP24,
.name = "Hoontech SoundTrack Audio DSP24",
.model = "dsp24",
.chip_init = snd_ice1712_hoontech_init,
},
{
.subvendor = ICE1712_SUBDEVICE_STDSP24_VALUE, /* a dummy id */
.name = "Hoontech SoundTrack Audio DSP24 Value",
.model = "dsp24_value",
.chip_init = snd_ice1712_value_init,
},
{
.subvendor = ICE1712_SUBDEVICE_STDSP24_MEDIA7_1,
.name = "Hoontech STA DSP24 Media 7.1",
.model = "dsp24_71",
.chip_init = snd_ice1712_hoontech_init,
},
{
.subvendor = ICE1712_SUBDEVICE_EVENT_EZ8, /* a dummy id */
.name = "Event Electronics EZ8",
.model = "ez8",
.chip_init = snd_ice1712_ez8_init,
},
{ } /* terminator */
};

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sound/pci/ice1712/hoontech.h Normal file
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#ifndef __SOUND_HOONTECH_H
#define __SOUND_HOONTECH_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for Hoontech STDSP24
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define HOONTECH_DEVICE_DESC \
"{Hoontech,SoundTrack DSP 24}," \
"{Hoontech,SoundTrack DSP 24 Value}," \
"{Hoontech,SoundTrack DSP 24 Media 7.1}," \
"{Event Electronics,EZ8},"
#define ICE1712_SUBDEVICE_STDSP24 0x12141217 /* Hoontech SoundTrack Audio DSP 24 */
#define ICE1712_SUBDEVICE_STDSP24_VALUE 0x00010010 /* A dummy id for Hoontech SoundTrack Audio DSP 24 Value */
#define ICE1712_SUBDEVICE_STDSP24_MEDIA7_1 0x16141217 /* Hoontech ST Audio DSP24 Media 7.1 */
#define ICE1712_SUBDEVICE_EVENT_EZ8 0x00010001 /* A dummy id for EZ8 */
extern struct snd_ice1712_card_info snd_ice1712_hoontech_cards[];
/* Hoontech SoundTrack Audio DSP 24 GPIO definitions */
#define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3))
#define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2))
#define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1))
#define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1))
#define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2))
#define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1))
#define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1))
#define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2))
#define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1))
#define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1))
#define ICE1712_STDSP24_3_INSEL(r, x) r[3] = ((r[3] & ~4) | (((x)&1)<<2))
#define ICE1712_STDSP24_SET_ADDR(r, a) r[a&3] = ((r[a&3] & ~0x18) | (((a)&3)<<3))
#define ICE1712_STDSP24_CLOCK(r, a, c) r[a&3] = ((r[a&3] & ~0x20) | (((c)&1)<<5))
#define ICE1712_STDSP24_CLOCK_BIT (1<<5)
/* Hoontech SoundTrack Audio DSP 24 box configuration definitions */
#define ICE1712_STDSP24_DAREAR (1<<0)
#define ICE1712_STDSP24_MUTE (1<<1)
#define ICE1712_STDSP24_INSEL (1<<2)
#define ICE1712_STDSP24_BOX_CHN1 (1<<0) /* input channel 1 */
#define ICE1712_STDSP24_BOX_CHN2 (1<<1) /* input channel 2 */
#define ICE1712_STDSP24_BOX_CHN3 (1<<2) /* input channel 3 */
#define ICE1712_STDSP24_BOX_CHN4 (1<<3) /* input channel 4 */
#define ICE1712_STDSP24_BOX_MIDI1 (1<<8)
#define ICE1712_STDSP24_BOX_MIDI2 (1<<9)
/* Hoontech SoundTrack Audio DSP 24 Value definitions for modified hardware */
#define ICE1712_STDSP24_AK4524_CS 0x03 /* AK4524 chip select; low = active */
#define ICE1712_STDSP24_SERIAL_DATA 0x0c /* ak4524 data */
#define ICE1712_STDSP24_SERIAL_CLOCK 0x30 /* ak4524 clock */
#endif /* __SOUND_HOONTECH_H */

2760
sound/pci/ice1712/ice1712.c Normal file
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494
sound/pci/ice1712/ice1712.h Normal file
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#ifndef __SOUND_ICE1712_H
#define __SOUND_ICE1712_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/control.h>
#include <sound/ac97_codec.h>
#include <sound/rawmidi.h>
#include <sound/i2c.h>
#include <sound/ak4xxx-adda.h>
#include <sound/ak4114.h>
#include <sound/pcm.h>
/*
* Direct registers
*/
#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
#define ICE1712_REG_CONTROL 0x00 /* byte */
#define ICE1712_RESET 0x80 /* reset whole chip */
#define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
#define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
#define ICE1712_REG_IRQMASK 0x01 /* byte */
#define ICE1712_IRQ_MPU1 0x80
#define ICE1712_IRQ_TIMER 0x40
#define ICE1712_IRQ_MPU2 0x20
#define ICE1712_IRQ_PROPCM 0x10
#define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
#define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
#define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
#define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
#define ICE1712_REG_IRQSTAT 0x02 /* byte */
/* look to ICE1712_IRQ_* */
#define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
#define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
#define ICE1712_REG_NMI_STAT1 0x05 /* byte */
#define ICE1712_REG_NMI_DATA 0x06 /* byte */
#define ICE1712_REG_NMI_INDEX 0x07 /* byte */
#define ICE1712_REG_AC97_INDEX 0x08 /* byte */
#define ICE1712_REG_AC97_CMD 0x09 /* byte */
#define ICE1712_AC97_COLD 0x80 /* cold reset */
#define ICE1712_AC97_WARM 0x40 /* warm reset */
#define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
#define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
#define ICE1712_AC97_READY 0x08 /* codec ready status bit */
#define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
#define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
#define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
#define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
#define ICE1712_REG_MPU1_DATA 0x0d /* byte */
#define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
#define ICE1712_I2C_WRITE 0x01 /* write direction */
#define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
#define ICE1712_REG_I2C_DATA 0x12 /* byte */
#define ICE1712_REG_I2C_CTRL 0x13 /* byte */
#define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
#define ICE1712_I2C_BUSY 0x01 /* busy bit */
#define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
#define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
#define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
#define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
#define ICE1712_REG_MPU2_DATA 0x1d /* byte */
#define ICE1712_REG_TIMER 0x1e /* word */
/*
* Indirect registers
*/
#define ICE1712_IREG_PBK_COUNT_LO 0x00
#define ICE1712_IREG_PBK_COUNT_HI 0x01
#define ICE1712_IREG_PBK_CTRL 0x02
#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
#define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
#define ICE1712_IREG_PBK_RATE_LO 0x06
#define ICE1712_IREG_PBK_RATE_MID 0x07
#define ICE1712_IREG_PBK_RATE_HI 0x08
#define ICE1712_IREG_CAP_COUNT_LO 0x10
#define ICE1712_IREG_CAP_COUNT_HI 0x11
#define ICE1712_IREG_CAP_CTRL 0x12
#define ICE1712_IREG_GPIO_DATA 0x20
#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
#define ICE1712_IREG_GPIO_DIRECTION 0x22
#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
#define ICE1712_IREG_PRO_POWERDOWN 0x31
/*
* Consumer section direct DMA registers
*/
#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
#define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
#define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
#define ICE1712_DS_DATA 0x04 /* dword - channel data */
#define ICE1712_DS_INDEX 0x08 /* dword - channel index */
/*
* Consumer section channel registers
*/
#define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
#define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
#define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
#define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
#define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
#define ICE1712_BUFFER1 0x80 /* buffer1 is active */
#define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
#define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
#define ICE1712_FLUSH 0x10 /* flush FIFO */
#define ICE1712_STEREO 0x08 /* stereo */
#define ICE1712_16BIT 0x04 /* 16-bit data */
#define ICE1712_PAUSE 0x02 /* pause */
#define ICE1712_START 0x01 /* start */
#define ICE1712_DSC_RATE 0x05 /* dword - rate */
#define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
/*
* Professional multi-track direct control registers
*/
#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
#define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
#define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
#define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
#define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
#define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
#define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
#define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
#define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
#define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
#define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
/* look to ICE1712_AC97_* */
#define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
#define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
#define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
#define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
#define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
#define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
#define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
#define ICE1712_PLAYBACK_START 0x01 /* playback start */
#define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
#define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
#define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
#define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
#define ICE1712_CAPTURE_START 0x01 /* capture start */
#define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
#define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
#define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
#define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
#define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
#define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
#define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
#define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
/*
* Codec configuration bits
*/
/* PCI[60] System Configuration */
#define ICE1712_CFG_CLOCK 0xc0
#define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
#define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
#define ICE1712_CFG_EXT 0x80 /* external clock */
#define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
#define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
#define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
#define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
/* PCI[61] AC-Link Configuration */
#define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
#define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
/* PCI[62] I2S Features */
#define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
#define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
#define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
#define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
/* PCI[63] S/PDIF Configuration */
#define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
#define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
#define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
/*
* DMA mode values
* identical with DMA_XXX on i386 architecture.
*/
#define ICE1712_DMA_MODE_WRITE 0x48
#define ICE1712_DMA_AUTOINIT 0x10
/*
*
*/
typedef struct _snd_ice1712 ice1712_t;
typedef struct {
unsigned int subvendor; /* PCI[2c-2f] */
unsigned char size; /* size of EEPROM image in bytes */
unsigned char version; /* must be 1 (or 2 for vt1724) */
unsigned char data[32];
unsigned int gpiomask;
unsigned int gpiostate;
unsigned int gpiodir;
} ice1712_eeprom_t;
enum {
ICE_EEP1_CODEC = 0, /* 06 */
ICE_EEP1_ACLINK, /* 07 */
ICE_EEP1_I2SID, /* 08 */
ICE_EEP1_SPDIF, /* 09 */
ICE_EEP1_GPIO_MASK, /* 0a */
ICE_EEP1_GPIO_STATE, /* 0b */
ICE_EEP1_GPIO_DIR, /* 0c */
ICE_EEP1_AC97_MAIN_LO, /* 0d */
ICE_EEP1_AC97_MAIN_HI, /* 0e */
ICE_EEP1_AC97_PCM_LO, /* 0f */
ICE_EEP1_AC97_PCM_HI, /* 10 */
ICE_EEP1_AC97_REC_LO, /* 11 */
ICE_EEP1_AC97_REC_HI, /* 12 */
ICE_EEP1_AC97_RECSRC, /* 13 */
ICE_EEP1_DAC_ID, /* 14 */
ICE_EEP1_DAC_ID1,
ICE_EEP1_DAC_ID2,
ICE_EEP1_DAC_ID3,
ICE_EEP1_ADC_ID, /* 18 */
ICE_EEP1_ADC_ID1,
ICE_EEP1_ADC_ID2,
ICE_EEP1_ADC_ID3
};
#define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
struct snd_ak4xxx_private {
unsigned int cif: 1; /* CIF mode */
unsigned char caddr; /* C0 and C1 bits */
unsigned int data_mask; /* DATA gpio bit */
unsigned int clk_mask; /* CLK gpio bit */
unsigned int cs_mask; /* bit mask for select/deselect address */
unsigned int cs_addr; /* bits to select address */
unsigned int cs_none; /* bits to deselect address */
unsigned int add_flags; /* additional bits at init */
unsigned int mask_flags; /* total mask bits */
struct snd_akm4xxx_ops {
void (*set_rate_val)(akm4xxx_t *ak, unsigned int rate);
} ops;
};
struct snd_ice1712_spdif {
unsigned char cs8403_bits;
unsigned char cs8403_stream_bits;
snd_kcontrol_t *stream_ctl;
struct snd_ice1712_spdif_ops {
void (*open)(ice1712_t *, snd_pcm_substream_t *);
void (*setup_rate)(ice1712_t *, int rate);
void (*close)(ice1712_t *, snd_pcm_substream_t *);
void (*default_get)(ice1712_t *, snd_ctl_elem_value_t * ucontrol);
int (*default_put)(ice1712_t *, snd_ctl_elem_value_t * ucontrol);
void (*stream_get)(ice1712_t *, snd_ctl_elem_value_t * ucontrol);
int (*stream_put)(ice1712_t *, snd_ctl_elem_value_t * ucontrol);
} ops;
};
struct _snd_ice1712 {
unsigned long conp_dma_size;
unsigned long conc_dma_size;
unsigned long prop_dma_size;
unsigned long proc_dma_size;
int irq;
unsigned long port;
unsigned long ddma_port;
unsigned long dmapath_port;
unsigned long profi_port;
struct pci_dev *pci;
snd_card_t *card;
snd_pcm_t *pcm;
snd_pcm_t *pcm_ds;
snd_pcm_t *pcm_pro;
snd_pcm_substream_t *playback_con_substream;
snd_pcm_substream_t *playback_con_substream_ds[6];
snd_pcm_substream_t *capture_con_substream;
snd_pcm_substream_t *playback_pro_substream;
snd_pcm_substream_t *capture_pro_substream;
unsigned int playback_pro_size;
unsigned int capture_pro_size;
unsigned int playback_con_virt_addr[6];
unsigned int playback_con_active_buf[6];
unsigned int capture_con_virt_addr;
unsigned int ac97_ext_id;
ac97_t *ac97;
snd_rawmidi_t *rmidi[2];
spinlock_t reg_lock;
snd_info_entry_t *proc_entry;
ice1712_eeprom_t eeprom;
unsigned int pro_volumes[20];
unsigned int omni: 1; /* Delta Omni I/O */
unsigned int vt1724: 1;
unsigned int vt1720: 1;
unsigned int has_spdif: 1; /* VT1720/4 - has SPDIF I/O */
unsigned int force_pdma4: 1; /* VT1720/4 - PDMA4 as non-spdif */
unsigned int force_rdma1: 1; /* VT1720/4 - RDMA1 as non-spdif */
unsigned int num_total_dacs; /* total DACs */
unsigned int num_total_adcs; /* total ADCs */
unsigned int cur_rate; /* current rate */
struct semaphore open_mutex;
snd_pcm_substream_t *pcm_reserved[4];
snd_pcm_hw_constraint_list_t *hw_rates; /* card-specific rate constraints */
unsigned int akm_codecs;
akm4xxx_t *akm;
struct snd_ice1712_spdif spdif;
struct semaphore i2c_mutex; /* I2C mutex for ICE1724 registers */
snd_i2c_bus_t *i2c; /* I2C bus */
snd_i2c_device_t *cs8427; /* CS8427 I2C device */
unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */
struct ice1712_gpio {
unsigned int direction; /* current direction bits */
unsigned int write_mask; /* current mask bits */
unsigned int saved[2]; /* for ewx_i2c */
/* operators */
void (*set_mask)(ice1712_t *ice, unsigned int data);
void (*set_dir)(ice1712_t *ice, unsigned int data);
void (*set_data)(ice1712_t *ice, unsigned int data);
unsigned int (*get_data)(ice1712_t *ice);
/* misc operators - move to another place? */
void (*set_pro_rate)(ice1712_t *ice, unsigned int rate);
void (*i2s_mclk_changed)(ice1712_t *ice);
} gpio;
struct semaphore gpio_mutex;
/* other board-specific data */
union {
/* additional i2c devices for EWS boards */
snd_i2c_device_t *i2cdevs[3];
/* AC97 register cache for Aureon */
struct aureon_spec {
unsigned short stac9744[64];
unsigned int cs8415_mux;
unsigned short master[2];
unsigned short vol[8];
} aureon;
/* Hoontech-specific setting */
struct hoontech_spec {
unsigned char boxbits[4];
unsigned int config;
unsigned short boxconfig[4];
} hoontech;
struct {
ak4114_t *ak4114;
unsigned int analog: 1;
} juli;
} spec;
};
/*
* gpio access functions
*/
static inline void snd_ice1712_gpio_set_dir(ice1712_t *ice, unsigned int bits)
{
ice->gpio.set_dir(ice, bits);
}
static inline void snd_ice1712_gpio_set_mask(ice1712_t *ice, unsigned int bits)
{
ice->gpio.set_mask(ice, bits);
}
static inline void snd_ice1712_gpio_write(ice1712_t *ice, unsigned int val)
{
ice->gpio.set_data(ice, val);
}
static inline unsigned int snd_ice1712_gpio_read(ice1712_t *ice)
{
return ice->gpio.get_data(ice);
}
/*
* save and restore gpio status
* The access to gpio will be protected by mutex, so don't forget to
* restore!
*/
static inline void snd_ice1712_save_gpio_status(ice1712_t *ice)
{
down(&ice->gpio_mutex);
ice->gpio.saved[0] = ice->gpio.direction;
ice->gpio.saved[1] = ice->gpio.write_mask;
}
static inline void snd_ice1712_restore_gpio_status(ice1712_t *ice)
{
ice->gpio.set_dir(ice, ice->gpio.saved[0]);
ice->gpio.set_mask(ice, ice->gpio.saved[1]);
ice->gpio.direction = ice->gpio.saved[0];
ice->gpio.write_mask = ice->gpio.saved[1];
up(&ice->gpio_mutex);
}
/* for bit controls */
#define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
{ .iface = xiface, .name = xname, .access = xaccess, .info = snd_ice1712_gpio_info, \
.get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
.private_value = mask | (invert << 24) }
int snd_ice1712_gpio_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
int snd_ice1712_gpio_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
int snd_ice1712_gpio_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
/*
* set gpio direction, write mask and data
*/
static inline void snd_ice1712_gpio_write_bits(ice1712_t *ice, unsigned int mask, unsigned int bits)
{
ice->gpio.direction |= mask;
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ~mask);
snd_ice1712_gpio_write(ice, mask & bits);
}
int snd_ice1712_spdif_build_controls(ice1712_t *ice);
int snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *template, const struct snd_ak4xxx_private *priv, ice1712_t *ice);
void snd_ice1712_akm4xxx_free(ice1712_t *ice);
int snd_ice1712_akm4xxx_build_controls(ice1712_t *ice);
int snd_ice1712_init_cs8427(ice1712_t *ice, int addr);
static inline void snd_ice1712_write(ice1712_t * ice, u8 addr, u8 data)
{
outb(addr, ICEREG(ice, INDEX));
outb(data, ICEREG(ice, DATA));
}
static inline u8 snd_ice1712_read(ice1712_t * ice, u8 addr)
{
outb(addr, ICEREG(ice, INDEX));
return inb(ICEREG(ice, DATA));
}
/*
* entry pointer
*/
struct snd_ice1712_card_info {
unsigned int subvendor;
char *name;
char *model;
char *driver;
int (*chip_init)(ice1712_t *);
int (*build_controls)(ice1712_t *);
unsigned int no_mpu401: 1;
unsigned int eeprom_size;
unsigned char *eeprom_data;
};
#endif /* __SOUND_ICE1712_H */

2340
sound/pci/ice1712/ice1724.c Normal file
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文件差異過大導致無法顯示 Load Diff

230
sound/pci/ice1712/juli.c Normal file
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/*
* ALSA driver for ICEnsemble VT1724 (Envy24HT)
*
* Lowlevel functions for ESI Juli@ cards
*
* Copyright (c) 2004 Jaroslav Kysela <perex@suse.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "envy24ht.h"
#include "juli.h"
/*
* chip addresses on I2C bus
*/
#define AK4114_ADDR 0x20 /* S/PDIF receiver */
#define AK4358_ADDR 0x22 /* DAC */
/*
* GPIO pins
*/
#define GPIO_FREQ_MASK (3<<0)
#define GPIO_FREQ_32KHZ (0<<0)
#define GPIO_FREQ_44KHZ (1<<0)
#define GPIO_FREQ_48KHZ (2<<0)
#define GPIO_MULTI_MASK (3<<2)
#define GPIO_MULTI_4X (0<<2)
#define GPIO_MULTI_2X (1<<2)
#define GPIO_MULTI_1X (2<<2) /* also external */
#define GPIO_MULTI_HALF (3<<2)
#define GPIO_INTERNAL_CLOCK (1<<4)
#define GPIO_ANALOG_PRESENT (1<<5) /* RO only: 0 = present */
#define GPIO_RXMCLK_SEL (1<<7) /* must be 0 */
#define GPIO_AK5385A_CKS0 (1<<8)
#define GPIO_AK5385A_DFS0 (1<<9) /* swapped with DFS1 according doc? */
#define GPIO_AK5385A_DFS1 (1<<10)
#define GPIO_DIGOUT_MONITOR (1<<11) /* 1 = active */
#define GPIO_DIGIN_MONITOR (1<<12) /* 1 = active */
#define GPIO_ANAIN_MONITOR (1<<13) /* 1 = active */
#define GPIO_AK5385A_MCLK (1<<14) /* must be 0 */
#define GPIO_MUTE_CONTROL (1<<15) /* 0 = off, 1 = on */
static void juli_ak4114_write(void *private_data, unsigned char reg, unsigned char val)
{
snd_vt1724_write_i2c((ice1712_t *)private_data, AK4114_ADDR, reg, val);
}
static unsigned char juli_ak4114_read(void *private_data, unsigned char reg)
{
return snd_vt1724_read_i2c((ice1712_t *)private_data, AK4114_ADDR, reg);
}
/*
* AK4358 section
*/
static void juli_akm_lock(akm4xxx_t *ak, int chip)
{
}
static void juli_akm_unlock(akm4xxx_t *ak, int chip)
{
}
static void juli_akm_write(akm4xxx_t *ak, int chip,
unsigned char addr, unsigned char data)
{
ice1712_t *ice = ak->private_data[0];
snd_assert(chip == 0, return);
snd_vt1724_write_i2c(ice, AK4358_ADDR, addr, data);
}
/*
* change the rate of envy24HT, AK4358
*/
static void juli_akm_set_rate_val(akm4xxx_t *ak, unsigned int rate)
{
unsigned char old, tmp, dfs;
if (rate == 0) /* no hint - S/PDIF input is master, simply return */
return;
/* adjust DFS on codecs */
if (rate > 96000)
dfs = 2;
else if (rate > 48000)
dfs = 1;
else
dfs = 0;
tmp = snd_akm4xxx_get(ak, 0, 2);
old = (tmp >> 4) & 0x03;
if (old == dfs)
return;
/* reset DFS */
snd_akm4xxx_reset(ak, 1);
tmp = snd_akm4xxx_get(ak, 0, 2);
tmp &= ~(0x03 << 4);
tmp |= dfs << 4;
snd_akm4xxx_set(ak, 0, 2, tmp);
snd_akm4xxx_reset(ak, 0);
}
static akm4xxx_t akm_juli_dac __devinitdata = {
.type = SND_AK4358,
.num_dacs = 2,
.ops = {
.lock = juli_akm_lock,
.unlock = juli_akm_unlock,
.write = juli_akm_write,
.set_rate_val = juli_akm_set_rate_val
}
};
static int __devinit juli_add_controls(ice1712_t *ice)
{
return snd_ice1712_akm4xxx_build_controls(ice);
}
/*
* initialize the chip
*/
static int __devinit juli_init(ice1712_t *ice)
{
static unsigned char ak4114_init_vals[] = {
/* AK4117_REG_PWRDN */ AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,
/* AK4114_REQ_FORMAT */ AK4114_DIF_I24I2S,
/* AK4114_REG_IO0 */ AK4114_TX1E,
/* AK4114_REG_IO1 */ AK4114_EFH_1024 | AK4114_DIT | AK4114_IPS(1),
/* AK4114_REG_INT0_MASK */ 0,
/* AK4114_REG_INT1_MASK */ 0
};
static unsigned char ak4114_init_txcsb[] = {
0x41, 0x02, 0x2c, 0x00, 0x00
};
int err;
akm4xxx_t *ak;
#if 0
for (err = 0; err < 0x20; err++)
juli_ak4114_read(ice, err);
juli_ak4114_write(ice, 0, 0x0f);
juli_ak4114_read(ice, 0);
juli_ak4114_read(ice, 1);
#endif
err = snd_ak4114_create(ice->card,
juli_ak4114_read,
juli_ak4114_write,
ak4114_init_vals, ak4114_init_txcsb,
ice, &ice->spec.juli.ak4114);
if (err < 0)
return err;
ice->spec.juli.analog = ice->gpio.get_data(ice) & GPIO_ANALOG_PRESENT;
if (ice->spec.juli.analog) {
printk(KERN_INFO "juli@: analog I/O detected\n");
ice->num_total_dacs = 2;
ice->num_total_adcs = 2;
ak = ice->akm = kcalloc(1, sizeof(akm4xxx_t), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 1;
if ((err = snd_ice1712_akm4xxx_init(ak, &akm_juli_dac, NULL, ice)) < 0)
return err;
}
return 0;
}
/*
* Juli@ boards don't provide the EEPROM data except for the vendor IDs.
* hence the driver needs to sets up it properly.
*/
static unsigned char juli_eeprom[] __devinitdata = {
0x20, /* SYSCONF: clock 512, mpu401, 1xADC, 1xDACs */
0x80, /* ACLINK: I2S */
0xf8, /* I2S: vol, 96k, 24bit, 192k */
0xc3, /* SPDIF: out-en, out-int, spdif-in */
0x9f, /* GPIO_DIR */
0xff, /* GPIO_DIR1 */
0x7f, /* GPIO_DIR2 */
0x9f, /* GPIO_MASK */
0xff, /* GPIO_MASK1 */
0x7f, /* GPIO_MASK2 */
0x16, /* GPIO_STATE: internal clock, multiple 1x, 48kHz */
0x80, /* GPIO_STATE1: mute */
0x00, /* GPIO_STATE2 */
};
/* entry point */
struct snd_ice1712_card_info snd_vt1724_juli_cards[] __devinitdata = {
{
.subvendor = VT1724_SUBDEVICE_JULI,
.name = "ESI Juli@",
.model = "juli",
.chip_init = juli_init,
.build_controls = juli_add_controls,
.eeprom_size = sizeof(juli_eeprom),
.eeprom_data = juli_eeprom,
},
{ } /* terminator */
};

10
sound/pci/ice1712/juli.h Normal file
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@@ -0,0 +1,10 @@
#ifndef __SOUND_JULI_H
#define __SOUND_JULI_H
#define JULI_DEVICE_DESC "{ESI,Juli@},"
#define VT1724_SUBDEVICE_JULI 0x31305345 /* Juli@ */
extern struct snd_ice1712_card_info snd_vt1724_juli_cards[];
#endif /* __SOUND_JULI_H */

138
sound/pci/ice1712/phase.c Normal file
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@@ -0,0 +1,138 @@
/*
* ALSA driver for ICEnsemble ICE1724 (Envy24)
*
* Lowlevel functions for Terratec PHASE 22
*
* Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/* PHASE 22 overview:
* Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
* Analog chip: AK4524 (partially via Philip's 74HCT125)
* Digital receiver: CS8414-CS (not supported in this release)
*
* Envy connects to AK4524
* - CS directly from GPIO 10
* - CCLK via 74HCT125's gate #4 from GPIO 4
* - CDTI via 74HCT125's gate #2 from GPIO 5
* CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "envy24ht.h"
#include "phase.h"
static akm4xxx_t akm_phase22 __devinitdata = {
.type = SND_AK4524,
.num_dacs = 2,
.num_adcs = 2,
};
static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
.caddr = 2,
.cif = 1,
.data_mask = 1 << 4,
.clk_mask = 1 << 5,
.cs_mask = 1 << 10,
.cs_addr = 1 << 10,
.cs_none = 0,
.add_flags = 1 << 3,
.mask_flags = 0,
};
static int __devinit phase22_init(ice1712_t *ice)
{
akm4xxx_t *ak;
int err;
// Configure DAC/ADC description for generic part of ice1724
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_PHASE22:
ice->num_total_dacs = 2;
ice->num_total_adcs = 2;
ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
break;
default:
snd_BUG();
return -EINVAL;
}
// Initialize analog chips
ak = ice->akm = kcalloc(1, sizeof(akm4xxx_t), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 1;
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_PHASE22:
if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
return err;
break;
}
return 0;
}
static int __devinit phase22_add_controls(ice1712_t *ice)
{
int err = 0;
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_PHASE22:
err = snd_ice1712_akm4xxx_build_controls(ice);
if (err < 0)
return err;
}
return 0;
}
static unsigned char phase22_eeprom[] __devinitdata = {
0x00, /* SYSCONF: 1xADC, 1xDACs */
0x80, /* ACLINK: I2S */
0xf8, /* I2S: vol, 96k, 24bit*/
0xc3, /* SPDIF: out-en, out-int, spdif-in */
0xFF, /* GPIO_DIR */
0xFF, /* GPIO_DIR1 */
0xFF, /* GPIO_DIR2 */
0x00, /* GPIO_MASK */
0x00, /* GPIO_MASK1 */
0x00, /* GPIO_MASK2 */
0x00, /* GPIO_STATE: */
0x00, /* GPIO_STATE1: */
0x00, /* GPIO_STATE2 */
};
struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
{
.subvendor = VT1724_SUBDEVICE_PHASE22,
.name = "Terratec PHASE 22",
.model = "phase22",
.chip_init = phase22_init,
.build_controls = phase22_add_controls,
.eeprom_size = sizeof(phase22_eeprom),
.eeprom_data = phase22_eeprom,
},
{ } /* terminator */
};

34
sound/pci/ice1712/phase.h Normal file
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@@ -0,0 +1,34 @@
#ifndef __SOUND_PHASE_H
#define __SOUND_PHASE_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for Terratec PHASE 22
*
* Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define PHASE_DEVICE_DESC "{Terratec,Phase 22},"
#define VT1724_SUBDEVICE_PHASE22 0x3b155011
/* entry point */
extern struct snd_ice1712_card_info snd_vt1724_phase_cards[];
#endif /* __SOUND_PHASE */

849
sound/pci/ice1712/pontis.c Normal file
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@@ -0,0 +1,849 @@
/*
* ALSA driver for ICEnsemble VT1724 (Envy24HT)
*
* Lowlevel functions for Pontis MS300
*
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/info.h>
#include "ice1712.h"
#include "envy24ht.h"
#include "pontis.h"
/* I2C addresses */
#define WM_DEV 0x34
#define CS_DEV 0x20
/* WM8776 registers */
#define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
#define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
#define WM_HP_MASTER 0x02 /* headphone master (both channels), override LLR */
#define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
#define WM_DAC_ATTEN_R 0x04
#define WM_DAC_MASTER 0x05
#define WM_PHASE_SWAP 0x06 /* DAC phase swap */
#define WM_DAC_CTRL1 0x07
#define WM_DAC_MUTE 0x08
#define WM_DAC_CTRL2 0x09
#define WM_DAC_INT 0x0a
#define WM_ADC_INT 0x0b
#define WM_MASTER_CTRL 0x0c
#define WM_POWERDOWN 0x0d
#define WM_ADC_ATTEN_L 0x0e
#define WM_ADC_ATTEN_R 0x0f
#define WM_ALC_CTRL1 0x10
#define WM_ALC_CTRL2 0x11
#define WM_ALC_CTRL3 0x12
#define WM_NOISE_GATE 0x13
#define WM_LIMITER 0x14
#define WM_ADC_MUX 0x15
#define WM_OUT_MUX 0x16
#define WM_RESET 0x17
/*
* GPIO
*/
#define PONTIS_CS_CS (1<<4) /* CS */
#define PONTIS_CS_CLK (1<<5) /* CLK */
#define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
#define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
/*
* get the current register value of WM codec
*/
static unsigned short wm_get(ice1712_t *ice, int reg)
{
reg <<= 1;
return ((unsigned short)ice->akm[0].images[reg] << 8) |
ice->akm[0].images[reg + 1];
}
/*
* set the register value of WM codec and remember it
*/
static void wm_put_nocache(ice1712_t *ice, int reg, unsigned short val)
{
unsigned short cval;
cval = (reg << 9) | val;
snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
}
static void wm_put(ice1712_t *ice, int reg, unsigned short val)
{
wm_put_nocache(ice, reg, val);
reg <<= 1;
ice->akm[0].images[reg] = val >> 8;
ice->akm[0].images[reg + 1] = val;
}
/*
* DAC volume attenuation mixer control (-64dB to 0dB)
*/
#define DAC_0dB 0xff
#define DAC_RES 128
#define DAC_MIN (DAC_0dB - DAC_RES)
static int wm_dac_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0; /* mute */
uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
return 0;
}
static int wm_dac_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short val;
int i;
down(&ice->gpio_mutex);
for (i = 0; i < 2; i++) {
val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
val = val > DAC_MIN ? (val - DAC_MIN) : 0;
ucontrol->value.integer.value[i] = val;
}
up(&ice->gpio_mutex);
return 0;
}
static int wm_dac_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short oval, nval;
int i, idx, change = 0;
down(&ice->gpio_mutex);
for (i = 0; i < 2; i++) {
nval = ucontrol->value.integer.value[i];
nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
idx = WM_DAC_ATTEN_L + i;
oval = wm_get(ice, idx) & 0xff;
if (oval != nval) {
wm_put(ice, idx, nval);
wm_put_nocache(ice, idx, nval | 0x100);
change = 1;
}
}
up(&ice->gpio_mutex);
return change;
}
/*
* ADC gain mixer control (-64dB to 0dB)
*/
#define ADC_0dB 0xcf
#define ADC_RES 128
#define ADC_MIN (ADC_0dB - ADC_RES)
static int wm_adc_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0; /* mute (-64dB) */
uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
return 0;
}
static int wm_adc_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short val;
int i;
down(&ice->gpio_mutex);
for (i = 0; i < 2; i++) {
val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
val = val > ADC_MIN ? (val - ADC_MIN) : 0;
ucontrol->value.integer.value[i] = val;
}
up(&ice->gpio_mutex);
return 0;
}
static int wm_adc_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short ovol, nvol;
int i, idx, change = 0;
down(&ice->gpio_mutex);
for (i = 0; i < 2; i++) {
nvol = ucontrol->value.integer.value[i];
nvol = nvol ? (nvol + ADC_MIN) : 0;
idx = WM_ADC_ATTEN_L + i;
ovol = wm_get(ice, idx) & 0xff;
if (ovol != nvol) {
wm_put(ice, idx, nvol);
change = 1;
}
}
up(&ice->gpio_mutex);
return change;
}
/*
* ADC input mux mixer control
*/
static int wm_adc_mux_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm_adc_mux_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int bit = kcontrol->private_value;
down(&ice->gpio_mutex);
ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
up(&ice->gpio_mutex);
return 0;
}
static int wm_adc_mux_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int bit = kcontrol->private_value;
unsigned short oval, nval;
int change;
down(&ice->gpio_mutex);
nval = oval = wm_get(ice, WM_ADC_MUX);
if (ucontrol->value.integer.value[0])
nval |= (1 << bit);
else
nval &= ~(1 << bit);
change = nval != oval;
if (change) {
wm_put(ice, WM_ADC_MUX, nval);
}
up(&ice->gpio_mutex);
return 0;
}
/*
* Analog bypass (In -> Out)
*/
static int wm_bypass_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm_bypass_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
up(&ice->gpio_mutex);
return 0;
}
static int wm_bypass_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short val, oval;
int change = 0;
down(&ice->gpio_mutex);
val = oval = wm_get(ice, WM_OUT_MUX);
if (ucontrol->value.integer.value[0])
val |= 0x04;
else
val &= ~0x04;
if (val != oval) {
wm_put(ice, WM_OUT_MUX, val);
change = 1;
}
up(&ice->gpio_mutex);
return change;
}
/*
* Left/Right swap
*/
static int wm_chswap_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm_chswap_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
up(&ice->gpio_mutex);
return 0;
}
static int wm_chswap_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned short val, oval;
int change = 0;
down(&ice->gpio_mutex);
oval = wm_get(ice, WM_DAC_CTRL1);
val = oval & 0x0f;
if (ucontrol->value.integer.value[0])
val |= 0x60;
else
val |= 0x90;
if (val != oval) {
wm_put(ice, WM_DAC_CTRL1, val);
wm_put_nocache(ice, WM_DAC_CTRL1, val);
change = 1;
}
up(&ice->gpio_mutex);
return change;
}
/*
* write data in the SPI mode
*/
static void set_gpio_bit(ice1712_t *ice, unsigned int bit, int val)
{
unsigned int tmp = snd_ice1712_gpio_read(ice);
if (val)
tmp |= bit;
else
tmp &= ~bit;
snd_ice1712_gpio_write(ice, tmp);
}
static void spi_send_byte(ice1712_t *ice, unsigned char data)
{
int i;
for (i = 0; i < 8; i++) {
set_gpio_bit(ice, PONTIS_CS_CLK, 0);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CLK, 1);
udelay(1);
data <<= 1;
}
}
static unsigned int spi_read_byte(ice1712_t *ice)
{
int i;
unsigned int val = 0;
for (i = 0; i < 8; i++) {
val <<= 1;
set_gpio_bit(ice, PONTIS_CS_CLK, 0);
udelay(1);
if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
val |= 1;
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CLK, 1);
udelay(1);
}
return val;
}
static void spi_write(ice1712_t *ice, unsigned int dev, unsigned int reg, unsigned int data)
{
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
spi_send_byte(ice, data); /* DATA */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
{
unsigned int val;
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev | 1); /* READ */
val = spi_read_byte(ice);
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
return val;
}
/*
* SPDIF input source
*/
static int cs_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
static char *texts[] = {
"Coax", /* RXP0 */
"Optical", /* RXP1 */
"CD", /* RXP2 */
};
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 3;
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
return 0;
}
static int cs_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
up(&ice->gpio_mutex);
return 0;
}
static int cs_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned char val;
int change = 0;
down(&ice->gpio_mutex);
if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
val = 0x80 | (ice->gpio.saved[0] << 3);
spi_write(ice, CS_DEV, 0x04, val);
change = 1;
}
up(&ice->gpio_mutex);
return 0;
}
/*
* GPIO controls
*/
static int pontis_gpio_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0xffff; /* 16bit */
return 0;
}
static int pontis_gpio_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
/* 4-7 reserved */
ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
up(&ice->gpio_mutex);
return 0;
}
static int pontis_gpio_mask_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned int val;
int changed;
down(&ice->gpio_mutex);
/* 4-7 reserved */
val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
changed = val != ice->gpio.write_mask;
ice->gpio.write_mask = val;
up(&ice->gpio_mutex);
return changed;
}
static int pontis_gpio_dir_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
/* 4-7 reserved */
ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
up(&ice->gpio_mutex);
return 0;
}
static int pontis_gpio_dir_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned int val;
int changed;
down(&ice->gpio_mutex);
/* 4-7 reserved */
val = ucontrol->value.integer.value[0] & 0xff0f;
changed = (val != ice->gpio.direction);
ice->gpio.direction = val;
up(&ice->gpio_mutex);
return changed;
}
static int pontis_gpio_data_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
down(&ice->gpio_mutex);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
up(&ice->gpio_mutex);
return 0;
}
static int pontis_gpio_data_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned int val, nval;
int changed = 0;
down(&ice->gpio_mutex);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
val = snd_ice1712_gpio_read(ice) & 0xffff;
nval = ucontrol->value.integer.value[0] & 0xffff;
if (val != nval) {
snd_ice1712_gpio_write(ice, nval);
changed = 1;
}
up(&ice->gpio_mutex);
return changed;
}
/*
* mixers
*/
static snd_kcontrol_new_t pontis_controls[] __devinitdata = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "PCM Playback Volume",
.info = wm_dac_vol_info,
.get = wm_dac_vol_get,
.put = wm_dac_vol_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Capture Volume",
.info = wm_adc_vol_info,
.get = wm_adc_vol_get,
.put = wm_adc_vol_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "CD Capture Switch",
.info = wm_adc_mux_info,
.get = wm_adc_mux_get,
.put = wm_adc_mux_put,
.private_value = 0,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Line Capture Switch",
.info = wm_adc_mux_info,
.get = wm_adc_mux_get,
.put = wm_adc_mux_put,
.private_value = 1,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Analog Bypass Switch",
.info = wm_bypass_info,
.get = wm_bypass_get,
.put = wm_bypass_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Swap Output Channels",
.info = wm_chswap_info,
.get = wm_chswap_get,
.put = wm_chswap_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "IEC958 Input Source",
.info = cs_source_info,
.get = cs_source_get,
.put = cs_source_put,
},
/* FIXME: which interface? */
{
.iface = SNDRV_CTL_ELEM_IFACE_CARD,
.name = "GPIO Mask",
.info = pontis_gpio_mask_info,
.get = pontis_gpio_mask_get,
.put = pontis_gpio_mask_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_CARD,
.name = "GPIO Direction",
.info = pontis_gpio_mask_info,
.get = pontis_gpio_dir_get,
.put = pontis_gpio_dir_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_CARD,
.name = "GPIO Data",
.info = pontis_gpio_mask_info,
.get = pontis_gpio_data_get,
.put = pontis_gpio_data_put,
},
};
/*
* WM codec registers
*/
static void wm_proc_regs_write(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
{
ice1712_t *ice = (ice1712_t *)entry->private_data;
char line[64];
unsigned int reg, val;
down(&ice->gpio_mutex);
while (!snd_info_get_line(buffer, line, sizeof(line))) {
if (sscanf(line, "%x %x", &reg, &val) != 2)
continue;
if (reg <= 0x17 && val <= 0xffff)
wm_put(ice, reg, val);
}
up(&ice->gpio_mutex);
}
static void wm_proc_regs_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
{
ice1712_t *ice = (ice1712_t *)entry->private_data;
int reg, val;
down(&ice->gpio_mutex);
for (reg = 0; reg <= 0x17; reg++) {
val = wm_get(ice, reg);
snd_iprintf(buffer, "%02x = %04x\n", reg, val);
}
up(&ice->gpio_mutex);
}
static void wm_proc_init(ice1712_t *ice)
{
snd_info_entry_t *entry;
if (! snd_card_proc_new(ice->card, "wm_codec", &entry)) {
snd_info_set_text_ops(entry, ice, 1024, wm_proc_regs_read);
entry->mode |= S_IWUSR;
entry->c.text.write_size = 1024;
entry->c.text.write = wm_proc_regs_write;
}
}
static void cs_proc_regs_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
{
ice1712_t *ice = (ice1712_t *)entry->private_data;
int reg, val;
down(&ice->gpio_mutex);
for (reg = 0; reg <= 0x26; reg++) {
val = spi_read(ice, CS_DEV, reg);
snd_iprintf(buffer, "%02x = %02x\n", reg, val);
}
val = spi_read(ice, CS_DEV, 0x7f);
snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
up(&ice->gpio_mutex);
}
static void cs_proc_init(ice1712_t *ice)
{
snd_info_entry_t *entry;
if (! snd_card_proc_new(ice->card, "cs_codec", &entry)) {
snd_info_set_text_ops(entry, ice, 1024, cs_proc_regs_read);
}
}
static int __devinit pontis_add_controls(ice1712_t *ice)
{
unsigned int i;
int err;
for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
if (err < 0)
return err;
}
wm_proc_init(ice);
cs_proc_init(ice);
return 0;
}
/*
* initialize the chip
*/
static int __devinit pontis_init(ice1712_t *ice)
{
static unsigned short wm_inits[] = {
/* These come first to reduce init pop noise */
WM_ADC_MUX, 0x00c0, /* ADC mute */
WM_DAC_MUTE, 0x0001, /* DAC softmute */
WM_DAC_CTRL1, 0x0000, /* DAC mute */
WM_POWERDOWN, 0x0008, /* All power-up except HP */
WM_RESET, 0x0000, /* reset */
};
static unsigned short wm_inits2[] = {
WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
WM_DAC_CTRL1, 0x0090, /* DAC L/R */
WM_OUT_MUX, 0x0001, /* OUT DAC */
WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
// WM_DAC_MASTER, 0x0100, /* DAC master muted */
WM_PHASE_SWAP, 0x0000, /* phase normal */
WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
#if 0
WM_ALC_CTRL1, 0x007b, /* */
WM_ALC_CTRL2, 0x0000, /* */
WM_ALC_CTRL3, 0x0000, /* */
WM_NOISE_GATE, 0x0000, /* */
#endif
WM_DAC_MUTE, 0x0000, /* DAC unmute */
WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
};
static unsigned char cs_inits[] = {
0x04, 0x80, /* RUN, RXP0 */
0x05, 0x05, /* slave, 24bit */
0x01, 0x00,
0x02, 0x00,
0x03, 0x00,
};
unsigned int i;
ice->vt1720 = 1;
ice->num_total_dacs = 2;
ice->num_total_adcs = 2;
/* to remeber the register values */
ice->akm = kcalloc(1, sizeof(akm4xxx_t), GFP_KERNEL);
if (! ice->akm)
return -ENOMEM;
ice->akm_codecs = 1;
/* HACK - use this as the SPDIF source.
* don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
*/
ice->gpio.saved[0] = 0;
/* initialize WM8776 codec */
for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
wm_put(ice, wm_inits[i], wm_inits[i+1]);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
/* initialize CS8416 codec */
/* assert PRST#; MT05 bit 7 */
outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
mdelay(5);
/* deassert PRST# */
outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
return 0;
}
/*
* Pontis boards don't provide the EEPROM data at all.
* hence the driver needs to sets up it properly.
*/
static unsigned char pontis_eeprom[] __devinitdata = {
0x08, /* SYSCONF: clock 256, mpu401, spdif-in/ADC, 1DAC */
0x80, /* ACLINK: I2S */
0xf8, /* I2S: vol, 96k, 24bit, 192k */
0xc3, /* SPDIF: out-en, out-int, spdif-in */
0x07, /* GPIO_DIR */
0x00, /* GPIO_DIR1 */
0x00, /* GPIO_DIR2 (ignored) */
0x0f, /* GPIO_MASK (4-7 reserved for CS8416) */
0xff, /* GPIO_MASK1 */
0x00, /* GPIO_MASK2 (ignored) */
0x06, /* GPIO_STATE (0-low, 1-high, 2-high) */
0x00, /* GPIO_STATE1 */
0x00, /* GPIO_STATE2 (ignored) */
};
/* entry point */
struct snd_ice1712_card_info snd_vt1720_pontis_cards[] __devinitdata = {
{
.subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
.name = "Pontis MS300",
.model = "ms300",
.chip_init = pontis_init,
.build_controls = pontis_add_controls,
.eeprom_size = sizeof(pontis_eeprom),
.eeprom_data = pontis_eeprom,
},
{ } /* terminator */
};

33
sound/pci/ice1712/pontis.h Normal file
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#ifndef __SOUND_PONTIS_H
#define __SOUND_PONTIS_H
/*
* ALSA driver for VIA VT1724 (Envy24HT)
*
* Lowlevel functions for Pontis MS300 boards
*
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define PONTIS_DEVICE_DESC "{Pontis,MS300},"
#define VT1720_SUBDEVICE_PONTIS_MS300 0x00020002 /* a dummy id for MS300 */
extern struct snd_ice1712_card_info snd_vt1720_pontis_cards[];
#endif /* __SOUND_PONTIS_H */

524
sound/pci/ice1712/prodigy192.c Normal file
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/*
* ALSA driver for ICEnsemble VT1724 (Envy24HT)
*
* Lowlevel functions for AudioTrak Prodigy 192 cards
*
* Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
* Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
* Copyright (c) 2004 Kouichi ONO <co2b@ceres.dti.ne.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "envy24ht.h"
#include "prodigy192.h"
#include "stac946x.h"
static inline void stac9460_put(ice1712_t *ice, int reg, unsigned char val)
{
snd_vt1724_write_i2c(ice, PRODIGY192_STAC9460_ADDR, reg, val);
}
static inline unsigned char stac9460_get(ice1712_t *ice, int reg)
{
return snd_vt1724_read_i2c(ice, PRODIGY192_STAC9460_ADDR, reg);
}
/*
* DAC mute control
*/
static int stac9460_dac_mute_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int stac9460_dac_mute_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned char val;
int idx;
if (kcontrol->private_value)
idx = STAC946X_MASTER_VOLUME;
else
idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
val = stac9460_get(ice, idx);
ucontrol->value.integer.value[0] = (~val >> 7) & 0x1;
return 0;
}
static int stac9460_dac_mute_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned char new, old;
int idx;
int change;
if (kcontrol->private_value)
idx = STAC946X_MASTER_VOLUME;
else
idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
old = stac9460_get(ice, idx);
new = (~ucontrol->value.integer.value[0]<< 7 & 0x80) | (old & ~0x80);
change = (new != old);
if (change)
stac9460_put(ice, idx, new);
return change;
}
/*
* DAC volume attenuation mixer control
*/
static int stac9460_dac_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0; /* mute */
uinfo->value.integer.max = 0x7f; /* 0dB */
return 0;
}
static int stac9460_dac_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int idx;
unsigned char vol;
if (kcontrol->private_value)
idx = STAC946X_MASTER_VOLUME;
else
idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
vol = stac9460_get(ice, idx) & 0x7f;
ucontrol->value.integer.value[0] = 0x7f - vol;
return 0;
}
static int stac9460_dac_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int idx;
unsigned char tmp, ovol, nvol;
int change;
if (kcontrol->private_value)
idx = STAC946X_MASTER_VOLUME;
else
idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + STAC946X_LF_VOLUME;
nvol = ucontrol->value.integer.value[0];
tmp = stac9460_get(ice, idx);
ovol = 0x7f - (tmp & 0x7f);
change = (ovol != nvol);
if (change) {
stac9460_put(ice, idx, (0x7f - nvol) | (tmp & 0x80));
}
return change;
}
/*
* ADC mute control
*/
static int stac9460_adc_mute_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int stac9460_adc_mute_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned char val;
int i;
for (i = 0; i < 2; ++i) {
val = stac9460_get(ice, STAC946X_MIC_L_VOLUME + i);
ucontrol->value.integer.value[i] = ~val>>7 & 0x1;
}
return 0;
}
static int stac9460_adc_mute_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
unsigned char new, old;
int i, reg;
int change;
for (i = 0; i < 2; ++i) {
reg = STAC946X_MIC_L_VOLUME + i;
old = stac9460_get(ice, reg);
new = (~ucontrol->value.integer.value[i]<<7&0x80) | (old&~0x80);
change = (new != old);
if (change)
stac9460_put(ice, reg, new);
}
return change;
}
/*
* ADC gain mixer control
*/
static int stac9460_adc_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0; /* 0dB */
uinfo->value.integer.max = 0x0f; /* 22.5dB */
return 0;
}
static int stac9460_adc_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int i, reg;
unsigned char vol;
for (i = 0; i < 2; ++i) {
reg = STAC946X_MIC_L_VOLUME + i;
vol = stac9460_get(ice, reg) & 0x0f;
ucontrol->value.integer.value[i] = 0x0f - vol;
}
return 0;
}
static int stac9460_adc_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int i, reg;
unsigned char ovol, nvol;
int change;
for (i = 0; i < 2; ++i) {
reg = STAC946X_MIC_L_VOLUME + i;
nvol = ucontrol->value.integer.value[i];
ovol = 0x0f - stac9460_get(ice, reg);
change = ((ovol & 0x0f) != nvol);
if (change)
stac9460_put(ice, reg, (0x0f - nvol) | (ovol & ~0x0f));
}
return change;
}
#if 0
/*
* Headphone Amplifier
*/
static int aureon_set_headphone_amp(ice1712_t *ice, int enable)
{
unsigned int tmp, tmp2;
tmp2 = tmp = snd_ice1712_gpio_read(ice);
if (enable)
tmp |= AUREON_HP_SEL;
else
tmp &= ~ AUREON_HP_SEL;
if (tmp != tmp2) {
snd_ice1712_gpio_write(ice, tmp);
return 1;
}
return 0;
}
static int aureon_get_headphone_amp(ice1712_t *ice)
{
unsigned int tmp = snd_ice1712_gpio_read(ice);
return ( tmp & AUREON_HP_SEL )!= 0;
}
static int aureon_bool_info(snd_kcontrol_t *k, snd_ctl_elem_info_t *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int aureon_hpamp_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
ucontrol->value.integer.value[0] = aureon_get_headphone_amp(ice);
return 0;
}
static int aureon_hpamp_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
return aureon_set_headphone_amp(ice,ucontrol->value.integer.value[0]);
}
/*
* Deemphasis
*/
static int aureon_deemp_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
return 0;
}
static int aureon_deemp_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
int temp, temp2;
temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
if (ucontrol->value.integer.value[0])
temp |= 0xf;
else
temp &= ~0xf;
if (temp != temp2) {
wm_put(ice, WM_DAC_CTRL2, temp);
return 1;
}
return 0;
}
/*
* ADC Oversampling
*/
static int aureon_oversampling_info(snd_kcontrol_t *k, snd_ctl_elem_info_t *uinfo)
{
static char *texts[2] = { "128x", "64x" };
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 2;
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
return 0;
}
static int aureon_oversampling_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
return 0;
}
static int aureon_oversampling_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
{
int temp, temp2;
ice1712_t *ice = snd_kcontrol_chip(kcontrol);
temp2 = temp = wm_get(ice, WM_MASTER);
if (ucontrol->value.enumerated.item[0])
temp |= 0x8;
else
temp &= ~0x8;
if (temp != temp2) {
wm_put(ice, WM_MASTER, temp);
return 1;
}
return 0;
}
#endif
/*
* mixers
*/
static snd_kcontrol_new_t stac_controls[] __devinitdata = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Master Playback Switch",
.info = stac9460_dac_mute_info,
.get = stac9460_dac_mute_get,
.put = stac9460_dac_mute_put,
.private_value = 1,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Master Playback Volume",
.info = stac9460_dac_vol_info,
.get = stac9460_dac_vol_get,
.put = stac9460_dac_vol_put,
.private_value = 1,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "DAC Switch",
.count = 6,
.info = stac9460_dac_mute_info,
.get = stac9460_dac_mute_get,
.put = stac9460_dac_mute_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "DAC Volume",
.count = 6,
.info = stac9460_dac_vol_info,
.get = stac9460_dac_vol_get,
.put = stac9460_dac_vol_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "ADC Switch",
.count = 1,
.info = stac9460_adc_mute_info,
.get = stac9460_adc_mute_get,
.put = stac9460_adc_mute_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "ADC Volume",
.count = 1,
.info = stac9460_adc_vol_info,
.get = stac9460_adc_vol_get,
.put = stac9460_adc_vol_put,
},
#if 0
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Capture Route",
.info = wm_adc_mux_info,
.get = wm_adc_mux_get,
.put = wm_adc_mux_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Headphone Amplifier Switch",
.info = aureon_bool_info,
.get = aureon_hpamp_get,
.put = aureon_hpamp_put
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "DAC Deemphasis Switch",
.info = aureon_bool_info,
.get = aureon_deemp_get,
.put = aureon_deemp_put
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "ADC Oversampling",
.info = aureon_oversampling_info,
.get = aureon_oversampling_get,
.put = aureon_oversampling_put
},
#endif
};
static int __devinit prodigy192_add_controls(ice1712_t *ice)
{
unsigned int i;
int err;
for (i = 0; i < ARRAY_SIZE(stac_controls); i++) {
err = snd_ctl_add(ice->card, snd_ctl_new1(&stac_controls[i], ice));
if (err < 0)
return err;
}
return 0;
}
/*
* initialize the chip
*/
static int __devinit prodigy192_init(ice1712_t *ice)
{
static unsigned short stac_inits_prodigy[] = {
STAC946X_RESET, 0,
/* STAC946X_MASTER_VOLUME, 0,
STAC946X_LF_VOLUME, 0,
STAC946X_RF_VOLUME, 0,
STAC946X_LR_VOLUME, 0,
STAC946X_RR_VOLUME, 0,
STAC946X_CENTER_VOLUME, 0,
STAC946X_LFE_VOLUME, 0,*/
(unsigned short)-1
};
unsigned short *p;
/* prodigy 192 */
ice->num_total_dacs = 6;
ice->num_total_adcs = 2;
/* initialize codec */
p = stac_inits_prodigy;
for (; *p != (unsigned short)-1; p += 2)
stac9460_put(ice, p[0], p[1]);
return 0;
}
/*
* Aureon boards don't provide the EEPROM data except for the vendor IDs.
* hence the driver needs to sets up it properly.
*/
static unsigned char prodigy71_eeprom[] __devinitdata = {
0x2b, /* SYSCONF: clock 512, mpu401, spdif-in/ADC, 4DACs */
0x80, /* ACLINK: I2S */
0xf8, /* I2S: vol, 96k, 24bit, 192k */
0xc3, /* SPDIF: out-en, out-int, spdif-in */
0xff, /* GPIO_DIR */
0xff, /* GPIO_DIR1 */
0xbf, /* GPIO_DIR2 */
0x00, /* GPIO_MASK */
0x00, /* GPIO_MASK1 */
0x00, /* GPIO_MASK2 */
0x00, /* GPIO_STATE */
0x00, /* GPIO_STATE1 */
0x00, /* GPIO_STATE2 */
};
/* entry point */
struct snd_ice1712_card_info snd_vt1724_prodigy192_cards[] __devinitdata = {
{
.subvendor = VT1724_SUBDEVICE_PRODIGY192VE,
.name = "Audiotrak Prodigy 192",
.model = "prodigy192",
.chip_init = prodigy192_init,
.build_controls = prodigy192_add_controls,
.eeprom_size = sizeof(prodigy71_eeprom),
.eeprom_data = prodigy71_eeprom,
},
{ } /* terminator */
};

11
sound/pci/ice1712/prodigy192.h Normal file
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#ifndef __SOUND_PRODIGY192_H
#define __SOUND_PRODIGY192_H
#define PRODIGY192_DEVICE_DESC "{AudioTrak,Prodigy 192},"
#define PRODIGY192_STAC9460_ADDR 0x54
#define VT1724_SUBDEVICE_PRODIGY192VE 0x34495345 /* PRODIGY 192 VE */
extern struct snd_ice1712_card_info snd_vt1724_prodigy192_cards[];
#endif /* __SOUND_PRODIGY192_H */

205
sound/pci/ice1712/revo.c Normal file
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/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for M-Audio Revolution 7.1
*
* Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "envy24ht.h"
#include "revo.h"
static void revo_i2s_mclk_changed(ice1712_t *ice)
{
/* assert PRST# to converters; MT05 bit 7 */
outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
mdelay(5);
/* deassert PRST# */
outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
}
/*
* change the rate of envy24HT, AK4355 and AK4381
*/
static void revo_set_rate_val(akm4xxx_t *ak, unsigned int rate)
{
unsigned char old, tmp, dfs;
int reg, shift;
if (rate == 0) /* no hint - S/PDIF input is master, simply return */
return;
/* adjust DFS on codecs */
if (rate > 96000)
dfs = 2;
else if (rate > 48000)
dfs = 1;
else
dfs = 0;
if (ak->type == SND_AK4355) {
reg = 2;
shift = 4;
} else {
reg = 1;
shift = 3;
}
tmp = snd_akm4xxx_get(ak, 0, reg);
old = (tmp >> shift) & 0x03;
if (old == dfs)
return;
/* reset DFS */
snd_akm4xxx_reset(ak, 1);
tmp = snd_akm4xxx_get(ak, 0, reg);
tmp &= ~(0x03 << shift);
tmp |= dfs << shift;
// snd_akm4xxx_write(ak, 0, reg, tmp);
snd_akm4xxx_set(ak, 0, reg, tmp); /* the value is written in reset(0) */
snd_akm4xxx_reset(ak, 0);
}
/*
* initialize the chips on M-Audio Revolution cards
*/
static akm4xxx_t akm_revo_front __devinitdata = {
.type = SND_AK4381,
.num_dacs = 2,
.ops = {
.set_rate_val = revo_set_rate_val
}
};
static struct snd_ak4xxx_private akm_revo_front_priv __devinitdata = {
.caddr = 1,
.cif = 0,
.data_mask = VT1724_REVO_CDOUT,
.clk_mask = VT1724_REVO_CCLK,
.cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
.cs_addr = VT1724_REVO_CS0 | VT1724_REVO_CS2,
.cs_none = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
.add_flags = VT1724_REVO_CCLK, /* high at init */
.mask_flags = 0,
};
static akm4xxx_t akm_revo_surround __devinitdata = {
.type = SND_AK4355,
.idx_offset = 1,
.num_dacs = 6,
.ops = {
.set_rate_val = revo_set_rate_val
}
};
static struct snd_ak4xxx_private akm_revo_surround_priv __devinitdata = {
.caddr = 3,
.cif = 0,
.data_mask = VT1724_REVO_CDOUT,
.clk_mask = VT1724_REVO_CCLK,
.cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
.cs_addr = VT1724_REVO_CS0 | VT1724_REVO_CS1,
.cs_none = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
.add_flags = VT1724_REVO_CCLK, /* high at init */
.mask_flags = 0,
};
static unsigned int rates[] = {
32000, 44100, 48000, 64000, 88200, 96000,
176400, 192000,
};
static snd_pcm_hw_constraint_list_t revo_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static int __devinit revo_init(ice1712_t *ice)
{
akm4xxx_t *ak;
int err;
/* determine I2C, DACs and ADCs */
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_REVOLUTION71:
ice->num_total_dacs = 8;
ice->num_total_adcs = 2;
break;
default:
snd_BUG();
return -EINVAL;
}
ice->gpio.i2s_mclk_changed = revo_i2s_mclk_changed;
/* second stage of initialization, analog parts and others */
ak = ice->akm = kcalloc(2, sizeof(akm4xxx_t), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 2;
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_REVOLUTION71:
if ((err = snd_ice1712_akm4xxx_init(ak, &akm_revo_front, &akm_revo_front_priv, ice)) < 0)
return err;
if ((err = snd_ice1712_akm4xxx_init(ak + 1, &akm_revo_surround, &akm_revo_surround_priv, ice)) < 0)
return err;
/* unmute all codecs */
snd_ice1712_gpio_write_bits(ice, VT1724_REVO_MUTE, VT1724_REVO_MUTE);
break;
}
ice->hw_rates = &revo_rates; /* AK codecs don't support lower than 32k */
return 0;
}
static int __devinit revo_add_controls(ice1712_t *ice)
{
int err;
switch (ice->eeprom.subvendor) {
case VT1724_SUBDEVICE_REVOLUTION71:
err = snd_ice1712_akm4xxx_build_controls(ice);
if (err < 0)
return err;
}
return 0;
}
/* entry point */
struct snd_ice1712_card_info snd_vt1724_revo_cards[] __devinitdata = {
{
.subvendor = VT1724_SUBDEVICE_REVOLUTION71,
.name = "M Audio Revolution-7.1",
.model = "revo71",
.chip_init = revo_init,
.build_controls = revo_add_controls,
},
{ } /* terminator */
};

48
sound/pci/ice1712/revo.h Normal file
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#ifndef __SOUND_REVO_H
#define __SOUND_REVO_H
/*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for M-Audio Revolution 7.1
*
* Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define REVO_DEVICE_DESC \
"{MidiMan M Audio,Revolution 7.1},"
#define VT1724_SUBDEVICE_REVOLUTION71 0x12143036
/* entry point */
extern struct snd_ice1712_card_info snd_vt1724_revo_cards[];
/*
* MidiMan M-Audio Revolution GPIO definitions
*/
#define VT1724_REVO_CCLK 0x02
#define VT1724_REVO_CDIN 0x04 /* not used */
#define VT1724_REVO_CDOUT 0x08
#define VT1724_REVO_CS0 0x10 /* not used */
#define VT1724_REVO_CS1 0x20 /* front AKM4381 chipselect */
#define VT1724_REVO_CS2 0x40 /* surround AKM4355 chipselect */
#define VT1724_REVO_MUTE (1<<22) /* 0 = all mute, 1 = normal operation */
#endif /* __SOUND_REVO_H */

25
sound/pci/ice1712/stac946x.h Normal file
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#ifndef __SOUND_STAC946X_H
#define __SOUND_STAC946X_H
#define STAC946X_RESET 0x00
#define STAC946X_STATUS 0x01
#define STAC946X_MASTER_VOLUME 0x02
#define STAC946X_LF_VOLUME 0x03
#define STAC946X_RF_VOLUME 0x04
#define STAC946X_LR_VOLUME 0x05
#define STAC946X_RR_VOLUME 0x06
#define STAC946X_CENTER_VOLUME 0x07
#define STAC946X_LFE_VOLUME 0x08
#define STAC946X_MIC_L_VOLUME 0x09
#define STAC946X_MIC_R_VOLUME 0x0a
#define STAC946X_DEEMPHASIS 0x0c
#define STAC946X_GENERAL_PURPOSE 0x0d
#define STAC946X_AUDIO_PORT_CONTROL 0x0e
#define STAC946X_MASTER_CLOCKING 0x0f
#define STAC946X_POWERDOWN_CTRL1 0x10
#define STAC946X_POWERDOWN_CTRL2 0x11
#define STAC946X_REVISION_CODE 0x12
#define STAC946X_ADDRESS_CONTROL 0x13
#define STAC946X_ADDRESS 0x14
#endif /* __SOUND_STAC946X_H */

115
sound/pci/ice1712/vt1720_mobo.c Normal file
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/*
* ALSA driver for VT1720/VT1724 (Envy24PT/Envy24HT)
*
* Lowlevel functions for VT1720-based motherboards
*
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include "ice1712.h"
#include "vt1720_mobo.h"
static int __devinit k8x800_init(ice1712_t *ice)
{
ice->vt1720 = 1;
/* VT1616 codec */
ice->num_total_dacs = 6;
ice->num_total_adcs = 2;
/* WM8728 codec */
/* FIXME: TODO */
return 0;
}
static int __devinit k8x800_add_controls(ice1712_t *ice)
{
/* FIXME: needs some quirks for VT1616? */
return 0;
}
/* EEPROM image */
static unsigned char k8x800_eeprom[] __devinitdata = {
0x01, /* SYSCONF: clock 256, 1ADC, 2DACs */
0x02, /* ACLINK: ACLINK, packed */
0x00, /* I2S: - */
0x00, /* SPDIF: - */
0xff, /* GPIO_DIR */
0xff, /* GPIO_DIR1 */
0x00, /* - */
0xff, /* GPIO_MASK */
0xff, /* GPIO_MASK1 */
0x00, /* - */
0x00, /* GPIO_STATE */
0x00, /* GPIO_STATE1 */
0x00, /* - */
};
/* entry point */
struct snd_ice1712_card_info snd_vt1720_mobo_cards[] __devinitdata = {
{
.subvendor = VT1720_SUBDEVICE_K8X800,
.name = "Albatron K8X800 Pro II",
.model = "k8x800",
.chip_init = k8x800_init,
.build_controls = k8x800_add_controls,
.eeprom_size = sizeof(k8x800_eeprom),
.eeprom_data = k8x800_eeprom,
},
{
.subvendor = VT1720_SUBDEVICE_ZNF3_150,
.name = "Chaintech ZNF3-150",
/* identical with k8x800 */
.chip_init = k8x800_init,
.build_controls = k8x800_add_controls,
.eeprom_size = sizeof(k8x800_eeprom),
.eeprom_data = k8x800_eeprom,
},
{
.subvendor = VT1720_SUBDEVICE_ZNF3_250,
.name = "Chaintech ZNF3-250",
/* identical with k8x800 */
.chip_init = k8x800_init,
.build_controls = k8x800_add_controls,
.eeprom_size = sizeof(k8x800_eeprom),
.eeprom_data = k8x800_eeprom,
},
{
.subvendor = VT1720_SUBDEVICE_9CJS,
.name = "Chaintech 9CJS",
/* identical with k8x800 */
.chip_init = k8x800_init,
.build_controls = k8x800_add_controls,
.eeprom_size = sizeof(k8x800_eeprom),
.eeprom_data = k8x800_eeprom,
},
{ } /* terminator */
};

39
sound/pci/ice1712/vt1720_mobo.h Normal file
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#ifndef __SOUND_VT1720_MOBO_H
#define __SOUND_VT1720_MOBO_H
/*
* ALSA driver for VT1720/VT1724 (Envy24PT/Envy24HT)
*
* Lowlevel functions for VT1720-based motherboards
*
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define VT1720_MOBO_DEVICE_DESC "{Albatron,K8X800 Pro II},"\
"{Chaintech,ZNF3-150},"\
"{Chaintech,ZNF3-250},"\
"{Chaintech,9CJS},"
#define VT1720_SUBDEVICE_K8X800 0xf217052c
#define VT1720_SUBDEVICE_ZNF3_150 0x0f2741f6
#define VT1720_SUBDEVICE_ZNF3_250 0x0f2745f6
#define VT1720_SUBDEVICE_9CJS 0x0f272327
extern struct snd_ice1712_card_info snd_vt1720_mobo_cards[];
#endif /* __SOUND_VT1720_MOBO_H */