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Linux-2.6.12-rc2

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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
commit 1da177e4c3
17291 changed files with 6718755 additions and 0 deletions
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98
include/asm-sparc/a.out.h Normal file
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/* $Id: a.out.h,v 1.13 2000/01/09 10:46:53 anton Exp $ */
#ifndef __SPARC_A_OUT_H__
#define __SPARC_A_OUT_H__
#define SPARC_PGSIZE 0x2000 /* Thanks to the sun4 architecture... */
#define SEGMENT_SIZE SPARC_PGSIZE /* whee... */
struct exec {
unsigned char a_dynamic:1; /* A __DYNAMIC is in this image */
unsigned char a_toolversion:7;
unsigned char a_machtype;
unsigned short a_info;
unsigned long a_text; /* length of text, in bytes */
unsigned long a_data; /* length of data, in bytes */
unsigned long a_bss; /* length of bss, in bytes */
unsigned long a_syms; /* length of symbol table, in bytes */
unsigned long a_entry; /* where program begins */
unsigned long a_trsize;
unsigned long a_drsize;
};
/* Where in the file does the text information begin? */
#define N_TXTOFF(x) (N_MAGIC(x) == ZMAGIC ? 0 : sizeof (struct exec))
/* Where do the Symbols start? */
#define N_SYMOFF(x) (N_TXTOFF(x) + (x).a_text + \
(x).a_data + (x).a_trsize + \
(x).a_drsize)
/* Where does text segment go in memory after being loaded? */
#define N_TXTADDR(x) (((N_MAGIC(x) == ZMAGIC) && \
((x).a_entry < SPARC_PGSIZE)) ? \
0 : SPARC_PGSIZE)
/* And same for the data segment.. */
#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ? \
(N_TXTADDR(x) + (x).a_text) \
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
/*
* Sparc relocation types
*/
enum reloc_type
{
RELOC_8,
RELOC_16,
RELOC_32, /* simplest relocs */
RELOC_DISP8,
RELOC_DISP16,
RELOC_DISP32, /* Disp's (pc-rel) */
RELOC_WDISP30,
RELOC_WDISP22, /* SR word disp's */
RELOC_HI22,
RELOC_22, /* SR 22-bit relocs */
RELOC_13,
RELOC_LO10, /* SR 13&10-bit relocs */
RELOC_SFA_BASE,
RELOC_SFA_OFF13, /* SR S.F.A. relocs */
RELOC_BASE10,
RELOC_BASE13,
RELOC_BASE22, /* base_relative pic */
RELOC_PC10,
RELOC_PC22, /* special pc-rel pic */
RELOC_JMP_TBL, /* jmp_tbl_rel in pic */
RELOC_SEGOFF16, /* ShLib offset-in-seg */
RELOC_GLOB_DAT,
RELOC_JMP_SLOT,
RELOC_RELATIVE /* rtld relocs */
};
/*
* Format of a relocation datum.
*/
struct relocation_info /* used when header.a_machtype == M_SPARC */
{
unsigned long r_address; /* relocation addr */
unsigned int r_index:24; /* segment index or symbol index */
unsigned int r_extern:1; /* if F, r_index==SEG#; if T, SYM idx */
int r_pad:2; /* <unused> */
enum reloc_type r_type:5; /* type of relocation to perform */
long r_addend; /* addend for relocation value */
};
#define N_RELOCATION_INFO_DECLARED 1
#ifdef __KERNEL__
#include <asm/page.h>
#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
#endif /* __KERNEL__ */
#endif /* __SPARC_A_OUT_H__ */

64
include/asm-sparc/apc.h Normal file
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/* apc - Driver definitions for power management functions
* of Aurora Personality Chip (APC) on SPARCstation-4/5 and
* derivatives
*
* Copyright (c) 2001 Eric Brower (ebrower@usa.net)
*
*/
#ifndef _SPARC_APC_H
#define _SPARC_APC_H
#include <linux/ioctl.h>
#define APC_IOC 'A'
#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int) /* Get fan speed */
#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int) /* Set fan speed */
#define APCIOCGCPWR _IOR(APC_IOC, 0x02, int) /* Get CPOWER state */
#define APCIOCSCPWR _IOW(APC_IOC, 0x03, int) /* Set CPOWER state */
#define APCIOCGBPORT _IOR(APC_IOC, 0x04, int) /* Get BPORT state */
#define APCIOCSBPORT _IOW(APC_IOC, 0x05, int) /* Set BPORT state */
/*
* Register offsets
*/
#define APC_IDLE_REG 0x00
#define APC_FANCTL_REG 0x20
#define APC_CPOWER_REG 0x24
#define APC_BPORT_REG 0x30
#define APC_REGMASK 0x01
#define APC_BPMASK 0x03
/*
* IDLE - CPU standby values (set to initiate standby)
*/
#define APC_IDLE_ON 0x01
/*
* FANCTL - Fan speed control state values
*/
#define APC_FANCTL_HI 0x00 /* Fan speed high */
#define APC_FANCTL_LO 0x01 /* Fan speed low */
/*
* CPWR - Convenience power outlet state values
*/
#define APC_CPOWER_ON 0x00 /* Conv power on */
#define APC_CPOWER_OFF 0x01 /* Conv power off */
/*
* BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
*
* WARNING: Internal usage of bit ports is platform dependent--
* don't modify BPORT settings unless you know what you are doing.
*
* On SS5 BPA seems to toggle onboard ethernet loopback... -E
*/
#define APC_BPORT_A 0x01 /* Bit Port A */
#define APC_BPORT_B 0x02 /* Bit Port B */
#endif /* !(_SPARC_APC_H) */

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/* $Id: asi.h,v 1.18 1998/03/09 14:04:46 jj Exp $ */
#ifndef _SPARC_ASI_H
#define _SPARC_ASI_H
/* asi.h: Address Space Identifier values for the sparc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*
* Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
* Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
*/
/* The first batch are for the sun4c. */
#define ASI_NULL1 0x00
#define ASI_NULL2 0x01
/* sun4c and sun4 control registers and mmu/vac ops */
#define ASI_CONTROL 0x02
#define ASI_SEGMAP 0x03
#define ASI_PTE 0x04
#define ASI_HWFLUSHSEG 0x05
#define ASI_HWFLUSHPAGE 0x06
#define ASI_REGMAP 0x06
#define ASI_HWFLUSHCONTEXT 0x07
#define ASI_USERTXT 0x08
#define ASI_KERNELTXT 0x09
#define ASI_USERDATA 0x0a
#define ASI_KERNELDATA 0x0b
/* VAC Cache flushing on sun4c and sun4 */
#define ASI_FLUSHSEG 0x0c
#define ASI_FLUSHPG 0x0d
#define ASI_FLUSHCTX 0x0e
/* SPARCstation-5: only 6 bits are decoded. */
/* wo = Write Only, rw = Read Write; */
/* ss = Single Size, as = All Sizes; */
#define ASI_M_RES00 0x00 /* Don't touch... */
#define ASI_M_UNA01 0x01 /* Same here... */
#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
/* The following cache flushing ASIs work only with the 'sta'
* instruction. Results are unpredictable for 'swap' and 'ldstuba',
* so don't do it.
*/
/* These ASI flushes affect external caches too. */
#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
/* Block-copy operations are available only on certain V8 cpus. */
#define ASI_M_BCOPY 0x17 /* Block copy */
/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
/* Block-fill operations are available on certain V8 cpus */
#define ASI_M_BFILL 0x1F
/* This allows direct access to main memory, actually 0x20 to 0x2f are
* the available ASI's for physical ram pass-through, but I don't have
* any idea what the other ones do....
*/
#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
#define ASI_M_SBUS 0x2E /* Direct SBus access */
#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
/* This is ROSS HyperSparc only. */
#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
#define ASI_M_IC_FLCLEAR 0x36
#define ASI_M_DC_FLCLEAR 0x37
#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
/* only available on SuperSparc I */
/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
#endif /* _SPARC_ASI_H */

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/* asmmacro.h: Assembler macros.
*
* Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
*/
#ifndef _SPARC_ASMMACRO_H
#define _SPARC_ASMMACRO_H
#include <linux/config.h>
#include <asm/btfixup.h>
#include <asm/asi.h>
#define GET_PROCESSOR4M_ID(reg) \
rd %tbr, %reg; \
srl %reg, 12, %reg; \
and %reg, 3, %reg;
#define GET_PROCESSOR4D_ID(reg) \
lda [%g0] ASI_M_VIKING_TMP1, %reg;
/* All trap entry points _must_ begin with this macro or else you
* lose. It makes sure the kernel has a proper window so that
* c-code can be called.
*/
#define SAVE_ALL_HEAD \
sethi %hi(trap_setup), %l4; \
jmpl %l4 + %lo(trap_setup), %l6;
#define SAVE_ALL \
SAVE_ALL_HEAD \
nop;
/* All traps low-level code here must end with this macro. */
#define RESTORE_ALL b ret_trap_entry; clr %l6;
/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
likes byte accesses. These are to avoid ifdef mania. */
#ifdef CONFIG_SUN4
#define lduXa lduha
#define stXa stha
#else
#define lduXa lduba
#define stXa stba
#endif
#endif /* !(_SPARC_ASMMACRO_H) */

158
include/asm-sparc/atomic.h Normal file
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/* atomic.h: These still suck, but the I-cache hit rate is higher.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
*
* Additions by Keith M Wesolowski (wesolows@foobazco.org) based
* on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
*/
#ifndef __ARCH_SPARC_ATOMIC__
#define __ARCH_SPARC_ATOMIC__
#include <linux/config.h>
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
#define ATOMIC_INIT(i) { (i) }
extern int __atomic_add_return(int, atomic_t *);
extern void atomic_set(atomic_t *, int);
#define atomic_read(v) ((v)->counter)
#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
#define atomic_inc(v) ((void)__atomic_add_return( 1, (v)))
#define atomic_dec(v) ((void)__atomic_add_return( -1, (v)))
#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
#define atomic_inc_return(v) (__atomic_add_return( 1, (v)))
#define atomic_dec_return(v) (__atomic_add_return( -1, (v)))
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
/* This is the old 24-bit implementation. It's still used internally
* by some sparc-specific code, notably the semaphore implementation.
*/
typedef struct { volatile int counter; } atomic24_t;
#ifndef CONFIG_SMP
#define ATOMIC24_INIT(i) { (i) }
#define atomic24_read(v) ((v)->counter)
#define atomic24_set(v, i) (((v)->counter) = i)
#else
/* We do the bulk of the actual work out of line in two common
* routines in assembler, see arch/sparc/lib/atomic.S for the
* "fun" details.
*
* For SMP the trick is you embed the spin lock byte within
* the word, use the low byte so signedness is easily retained
* via a quick arithmetic shift. It looks like this:
*
* ----------------------------------------
* | signed 24-bit counter value | lock | atomic_t
* ----------------------------------------
* 31 8 7 0
*/
#define ATOMIC24_INIT(i) { ((i) << 8) }
static inline int atomic24_read(const atomic24_t *v)
{
int ret = v->counter;
while(ret & 0xff)
ret = v->counter;
return ret >> 8;
}
#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
#endif
static inline int __atomic24_add(int i, atomic24_t *v)
{
register volatile int *ptr asm("g1");
register int increment asm("g2");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g7");
ptr = &v->counter;
increment = i;
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___atomic24_add\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
: "0" (increment), "r" (ptr)
: "memory", "cc");
return increment;
}
static inline int __atomic24_sub(int i, atomic24_t *v)
{
register volatile int *ptr asm("g1");
register int increment asm("g2");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g7");
ptr = &v->counter;
increment = i;
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___atomic24_sub\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
: "0" (increment), "r" (ptr)
: "memory", "cc");
return increment;
}
#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
#define atomic24_dec_return(v) __atomic24_sub(1, (v))
#define atomic24_inc_return(v) __atomic24_add(1, (v))
#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
/* Atomic operations are already serializing */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#endif /* !(__KERNEL__) */
#endif /* !(__ARCH_SPARC_ATOMIC__) */

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/*
* include/asm-sparc/audioio.h
*
* Sparc Audio Midlayer
* Copyright (C) 1996 Thomas K. Dyas (tdyas@noc.rutgers.edu)
*/
#ifndef _AUDIOIO_H_
#define _AUDIOIO_H_
/*
* SunOS/Solaris /dev/audio interface
*/
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#include <linux/types.h>
#include <linux/time.h>
#include <linux/ioctl.h>
#endif
/*
* This structure contains state information for audio device IO streams.
*/
typedef struct audio_prinfo {
/*
* The following values describe the audio data encoding.
*/
unsigned int sample_rate; /* samples per second */
unsigned int channels; /* number of interleaved channels */
unsigned int precision; /* bit-width of each sample */
unsigned int encoding; /* data encoding method */
/*
* The following values control audio device configuration
*/
unsigned int gain; /* gain level: 0 - 255 */
unsigned int port; /* selected I/O port (see below) */
unsigned int avail_ports; /* available I/O ports (see below) */
unsigned int _xxx[2]; /* Reserved for future use */
unsigned int buffer_size; /* I/O buffer size */
/*
* The following values describe driver state
*/
unsigned int samples; /* number of samples converted */
unsigned int eof; /* End Of File counter (play only) */
unsigned char pause; /* non-zero for pause, zero to resume */
unsigned char error; /* non-zero if overflow/underflow */
unsigned char waiting; /* non-zero if a process wants access */
unsigned char balance; /* stereo channel balance */
unsigned short minordev;
/*
* The following values are read-only state flags
*/
unsigned char open; /* non-zero if open access permitted */
unsigned char active; /* non-zero if I/O is active */
} audio_prinfo_t;
/*
* This structure describes the current state of the audio device.
*/
typedef struct audio_info {
/*
* Per-stream information
*/
audio_prinfo_t play; /* output status information */
audio_prinfo_t record; /* input status information */
/*
* Per-unit/channel information
*/
unsigned int monitor_gain; /* input to output mix: 0 - 255 */
unsigned char output_muted; /* non-zero if output is muted */
unsigned char _xxx[3]; /* Reserved for future use */
unsigned int _yyy[3]; /* Reserved for future use */
} audio_info_t;
/*
* Audio encoding types
*/
#define AUDIO_ENCODING_NONE (0) /* no encoding assigned */
#define AUDIO_ENCODING_ULAW (1) /* u-law encoding */
#define AUDIO_ENCODING_ALAW (2) /* A-law encoding */
#define AUDIO_ENCODING_LINEAR (3) /* Linear PCM encoding */
#define AUDIO_ENCODING_FLOAT (4) /* IEEE float (-1. <-> +1.) */
#define AUDIO_ENCODING_DVI (104) /* DVI ADPCM */
#define AUDIO_ENCODING_LINEAR8 (105) /* 8 bit UNSIGNED */
#define AUDIO_ENCODING_LINEARLE (106) /* Linear PCM LE encoding */
/*
* These ranges apply to record, play, and monitor gain values
*/
#define AUDIO_MIN_GAIN (0) /* minimum gain value */
#define AUDIO_MAX_GAIN (255) /* maximum gain value */
/*
* These values apply to the balance field to adjust channel gain values
*/
#define AUDIO_LEFT_BALANCE (0) /* left channel only */
#define AUDIO_MID_BALANCE (32) /* equal left/right channel */
#define AUDIO_RIGHT_BALANCE (64) /* right channel only */
#define AUDIO_BALANCE_SHIFT (3)
/*
* Generic minimum/maximum limits for number of channels, both modes
*/
#define AUDIO_MIN_PLAY_CHANNELS (1)
#define AUDIO_MAX_PLAY_CHANNELS (4)
#define AUDIO_MIN_REC_CHANNELS (1)
#define AUDIO_MAX_REC_CHANNELS (4)
/*
* Generic minimum/maximum limits for sample precision
*/
#define AUDIO_MIN_PLAY_PRECISION (8)
#define AUDIO_MAX_PLAY_PRECISION (32)
#define AUDIO_MIN_REC_PRECISION (8)
#define AUDIO_MAX_REC_PRECISION (32)
/*
* Define some convenient names for typical audio ports
*/
/*
* output ports (several may be enabled simultaneously)
*/
#define AUDIO_SPEAKER 0x01 /* output to built-in speaker */
#define AUDIO_HEADPHONE 0x02 /* output to headphone jack */
#define AUDIO_LINE_OUT 0x04 /* output to line out */
/*
* input ports (usually only one at a time)
*/
#define AUDIO_MICROPHONE 0x01 /* input from microphone */
#define AUDIO_LINE_IN 0x02 /* input from line in */
#define AUDIO_CD 0x04 /* input from on-board CD inputs */
#define AUDIO_INTERNAL_CD_IN AUDIO_CD /* input from internal CDROM */
#define AUDIO_ANALOG_LOOPBACK 0x40 /* input from output */
/*
* This macro initializes an audio_info structure to 'harmless' values.
* Note that (~0) might not be a harmless value for a flag that was
* a signed int.
*/
#define AUDIO_INITINFO(i) { \
unsigned int *__x__; \
for (__x__ = (unsigned int *)(i); \
(char *) __x__ < (((char *)(i)) + sizeof (audio_info_t)); \
*__x__++ = ~0); \
}
/*
* These allow testing for what the user wants to set
*/
#define AUD_INITVALUE (~0)
#define Modify(X) ((unsigned int)(X) != AUD_INITVALUE)
#define Modifys(X) ((X) != (unsigned short)AUD_INITVALUE)
#define Modifyc(X) ((X) != (unsigned char)AUD_INITVALUE)
/*
* Parameter for the AUDIO_GETDEV ioctl to determine current
* audio devices.
*/
#define MAX_AUDIO_DEV_LEN (16)
typedef struct audio_device {
char name[MAX_AUDIO_DEV_LEN];
char version[MAX_AUDIO_DEV_LEN];
char config[MAX_AUDIO_DEV_LEN];
} audio_device_t;
/*
* Ioctl calls for the audio device.
*/
/*
* AUDIO_GETINFO retrieves the current state of the audio device.
*
* AUDIO_SETINFO copies all fields of the audio_info structure whose
* values are not set to the initialized value (-1) to the device state.
* It performs an implicit AUDIO_GETINFO to return the new state of the
* device. Note that the record.samples and play.samples fields are set
* to the last value before the AUDIO_SETINFO took effect. This allows
* an application to reset the counters while atomically retrieving the
* last value.
*
* AUDIO_DRAIN suspends the calling process until the write buffers are
* empty.
*
* AUDIO_GETDEV returns a structure of type audio_device_t which contains
* three strings. The string "name" is a short identifying string (for
* example, the SBus Fcode name string), the string "version" identifies
* the current version of the device, and the "config" string identifies
* the specific configuration of the audio stream. All fields are
* device-dependent -- see the device specific manual pages for details.
*
* AUDIO_GETDEV_SUNOS returns a number which is an audio device defined
* herein (making it not too portable)
*
* AUDIO_FLUSH stops all playback and recording, clears all queued buffers,
* resets error counters, and restarts recording and playback as appropriate
* for the current sampling mode.
*/
#define AUDIO_GETINFO _IOR('A', 1, audio_info_t)
#define AUDIO_SETINFO _IOWR('A', 2, audio_info_t)
#define AUDIO_DRAIN _IO('A', 3)
#define AUDIO_GETDEV _IOR('A', 4, audio_device_t)
#define AUDIO_GETDEV_SUNOS _IOR('A', 4, int)
#define AUDIO_FLUSH _IO('A', 5)
/* Define possible audio hardware configurations for
* old SunOS-style AUDIO_GETDEV ioctl */
#define AUDIO_DEV_UNKNOWN (0) /* not defined */
#define AUDIO_DEV_AMD (1) /* audioamd device */
#define AUDIO_DEV_SPEAKERBOX (2) /* dbri device with speakerbox */
#define AUDIO_DEV_CODEC (3) /* dbri device (internal speaker) */
#define AUDIO_DEV_CS4231 (5) /* cs4231 device */
/*
* The following ioctl sets the audio device into an internal loopback mode,
* if the hardware supports this. The argument is TRUE to set loopback,
* FALSE to reset to normal operation. If the hardware does not support
* internal loopback, the ioctl should fail with EINVAL.
* Causes ADC data to be digitally mixed in and sent to the DAC.
*/
#define AUDIO_DIAG_LOOPBACK _IOW('A', 101, int)
#endif /* _AUDIOIO_H_ */

89
include/asm-sparc/auxio.h Normal file
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/* $Id: auxio.h,v 1.18 1997/11/07 15:01:45 jj Exp $
* auxio.h: Definitions and code for the Auxiliary I/O register.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_AUXIO_H
#define _SPARC_AUXIO_H
#include <asm/system.h>
#include <asm/vaddrs.h>
/* This register is an unsigned char in IO space. It does two things.
* First, it is used to control the front panel LED light on machines
* that have it (good for testing entry points to trap handlers and irq's)
* Secondly, it controls various floppy drive parameters.
*/
#define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */
#define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */
#define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
#define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
#define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */
#define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
#define AUXIO_LINK_TEST 0x08 /* sun4m - On means TPE Carrier detect. */
/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
#define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
/* Set the following to zero to eject the floppy. */
#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
#ifndef __ASSEMBLY__
/*
* NOTE: these routines are implementation dependent--
* understand the hardware you are querying!
*/
extern void set_auxio(unsigned char bits_on, unsigned char bits_off);
extern unsigned char get_auxio(void); /* .../asm-sparc/floppy.h */
/*
* The following routines are provided for driver-compatibility
* with sparc64 (primarily sunlance.c)
*/
#define AUXIO_LTE_ON 1
#define AUXIO_LTE_OFF 0
/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
*
* on - AUXIO_LTE_ON or AUXIO_LTE_OFF
*/
#define auxio_set_lte(on) \
do { \
if(on) { \
set_auxio(AUXIO_LINK_TEST, 0); \
} else { \
set_auxio(0, AUXIO_LINK_TEST); \
} \
} while (0)
#define AUXIO_LED_ON 1
#define AUXIO_LED_OFF 0
/* auxio_set_led - Set system front panel LED
*
* on - AUXIO_LED_ON or AUXIO_LED_OFF
*/
#define auxio_set_led(on) \
do { \
if(on) { \
set_auxio(AUXIO_LED, 0); \
} else { \
set_auxio(0, AUXIO_LED); \
} \
} while (0)
#endif /* !(__ASSEMBLY__) */
/* AUXIO2 (Power Off Control) */
extern __volatile__ unsigned char * auxio_power_register;
#define AUXIO_POWER_DETECT_FAILURE 32
#define AUXIO_POWER_CLEAR_FAILURE 2
#define AUXIO_POWER_OFF 1
#endif /* !(_SPARC_AUXIO_H) */

27
include/asm-sparc/bitext.h Normal file
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/*
* bitext.h: Bit string operations on the sparc, specific to architecture.
*
* Copyright 2002 Pete Zaitcev <zaitcev@yahoo.com>
*/
#ifndef _SPARC_BITEXT_H
#define _SPARC_BITEXT_H
#include <linux/spinlock.h>
struct bit_map {
spinlock_t lock;
unsigned long *map;
int size;
int used;
int last_off;
int last_size;
int first_free;
int num_colors;
};
extern int bit_map_string_get(struct bit_map *t, int len, int align);
extern void bit_map_clear(struct bit_map *t, int offset, int len);
extern void bit_map_init(struct bit_map *t, unsigned long *map, int size);
#endif /* defined(_SPARC_BITEXT_H) */

537
include/asm-sparc/bitops.h Normal file
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/* $Id: bitops.h,v 1.67 2001/11/19 18:36:34 davem Exp $
* bitops.h: Bit string operations on the Sparc.
*
* Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright 1996 Eddie C. Dost (ecd@skynet.be)
* Copyright 2001 Anton Blanchard (anton@samba.org)
*/
#ifndef _SPARC_BITOPS_H
#define _SPARC_BITOPS_H
#include <linux/compiler.h>
#include <asm/byteorder.h>
#ifdef __KERNEL__
/*
* Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
* is in the highest of the four bytes and bit '31' is the high bit
* within the first byte. Sparc is BIG-Endian. Unless noted otherwise
* all bit-ops return 0 if bit was previously clear and != 0 otherwise.
*/
static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___set_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
return mask != 0;
}
static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___set_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
}
static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___clear_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
return mask != 0;
}
static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___clear_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
}
static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___change_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
return mask != 0;
}
static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
{
register unsigned long mask asm("g2");
register unsigned long *ADDR asm("g1");
register int tmp1 asm("g3");
register int tmp2 asm("g4");
register int tmp3 asm("g5");
register int tmp4 asm("g7");
ADDR = ((unsigned long *) addr) + (nr >> 5);
mask = 1 << (nr & 31);
__asm__ __volatile__(
"mov %%o7, %%g4\n\t"
"call ___change_bit\n\t"
" add %%o7, 8, %%o7\n"
: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
: "0" (mask), "r" (ADDR)
: "memory", "cc");
}
/*
* non-atomic versions
*/
static inline void __set_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p |= mask;
}
static inline void __clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p &= ~mask;
}
static inline void __change_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p ^= mask;
}
static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old | mask;
return (old & mask) != 0;
}
static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old & ~mask;
return (old & mask) != 0;
}
static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1UL << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old ^ mask;
return (old & mask) != 0;
}
#define smp_mb__before_clear_bit() do { } while(0)
#define smp_mb__after_clear_bit() do { } while(0)
/* The following routine need not be atomic. */
static inline int test_bit(int nr, __const__ volatile unsigned long *addr)
{
return (1UL & (((unsigned long *)addr)[nr >> 5] >> (nr & 31))) != 0UL;
}
/* The easy/cheese version for now. */
static inline unsigned long ffz(unsigned long word)
{
unsigned long result = 0;
while(word & 1) {
result++;
word >>= 1;
}
return result;
}
/**
* __ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline int __ffs(unsigned long word)
{
int num = 0;
if ((word & 0xffff) == 0) {
num += 16;
word >>= 16;
}
if ((word & 0xff) == 0) {
num += 8;
word >>= 8;
}
if ((word & 0xf) == 0) {
num += 4;
word >>= 4;
}
if ((word & 0x3) == 0) {
num += 2;
word >>= 2;
}
if ((word & 0x1) == 0)
num += 1;
return num;
}
/*
* Every architecture must define this function. It's the fastest
* way of searching a 140-bit bitmap where the first 100 bits are
* unlikely to be set. It's guaranteed that at least one of the 140
* bits is cleared.
*/
static inline int sched_find_first_bit(unsigned long *b)
{
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 32;
if (unlikely(b[2]))
return __ffs(b[2]) + 64;
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
}
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline int ffs(int x)
{
if (!x)
return 0;
return __ffs((unsigned long)x) + 1;
}
/*
* fls: find last (most-significant) bit set.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
#define fls(x) generic_fls(x)
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
/*
* find_next_zero_bit() finds the first zero bit in a bit string of length
* 'size' bits, starting the search at bit 'offset'. This is largely based
* on Linus's ALPHA routines, which are pretty portable BTW.
*/
static inline unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
const unsigned long *p = addr + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
if (~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
found_middle:
return result + ffz(tmp);
}
/*
* Linus sez that gcc can optimize the following correctly, we'll see if this
* holds on the Sparc as it does for the ALPHA.
*/
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
/**
* find_next_bit - find the first set bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*
* Scheduler induced bitop, do not use.
*/
static inline int find_next_bit(const unsigned long *addr, int size, int offset)
{
const unsigned long *p = addr + (offset >> 5);
int num = offset & ~0x1f;
unsigned long word;
word = *p++;
word &= ~((1 << (offset & 0x1f)) - 1);
while (num < size) {
if (word != 0) {
return __ffs(word) + num;
}
word = *p++;
num += 0x20;
}
return num;
}
/**
* find_first_bit - find the first set bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first set bit, not the number of the byte
* containing a bit.
*/
#define find_first_bit(addr, size) \
find_next_bit((addr), (size), 0)
/*
*/
static inline int test_le_bit(int nr, __const__ unsigned long * addr)
{
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
return (ADDR[nr >> 3] >> (nr & 7)) & 1;
}
/*
* non-atomic versions
*/
static inline void __set_le_bit(int nr, unsigned long *addr)
{
unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
*ADDR |= 1 << (nr & 0x07);
}
static inline void __clear_le_bit(int nr, unsigned long *addr)
{
unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
*ADDR &= ~(1 << (nr & 0x07));
}
static inline int __test_and_set_le_bit(int nr, unsigned long *addr)
{
int mask, retval;
unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
retval = (mask & *ADDR) != 0;
*ADDR |= mask;
return retval;
}
static inline int __test_and_clear_le_bit(int nr, unsigned long *addr)
{
int mask, retval;
unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
retval = (mask & *ADDR) != 0;
*ADDR &= ~mask;
return retval;
}
static inline unsigned long find_next_zero_le_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
const unsigned long *p = addr + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if(offset) {
tmp = *(p++);
tmp |= __swab32(~0UL >> (32-offset));
if(size < 32)
goto found_first;
if(~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while(size & ~31UL) {
if(~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if(!size)
return result;
tmp = *p;
found_first:
tmp = __swab32(tmp) | (~0UL << size);
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
return result + ffz(tmp);
found_middle:
return result + ffz(__swab32(tmp));
}
#define find_first_zero_le_bit(addr, size) \
find_next_zero_le_bit((addr), (size), 0)
#define ext2_set_bit(nr,addr) \
__test_and_set_le_bit((nr),(unsigned long *)(addr))
#define ext2_clear_bit(nr,addr) \
__test_and_clear_le_bit((nr),(unsigned long *)(addr))
#define ext2_set_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_set_bit((nr), (unsigned long *)(addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_clear_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_clear_bit((nr), (unsigned long *)(addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_test_bit(nr,addr) \
test_le_bit((nr),(unsigned long *)(addr))
#define ext2_find_first_zero_bit(addr, size) \
find_first_zero_le_bit((unsigned long *)(addr), (size))
#define ext2_find_next_zero_bit(addr, size, off) \
find_next_zero_le_bit((unsigned long *)(addr), (size), (off))
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) \
test_and_set_bit((nr),(unsigned long *)(addr))
#define minix_set_bit(nr,addr) \
set_bit((nr),(unsigned long *)(addr))
#define minix_test_and_clear_bit(nr,addr) \
test_and_clear_bit((nr),(unsigned long *)(addr))
#define minix_test_bit(nr,addr) \
test_bit((nr),(unsigned long *)(addr))
#define minix_find_first_zero_bit(addr,size) \
find_first_zero_bit((unsigned long *)(addr),(size))
#endif /* __KERNEL__ */
#endif /* defined(_SPARC_BITOPS_H) */

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#ifndef _SPARC_BPP_H
#define _SPARC_BPP_H
/*
* Copyright (c) 1995 Picture Elements
* Stephen Williams
* Gus Baldauf
*
* Linux/SPARC port by Peter Zaitcev.
* Integration into SPARC tree by Tom Dyas.
*/
#include <linux/ioctl.h>
/*
* This is a driver that supports IEEE Std 1284-1994 communications
* with compliant or compatible devices. It will use whatever features
* the device supports, prefering those that are typically faster.
*
* When the device is opened, it is left in COMPATABILITY mode, and
* writes work like any printer device. The driver only attempt to
* negotiate 1284 modes when needed so that plugs can be pulled,
* switch boxes switched, etc., without disrupting things. It will
* also leave the device in compatibility mode when closed.
*/
/*
* This driver also supplies ioctls to manually manipulate the
* pins. This is great for testing devices, or writing code to deal
* with bizzarro-mode of the ACME Special TurboThingy Plus.
*
* NOTE: These ioctl currently do not interact well with
* read/write. Caveat emptor.
*
* PUT_PINS allows us to assign the sense of all the pins, including
* the data pins if being driven by the host. The GET_PINS returns the
* pins that the peripheral drives, including data if appropriate.
*/
# define BPP_PUT_PINS _IOW('B', 1, int)
# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
# define BPP_PUT_DATA _IOW('B', 3, int)
# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
/*
* Set the data bus to input mode. Disengage the data bin driver and
* be prepared to read values from the peripheral. If the arg is 0,
* then revert the bus to output mode.
*/
# define BPP_SET_INPUT _IOW('B', 5, int)
/*
* These bits apply to the PUT operation...
*/
# define BPP_PP_nStrobe 0x0001
# define BPP_PP_nAutoFd 0x0002
# define BPP_PP_nInit 0x0004
# define BPP_PP_nSelectIn 0x0008
/*
* These apply to the GET operation, which also reads the current value
* of the previously put values. A bit mask of these will be returned
* as a bit mask in the return code of the ioctl().
*/
# define BPP_GP_nAck 0x0100
# define BPP_GP_Busy 0x0200
# define BPP_GP_PError 0x0400
# define BPP_GP_Select 0x0800
# define BPP_GP_nFault 0x1000
#endif

94
include/asm-sparc/bsderrno.h Normal file
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/* $Id: bsderrno.h,v 1.3 1996/04/25 06:12:47 davem Exp $
* bsderrno.h: Error numbers for NetBSD binary compatibility
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_BSDERRNO_H
#define _SPARC_BSDERRNO_H
#define BSD_EPERM 1 /* Operation not permitted */
#define BSD_ENOENT 2 /* No such file or directory */
#define BSD_ESRCH 3 /* No such process */
#define BSD_EINTR 4 /* Interrupted system call */
#define BSD_EIO 5 /* Input/output error */
#define BSD_ENXIO 6 /* Device not configured */
#define BSD_E2BIG 7 /* Argument list too long */
#define BSD_ENOEXEC 8 /* Exec format error */
#define BSD_EBADF 9 /* Bad file descriptor */
#define BSD_ECHILD 10 /* No child processes */
#define BSD_EDEADLK 11 /* Resource deadlock avoided */
#define BSD_ENOMEM 12 /* Cannot allocate memory */
#define BSD_EACCES 13 /* Permission denied */
#define BSD_EFAULT 14 /* Bad address */
#define BSD_ENOTBLK 15 /* Block device required */
#define BSD_EBUSY 16 /* Device busy */
#define BSD_EEXIST 17 /* File exists */
#define BSD_EXDEV 18 /* Cross-device link */
#define BSD_ENODEV 19 /* Operation not supported by device */
#define BSD_ENOTDIR 20 /* Not a directory */
#define BSD_EISDIR 21 /* Is a directory */
#define BSD_EINVAL 22 /* Invalid argument */
#define BSD_ENFILE 23 /* Too many open files in system */
#define BSD_EMFILE 24 /* Too many open files */
#define BSD_ENOTTY 25 /* Inappropriate ioctl for device */
#define BSD_ETXTBSY 26 /* Text file busy */
#define BSD_EFBIG 27 /* File too large */
#define BSD_ENOSPC 28 /* No space left on device */
#define BSD_ESPIPE 29 /* Illegal seek */
#define BSD_EROFS 30 /* Read-only file system */
#define BSD_EMLINK 31 /* Too many links */
#define BSD_EPIPE 32 /* Broken pipe */
#define BSD_EDOM 33 /* Numerical argument out of domain */
#define BSD_ERANGE 34 /* Result too large */
#define BSD_EAGAIN 35 /* Resource temporarily unavailable */
#define BSD_EWOULDBLOCK EAGAIN /* Operation would block */
#define BSD_EINPROGRESS 36 /* Operation now in progress */
#define BSD_EALREADY 37 /* Operation already in progress */
#define BSD_ENOTSOCK 38 /* Socket operation on non-socket */
#define BSD_EDESTADDRREQ 39 /* Destination address required */
#define BSD_EMSGSIZE 40 /* Message too long */
#define BSD_EPROTOTYPE 41 /* Protocol wrong type for socket */
#define BSD_ENOPROTOOPT 42 /* Protocol not available */
#define BSD_EPROTONOSUPPORT 43 /* Protocol not supported */
#define BSD_ESOCKTNOSUPPORT 44 /* Socket type not supported */
#define BSD_EOPNOTSUPP 45 /* Operation not supported */
#define BSD_EPFNOSUPPORT 46 /* Protocol family not supported */
#define BSD_EAFNOSUPPORT 47 /* Address family not supported by protocol family */
#define BSD_EADDRINUSE 48 /* Address already in use */
#define BSD_EADDRNOTAVAIL 49 /* Can't assign requested address */
#define BSD_ENETDOWN 50 /* Network is down */
#define BSD_ENETUNREACH 51 /* Network is unreachable */
#define BSD_ENETRESET 52 /* Network dropped connection on reset */
#define BSD_ECONNABORTED 53 /* Software caused connection abort */
#define BSD_ECONNRESET 54 /* Connection reset by peer */
#define BSD_ENOBUFS 55 /* No buffer space available */
#define BSD_EISCONN 56 /* Socket is already connected */
#define BSD_ENOTCONN 57 /* Socket is not connected */
#define BSD_ESHUTDOWN 58 /* Can't send after socket shutdown */
#define BSD_ETOOMANYREFS 59 /* Too many references: can't splice */
#define BSD_ETIMEDOUT 60 /* Operation timed out */
#define BSD_ECONNREFUSED 61 /* Connection refused */
#define BSD_ELOOP 62 /* Too many levels of symbolic links */
#define BSD_ENAMETOOLONG 63 /* File name too long */
#define BSD_EHOSTDOWN 64 /* Host is down */
#define BSD_EHOSTUNREACH 65 /* No route to host */
#define BSD_ENOTEMPTY 66 /* Directory not empty */
#define BSD_EPROCLIM 67 /* Too many processes */
#define BSD_EUSERS 68 /* Too many users */
#define BSD_EDQUOT 69 /* Disc quota exceeded */
#define BSD_ESTALE 70 /* Stale NFS file handle */
#define BSD_EREMOTE 71 /* Too many levels of remote in path */
#define BSD_EBADRPC 72 /* RPC struct is bad */
#define BSD_ERPCMISMATCH 73 /* RPC version wrong */
#define BSD_EPROGUNAVAIL 74 /* RPC prog. not avail */
#define BSD_EPROGMISMATCH 75 /* Program version wrong */
#define BSD_EPROCUNAVAIL 76 /* Bad procedure for program */
#define BSD_ENOLCK 77 /* No locks available */
#define BSD_ENOSYS 78 /* Function not implemented */
#define BSD_EFTYPE 79 /* Inappropriate file type or format */
#define BSD_EAUTH 80 /* Authentication error */
#define BSD_ENEEDAUTH 81 /* Need authenticator */
#define BSD_ELAST 81 /* Must be equal largest errno */
#endif /* !(_SPARC_BSDERRNO_H) */

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/* $Id: btfixup.h,v 1.4 1998/03/09 14:04:43 jj Exp $
* asm-sparc/btfixup.h: Macros for boot time linking.
*
* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
*/
#ifndef _SPARC_BTFIXUP_H
#define _SPARC_BTFIXUP_H
#include <linux/init.h>
#ifndef __ASSEMBLY__
#ifdef MODULE
extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
#else
#define BTFIXUP_SIMM13(__name) ___sf_##__name()
#define BTFIXUP_HALF(__name) ___af_##__name()
#define BTFIXUP_SETHI(__name) ___hf_##__name()
#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
/* This must be written in assembly and present in a sethi */
#define BTFIXUP_BLACKBOX(__name) ___b_##__name
#endif /* MODULE */
/* Fixup call xx */
#define BTFIXUPDEF_CALL(__type, __name, __args...) \
extern __type ___f_##__name(__args); \
extern unsigned ___fs_##__name[3];
#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...) \
extern __type ___f_##__name(__args) __attribute_const__; \
extern unsigned ___fs_##__name[3];
#define BTFIXUP_CALL(__name) ___f_##__name
#define BTFIXUPDEF_BLACKBOX(__name) \
extern unsigned ___bs_##__name[2];
/* Put bottom 13bits into some register variable */
#define BTFIXUPDEF_SIMM13(__name) \
extern unsigned int ___sf_##__name(void) __attribute_const__; \
extern unsigned ___ss_##__name[2]; \
extern __inline__ unsigned int ___sf_##__name(void) { \
unsigned int ret; \
__asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret)); \
return ret; \
}
#define BTFIXUPDEF_SIMM13_INIT(__name,__val) \
extern unsigned int ___sf_##__name(void) __attribute_const__; \
extern unsigned ___ss_##__name[2]; \
extern __inline__ unsigned int ___sf_##__name(void) { \
unsigned int ret; \
__asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
return ret; \
}
/* Put either bottom 13 bits, or upper 22 bits into some register variable
* (depending on the value, this will lead into sethi FIX, reg; or
* mov FIX, reg; )
*/
#define BTFIXUPDEF_HALF(__name) \
extern unsigned int ___af_##__name(void) __attribute_const__; \
extern unsigned ___as_##__name[2]; \
extern __inline__ unsigned int ___af_##__name(void) { \
unsigned int ret; \
__asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret)); \
return ret; \
}
#define BTFIXUPDEF_HALF_INIT(__name,__val) \
extern unsigned int ___af_##__name(void) __attribute_const__; \
extern unsigned ___as_##__name[2]; \
extern __inline__ unsigned int ___af_##__name(void) { \
unsigned int ret; \
__asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
return ret; \
}
/* Put upper 22 bits into some register variable */
#define BTFIXUPDEF_SETHI(__name) \
extern unsigned int ___hf_##__name(void) __attribute_const__; \
extern unsigned ___hs_##__name[2]; \
extern __inline__ unsigned int ___hf_##__name(void) { \
unsigned int ret; \
__asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret)); \
return ret; \
}
#define BTFIXUPDEF_SETHI_INIT(__name,__val) \
extern unsigned int ___hf_##__name(void) __attribute_const__; \
extern unsigned ___hs_##__name[2]; \
extern __inline__ unsigned int ___hf_##__name(void) { \
unsigned int ret; \
__asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" : \
"=r"(ret)); \
return ret; \
}
/* Put a full 32bit integer into some register variable */
#define BTFIXUPDEF_INT(__name) \
extern unsigned char ___i_##__name; \
extern unsigned ___is_##__name[2];
#define BTFIXUPCALL_NORM 0x00000000 /* Always call */
#define BTFIXUPCALL_NOP 0x01000000 /* Possibly optimize to nop */
#define BTFIXUPCALL_RETINT(i) (0x90102000|((i) & 0x1fff)) /* Possibly optimize to mov i, %o0 */
#define BTFIXUPCALL_ORINT(i) (0x90122000|((i) & 0x1fff)) /* Possibly optimize to or %o0, i, %o0 */
#define BTFIXUPCALL_RETO0 0x01000000 /* Return first parameter, actually a nop */
#define BTFIXUPCALL_ANDNINT(i) (0x902a2000|((i) & 0x1fff)) /* Possibly optimize to andn %o0, i, %o0 */
#define BTFIXUPCALL_SWAPO0O1 0xd27a0000 /* Possibly optimize to swap [%o0],%o1 */
#define BTFIXUPCALL_SWAPO0G0 0xc07a0000 /* Possibly optimize to swap [%o0],%g0 */
#define BTFIXUPCALL_SWAPG1G2 0xc4784000 /* Possibly optimize to swap [%g1],%g2 */
#define BTFIXUPCALL_STG0O0 0xc0220000 /* Possibly optimize to st %g0,[%o0] */
#define BTFIXUPCALL_STO1O0 0xd2220000 /* Possibly optimize to st %o1,[%o0] */
#define BTFIXUPSET_CALL(__name, __addr, __insn) \
do { \
___fs_##__name[0] |= 1; \
___fs_##__name[1] = (unsigned long)__addr; \
___fs_##__name[2] = __insn; \
} while (0)
#define BTFIXUPSET_BLACKBOX(__name, __func) \
do { \
___bs_##__name[0] |= 1; \
___bs_##__name[1] = (unsigned long)__func; \
} while (0)
#define BTFIXUPCOPY_CALL(__name, __from) \
do { \
___fs_##__name[0] |= 1; \
___fs_##__name[1] = ___fs_##__from[1]; \
___fs_##__name[2] = ___fs_##__from[2]; \
} while (0)
#define BTFIXUPSET_SIMM13(__name, __val) \
do { \
___ss_##__name[0] |= 1; \
___ss_##__name[1] = (unsigned)__val; \
} while (0)
#define BTFIXUPCOPY_SIMM13(__name, __from) \
do { \
___ss_##__name[0] |= 1; \
___ss_##__name[1] = ___ss_##__from[1]; \
} while (0)
#define BTFIXUPSET_HALF(__name, __val) \
do { \
___as_##__name[0] |= 1; \
___as_##__name[1] = (unsigned)__val; \
} while (0)
#define BTFIXUPCOPY_HALF(__name, __from) \
do { \
___as_##__name[0] |= 1; \
___as_##__name[1] = ___as_##__from[1]; \
} while (0)
#define BTFIXUPSET_SETHI(__name, __val) \
do { \
___hs_##__name[0] |= 1; \
___hs_##__name[1] = (unsigned)__val; \
} while (0)
#define BTFIXUPCOPY_SETHI(__name, __from) \
do { \
___hs_##__name[0] |= 1; \
___hs_##__name[1] = ___hs_##__from[1]; \
} while (0)
#define BTFIXUPSET_INT(__name, __val) \
do { \
___is_##__name[0] |= 1; \
___is_##__name[1] = (unsigned)__val; \
} while (0)
#define BTFIXUPCOPY_INT(__name, __from) \
do { \
___is_##__name[0] |= 1; \
___is_##__name[1] = ___is_##__from[1]; \
} while (0)
#define BTFIXUPVAL_CALL(__name) \
((unsigned long)___fs_##__name[1])
extern void btfixup(void);
#else /* __ASSEMBLY__ */
#define BTFIXUP_SETHI(__name) %hi(___h_ ## __name)
#define BTFIXUP_SETHI_INIT(__name,__val) %hi(___h_ ## __name ## __btset_ ## __val)
#endif /* __ASSEMBLY__ */
#endif /* !(_SPARC_BTFIXUP_H) */

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#ifndef _SPARC_BUG_H
#define _SPARC_BUG_H
/* Only use the inline asm until a gcc release that can handle __builtin_trap
* -rob 2003-06-25
*
* gcc-3.3.1 and later will be OK -DaveM
*/
#if (__GNUC__ > 3) || \
(__GNUC__ == 3 && __GNUC_MINOR__ > 3) || \
(__GNUC__ == 3 && __GNUC_MINOR__ == 3 && __GNUC_PATCHLEVEL__ >= 4)
#define __bug_trap() __builtin_trap()
#else
#define __bug_trap() \
__asm__ __volatile__ ("t 0x5\n\t" : : )
#endif
#ifdef CONFIG_DEBUG_BUGVERBOSE
extern void do_BUG(const char *file, int line);
#define BUG() do { \
do_BUG(__FILE__, __LINE__); \
__bug_trap(); \
} while (0)
#else
#define BUG() __bug_trap()
#endif
#define HAVE_ARCH_BUG
#include <asm-generic/bug.h>
#endif

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/* $Id: bugs.h,v 1.1 1996/12/26 13:25:20 davem Exp $
* include/asm-sparc/bugs.h: Sparc probes for various bugs.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
*/
#include <asm/cpudata.h>
#include <linux/config.h>
extern unsigned long loops_per_jiffy;
static void check_bugs(void)
{
#ifndef CONFIG_SMP
cpu_data(0).udelay_val = loops_per_jiffy;
#endif
}

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/* $Id: byteorder.h,v 1.15 1997/12/16 19:20:44 davem Exp $ */
#ifndef _SPARC_BYTEORDER_H
#define _SPARC_BYTEORDER_H
#include <asm/types.h>
#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _SPARC_BYTEORDER_H */

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/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $
* cache.h: Cache specific code for the Sparc. These include flushing
* and direct tag/data line access.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_CACHE_H
#define _SPARC_CACHE_H
#include <asm/asi.h>
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES 32
#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
#define SMP_CACHE_BYTES 32
/* Direct access to the instruction cache is provided through and
* alternate address space. The IDC bit must be off in the ICCR on
* HyperSparcs for these accesses to work. The code below does not do
* any checking, the caller must do so. These routines are for
* diagnostics only, but could end up being useful. Use with care.
* Also, you are asking for trouble if you execute these in one of the
* three instructions following a %asr/%psr access or modification.
*/
/* First, cache-tag access. */
extern __inline__ unsigned int get_icache_tag(int setnum, int tagnum)
{
unsigned int vaddr, retval;
vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (vaddr), "i" (ASI_M_TXTC_TAG));
return retval;
}
extern __inline__ void put_icache_tag(int setnum, int tagnum, unsigned int entry)
{
unsigned int vaddr;
vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
"memory");
}
/* Second cache-data access. The data is returned two-32bit quantities
* at a time.
*/
extern __inline__ void get_icache_data(int setnum, int tagnum, int subblock,
unsigned int *data)
{
unsigned int value1, value2, vaddr;
vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
((subblock&0x3) << 3);
__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
"or %%g0, %%g2, %0\n\t"
"or %%g0, %%g3, %1\n\t" :
"=r" (value1), "=r" (value2) :
"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
"g2", "g3");
data[0] = value1; data[1] = value2;
}
extern __inline__ void put_icache_data(int setnum, int tagnum, int subblock,
unsigned int *data)
{
unsigned int value1, value2, vaddr;
vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
((subblock&0x3) << 3);
value1 = data[0]; value2 = data[1];
__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
"or %%g0, %1, %%g3\n\t"
"stda %%g2, [%2] %3\n\t" : :
"r" (value1), "r" (value2),
"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
"g2", "g3", "memory" /* no joke */);
}
/* Different types of flushes with the ICACHE. Some of the flushes
* affect both the ICACHE and the external cache. Others only clear
* the ICACHE entries on the cpu itself. V8's (most) allow
* granularity of flushes on the packet (element in line), whole line,
* and entire cache (ie. all lines) level. The ICACHE only flushes are
* ROSS HyperSparc specific and are in ross.h
*/
/* Flushes which clear out both the on-chip and external caches */
extern __inline__ void flush_ei_page(unsigned int addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_PAGE) :
"memory");
}
extern __inline__ void flush_ei_seg(unsigned int addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_SEG) :
"memory");
}
extern __inline__ void flush_ei_region(unsigned int addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_REGION) :
"memory");
}
extern __inline__ void flush_ei_ctx(unsigned int addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_CTX) :
"memory");
}
extern __inline__ void flush_ei_user(unsigned int addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_USER) :
"memory");
}
#endif /* !(_SPARC_CACHE_H) */

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#ifndef _SPARC_CACHEFLUSH_H
#define _SPARC_CACHEFLUSH_H
#include <linux/config.h>
#include <linux/mm.h> /* Common for other includes */
// #include <linux/kernel.h> from pgalloc.h
// #include <linux/sched.h> from pgalloc.h
// #include <asm/page.h>
#include <asm/btfixup.h>
/*
* Fine grained cache flushing.
*/
#ifdef CONFIG_SMP
BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
extern void smp_flush_cache_all(void);
extern void smp_flush_cache_mm(struct mm_struct *mm);
extern void smp_flush_cache_range(struct vm_area_struct *vma,
unsigned long start,
unsigned long end);
extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
extern void smp_flush_page_to_ram(unsigned long page);
extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
#endif /* CONFIG_SMP */
BTFIXUPDEF_CALL(void, flush_cache_all, void)
BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma, pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
} while (0)
BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
extern void sparc_flush_page_to_ram(struct page *page);
#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#endif /* _SPARC_CACHEFLUSH_H */

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/* $Id: checksum.h,v 1.33 2002/02/01 22:01:05 davem Exp $ */
#ifndef __SPARC_CHECKSUM_H
#define __SPARC_CHECKSUM_H
/* checksum.h: IP/UDP/TCP checksum routines on the Sparc.
*
* Copyright(C) 1995 Linus Torvalds
* Copyright(C) 1995 Miguel de Icaza
* Copyright(C) 1996 David S. Miller
* Copyright(C) 1996 Eddie C. Dost
* Copyright(C) 1997 Jakub Jelinek
*
* derived from:
* Alpha checksum c-code
* ix86 inline assembly
* RFC1071 Computing the Internet Checksum
*/
#include <linux/in6.h>
#include <asm/uaccess.h>
/* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
/* the same as csum_partial, but copies from fs:src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
extern unsigned int __csum_partial_copy_sparc_generic (const unsigned char *, unsigned char *);
static inline unsigned int
csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst, int len,
unsigned int sum)
{
register unsigned int ret asm("o0") = (unsigned int)src;
register char *d asm("o1") = dst;
register int l asm("g1") = len;
__asm__ __volatile__ (
"call __csum_partial_copy_sparc_generic\n\t"
" mov %6, %%g7\n"
: "=&r" (ret), "=&r" (d), "=&r" (l)
: "0" (ret), "1" (d), "2" (l), "r" (sum)
: "o2", "o3", "o4", "o5", "o7",
"g2", "g3", "g4", "g5", "g7",
"memory", "cc");
return ret;
}
static inline unsigned int
csum_partial_copy_from_user(const unsigned char __user *src, unsigned char *dst, int len,
unsigned int sum, int *err)
{
if (!access_ok (VERIFY_READ, src, len)) {
*err = -EFAULT;
memset (dst, 0, len);
return sum;
} else {
register unsigned long ret asm("o0") = (unsigned long)src;
register char *d asm("o1") = dst;
register int l asm("g1") = len;
register unsigned int s asm("g7") = sum;
__asm__ __volatile__ (
".section __ex_table,#alloc\n\t"
".align 4\n\t"
".word 1f,2\n\t"
".previous\n"
"1:\n\t"
"call __csum_partial_copy_sparc_generic\n\t"
" st %8, [%%sp + 64]\n"
: "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
: "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
: "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5",
"cc", "memory");
return ret;
}
}
static inline unsigned int
csum_partial_copy_to_user(const unsigned char *src, unsigned char __user *dst, int len,
unsigned int sum, int *err)
{
if (!access_ok (VERIFY_WRITE, dst, len)) {
*err = -EFAULT;
return sum;
} else {
register unsigned long ret asm("o0") = (unsigned long)src;
register char __user *d asm("o1") = dst;
register int l asm("g1") = len;
register unsigned int s asm("g7") = sum;
__asm__ __volatile__ (
".section __ex_table,#alloc\n\t"
".align 4\n\t"
".word 1f,1\n\t"
".previous\n"
"1:\n\t"
"call __csum_partial_copy_sparc_generic\n\t"
" st %8, [%%sp + 64]\n"
: "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
: "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
: "o2", "o3", "o4", "o5", "o7",
"g2", "g3", "g4", "g5",
"cc", "memory");
return ret;
}
}
#define HAVE_CSUM_COPY_USER
#define csum_and_copy_to_user csum_partial_copy_to_user
/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
* the majority of the time.
*/
static inline unsigned short ip_fast_csum(const unsigned char *iph,
unsigned int ihl)
{
unsigned short sum;
/* Note: We must read %2 before we touch %0 for the first time,
* because GCC can legitimately use the same register for
* both operands.
*/
__asm__ __volatile__("sub\t%2, 4, %%g4\n\t"
"ld\t[%1 + 0x00], %0\n\t"
"ld\t[%1 + 0x04], %%g2\n\t"
"ld\t[%1 + 0x08], %%g3\n\t"
"addcc\t%%g2, %0, %0\n\t"
"addxcc\t%%g3, %0, %0\n\t"
"ld\t[%1 + 0x0c], %%g2\n\t"
"ld\t[%1 + 0x10], %%g3\n\t"
"addxcc\t%%g2, %0, %0\n\t"
"addx\t%0, %%g0, %0\n"
"1:\taddcc\t%%g3, %0, %0\n\t"
"add\t%1, 4, %1\n\t"
"addxcc\t%0, %%g0, %0\n\t"
"subcc\t%%g4, 1, %%g4\n\t"
"be,a\t2f\n\t"
"sll\t%0, 16, %%g2\n\t"
"b\t1b\n\t"
"ld\t[%1 + 0x10], %%g3\n"
"2:\taddcc\t%0, %%g2, %%g2\n\t"
"srl\t%%g2, 16, %0\n\t"
"addx\t%0, %%g0, %0\n\t"
"xnor\t%%g0, %0, %0"
: "=r" (sum), "=&r" (iph)
: "r" (ihl), "1" (iph)
: "g2", "g3", "g4", "cc");
return sum;
}
/* Fold a partial checksum without adding pseudo headers. */
static inline unsigned int csum_fold(unsigned int sum)
{
unsigned int tmp;
__asm__ __volatile__("addcc\t%0, %1, %1\n\t"
"srl\t%1, 16, %1\n\t"
"addx\t%1, %%g0, %1\n\t"
"xnor\t%%g0, %1, %0"
: "=&r" (sum), "=r" (tmp)
: "0" (sum), "1" (sum<<16)
: "cc");
return sum;
}
static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr,
unsigned int len,
unsigned short proto,
unsigned int sum)
{
__asm__ __volatile__("addcc\t%1, %0, %0\n\t"
"addxcc\t%2, %0, %0\n\t"
"addxcc\t%3, %0, %0\n\t"
"addx\t%0, %%g0, %0\n\t"
: "=r" (sum), "=r" (saddr)
: "r" (daddr), "r" ((proto<<16)+len), "0" (sum),
"1" (saddr)
: "cc");
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
#define _HAVE_ARCH_IPV6_CSUM
static inline unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
struct in6_addr *daddr,
__u32 len,
unsigned short proto,
unsigned int sum)
{
__asm__ __volatile__ (
"addcc %3, %4, %%g4\n\t"
"addxcc %5, %%g4, %%g4\n\t"
"ld [%2 + 0x0c], %%g2\n\t"
"ld [%2 + 0x08], %%g3\n\t"
"addxcc %%g2, %%g4, %%g4\n\t"
"ld [%2 + 0x04], %%g2\n\t"
"addxcc %%g3, %%g4, %%g4\n\t"
"ld [%2 + 0x00], %%g3\n\t"
"addxcc %%g2, %%g4, %%g4\n\t"
"ld [%1 + 0x0c], %%g2\n\t"
"addxcc %%g3, %%g4, %%g4\n\t"
"ld [%1 + 0x08], %%g3\n\t"
"addxcc %%g2, %%g4, %%g4\n\t"
"ld [%1 + 0x04], %%g2\n\t"
"addxcc %%g3, %%g4, %%g4\n\t"
"ld [%1 + 0x00], %%g3\n\t"
"addxcc %%g2, %%g4, %%g4\n\t"
"addxcc %%g3, %%g4, %0\n\t"
"addx 0, %0, %0\n"
: "=&r" (sum)
: "r" (saddr), "r" (daddr),
"r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
: "g2", "g3", "g4", "cc");
return csum_fold(sum);
}
/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#endif /* !(__SPARC_CHECKSUM_H) */

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/* $Id: clock.h,v 1.3 1995/11/25 02:31:25 davem Exp $
* clock.h: Definitions for clock operations on the Sparc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_CLOCK_H
#define _SPARC_CLOCK_H
/* Foo for now. */
#endif /* !(_SPARC_CLOCK_H) */

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include/asm-sparc/contregs.h Normal file
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/* $Id: contregs.h,v 1.8 2000/12/28 22:49:11 davem Exp $ */
#ifndef _SPARC_CONTREGS_H
#define _SPARC_CONTREGS_H
/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
* space. These are for the mmu's context register, etc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* 3=sun3
4=sun4 (as in sun4 sysmaint student book)
c=sun4c (according to davem) */
#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
#define AC_SYNC_ERR 0x60000000 /* c fault type */
#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
#define AC_M_RESET 0x0700 /* hv Reset Reg */
#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
#define AC_M_ITR 0x1300 /* hv Index Tag Register */
#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
#endif /* _SPARC_CONTREGS_H */

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/* cpudata.h: Per-cpu parameters.
*
* Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
*
* Based on include/asm-sparc64/cpudata.h and Linux 2.4 smp.h
* both (C) David S. Miller.
*/
#ifndef _SPARC_CPUDATA_H
#define _SPARC_CPUDATA_H
#include <linux/percpu.h>
typedef struct {
unsigned long udelay_val;
unsigned long clock_tick;
unsigned int multiplier;
unsigned int counter;
int prom_node;
int mid;
} cpuinfo_sparc;
DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
#endif /* _SPARC_CPUDATA_H */

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#ifndef __SPARC_CPUTIME_H
#define __SPARC_CPUTIME_H
#include <asm-generic/cputime.h>
#endif /* __SPARC_CPUTIME_H */

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include/asm-sparc/current.h Normal file
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/*
* include/asm-sparc/current.h
*
* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
* Copyright (C) 2002 Pete Zaitcev (zaitcev@yahoo.com)
*
* Derived from "include/asm-s390/current.h" by
* Martin Schwidefsky (schwidefsky@de.ibm.com)
* Derived from "include/asm-i386/current.h"
*/
#ifndef _ASM_CURRENT_H
#define _ASM_CURRENT_H
/*
* At the sparc64 DaveM keeps current_thread_info in %g4.
* We might want to consider doing the same to shave a few cycles.
*/
#include <linux/thread_info.h>
struct task_struct;
/* Two stage process (inline + #define) for type-checking. */
/* We also obfuscate get_current() to check if anyone used that by mistake. */
static inline struct task_struct *__get_current(void)
{
return current_thread_info()->task;
}
#define current __get_current()
#endif /* !(_ASM_CURRENT_H) */

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/* $Id: cypress.h,v 1.6 1996/08/29 09:48:09 davem Exp $
* cypress.h: Cypress module specific definitions and defines.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_CYPRESS_H
#define _SPARC_CYPRESS_H
/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
*
* ---------------------------------------------------------------
* |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
* ---------------------------------------------------------------
* 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
*
* MCA: MultiChip Access -- Used for configuration of multiple
* CY7C604/605 cache units.
* MCM: MultiChip Mask -- Again, for multiple cache unit config.
* MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
* MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
* BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
* C: Cacheable -- Indicates whether accesses are cacheable while
* the MMU is off. 0=no 1=yes
* MR: MemoryReflection -- Indicates whether the bus attached to the
* MBus supports memory reflection. 0=no 1=yes (605 only)
* CM: CacheMode -- Indicates whether the cache is operating in write
* through or copy-back mode. 0=write-through 1=copy-back
* CL: CacheLock -- Indicates if the entire cache is locked or not.
* 0=not-locked 1=locked (604 only)
* CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
* NF: NoFault -- Do faults generate traps? 0=yes 1=no
* ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
*/
#define CYPRESS_MCA 0x00c00000
#define CYPRESS_MCM 0x00300000
#define CYPRESS_MVALID 0x00080000
#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */
#define CYPRESS_BMODE 0x00004000
#define CYPRESS_ACENABLE 0x00002000
#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */
#define CYPRESS_CMODE 0x00000400
#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */
#define CYPRESS_CENABLE 0x00000100
#define CYPRESS_NFAULT 0x00000002
#define CYPRESS_MENABLE 0x00000001
extern __inline__ void cypress_flush_page(unsigned long page)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (page), "i" (ASI_M_FLUSH_PAGE));
}
extern __inline__ void cypress_flush_segment(unsigned long addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_SEG));
}
extern __inline__ void cypress_flush_region(unsigned long addr)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_FLUSH_REGION));
}
extern __inline__ void cypress_flush_context(void)
{
__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
"i" (ASI_M_FLUSH_CTX));
}
/* XXX Displacement flushes for buggy chips and initial testing
* XXX go here.
*/
#endif /* !(_SPARC_CYPRESS_H) */

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/* $Id: delay.h,v 1.11 2001/01/01 01:46:15 davem Exp $
* delay.h: Linux delay routines on the Sparc.
*
* Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
*/
#ifndef __SPARC_DELAY_H
#define __SPARC_DELAY_H
#include <linux/config.h>
#include <asm/cpudata.h>
extern __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__("cmp %0, 0\n\t"
"1: bne 1b\n\t"
"subcc %0, 1, %0\n" :
"=&r" (loops) :
"0" (loops) :
"cc");
}
/* This is too messy with inline asm on the Sparc. */
extern void __udelay(unsigned long usecs, unsigned long lpj);
extern void __ndelay(unsigned long nsecs, unsigned long lpj);
#ifdef CONFIG_SMP
#define __udelay_val cpu_data(smp_processor_id()).udelay_val
#else /* SMP */
#define __udelay_val loops_per_jiffy
#endif /* SMP */
#define udelay(__usecs) __udelay(__usecs, __udelay_val)
#define ndelay(__nsecs) __ndelay(__nsecs, __udelay_val)
#endif /* defined(__SPARC_DELAY_H) */

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#include <asm-generic/div64.h>

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include/asm-sparc/dma-mapping.h Normal file
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#ifndef _ASM_SPARC_DMA_MAPPING_H
#define _ASM_SPARC_DMA_MAPPING_H
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <asm-generic/dma-mapping.h>
#else
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
{
BUG();
return NULL;
}
static inline void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
BUG();
}
#endif /* PCI */
#endif /* _ASM_SPARC_DMA_MAPPING_H */

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/* $Id: dma.h,v 1.35 1999/12/27 06:37:09 anton Exp $
* include/asm-sparc/dma.h
*
* Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _ASM_SPARC_DMA_H
#define _ASM_SPARC_DMA_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/vac-ops.h> /* for invalidate's, etc. */
#include <asm/sbus.h>
#include <asm/delay.h>
#include <asm/oplib.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>
struct page;
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* These are irrelevant for Sparc DMA, but we leave it in so that
* things can compile.
*/
#define MAX_DMA_CHANNELS 8
#define MAX_DMA_ADDRESS (~0UL)
#define DMA_MODE_READ 1
#define DMA_MODE_WRITE 2
/* Useful constants */
#define SIZE_16MB (16*1024*1024)
#define SIZE_64K (64*1024)
/* SBUS DMA controller reg offsets */
#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
/* DVMA chip revisions */
enum dvma_rev {
dvmarev0,
dvmaesc1,
dvmarev1,
dvmarev2,
dvmarev3,
dvmarevplus,
dvmahme
};
#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
/* Linux DMA information structure, filled during probe. */
struct sbus_dma {
struct sbus_dma *next;
struct sbus_dev *sdev;
void __iomem *regs;
/* Status, misc info */
int node; /* Prom node for this DMA device */
int running; /* Are we doing DMA now? */
int allocated; /* Are we "owned" by anyone yet? */
/* Transfer information. */
unsigned long addr; /* Start address of current transfer */
int nbytes; /* Size of current transfer */
int realbytes; /* For splitting up large transfers, etc. */
/* DMA revision */
enum dvma_rev revision;
};
extern struct sbus_dma *dma_chain;
/* Broken hardware... */
#ifdef CONFIG_SUN4
/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
* Or is rev0 present only on sun4 boxes? -jj */
#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
#else
#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
#endif
#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
/* Main routines in dma.c */
extern void dvma_init(struct sbus_bus *);
/* Fields in the cond_reg register */
/* First, the version identification bits */
#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
#define DMA_VERS0 0x00000000 /* Sunray DMA version */
#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
#define DMA_VERS1 0x80000000 /* DMA rev 1 */
#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
/* Values describing the burst-size property from the PROM */
#define DMA_BURST1 0x01
#define DMA_BURST2 0x02
#define DMA_BURST4 0x04
#define DMA_BURST8 0x08
#define DMA_BURST16 0x10
#define DMA_BURST32 0x20
#define DMA_BURST64 0x40
#define DMA_BURSTBITS 0x7f
/* Determine highest possible final transfer address given a base */
#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
/* Yes, I hack a lot of elisp in my spare time... */
#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
#define DMA_BEGINDMA_W(regs) \
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
#define DMA_BEGINDMA_R(regs) \
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/* For certain DMA chips, we need to disable ints upon irq entry
* and turn them back on when we are done. So in any ESP interrupt
* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
* when leaving the handler. You have been warned...
*/
#define DMA_IRQ_ENTRY(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
} while (0)
#define DMA_IRQ_EXIT(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
} while(0)
#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
/* Pause until counter runs out or BIT isn't set in the DMA condition
* register.
*/
extern __inline__ void sparc_dma_pause(struct sparc_dma_registers *regs,
unsigned long bit)
{
int ctr = 50000; /* Let's find some bugs ;) */
/* Busy wait until the bit is not set any more */
while((regs->cond_reg&bit) && (ctr>0)) {
ctr--;
__delay(5);
}
/* Check for bogus outcome. */
if(!ctr)
panic("DMA timeout");
}
/* Reset the friggin' thing... */
#define DMA_RESET(dma) do { \
struct sparc_dma_registers *regs = dma->regs; \
/* Let the current FIFO drain itself */ \
sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
/* Reset the logic */ \
regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
__delay(400); /* let the bits set ;) */ \
regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
/* Enable FAST transfers if available */ \
if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
dma->running = 0; \
} while(0)
#endif
#define for_each_dvma(dma) \
for((dma) = dma_chain; (dma); (dma) = (dma)->next)
extern int get_dma_list(char *);
extern int request_dma(unsigned int, __const__ char *);
extern void free_dma(unsigned int);
/* From PCI */
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
/* Routines for data transfer buffers. */
BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
/*
* mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
*
* The mmu_map_dma_area establishes two mappings in one go.
* These mappings point to pages normally mapped at 'va' (linear address).
* First mapping is for CPU visible address at 'a', uncached.
* This is an alias, but it works because it is an uncached mapping.
* Second mapping is for device visible address, or "bus" address.
* The bus address is returned at '*pba'.
*
* These functions seem distinct, but are hard to split. On sun4c,
* at least for now, 'a' is equal to bus address, and retured in *pba.
* On sun4m, page attributes depend on the CPU type, so we have to
* know if we are mapping RAM or I/O, so it has to be an additional argument
* to a separate mapping function for CPU visible mappings.
*/
BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
#endif /* !(_ASM_SPARC_DMA_H) */

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/* $Id: ebus.h,v 1.2 1999/09/11 23:05:55 zaitcev Exp $
* ebus.h: PCI to Ebus pseudo driver software state.
*
* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
*
* Adopted for sparc by V. Roganov and G. Raiko.
*/
#ifndef __SPARC_EBUS_H
#define __SPARC_EBUS_H
#ifndef _LINUX_IOPORT_H
#include <linux/ioport.h>
#endif
#include <asm/oplib.h>
struct linux_ebus_child {
struct linux_ebus_child *next;
struct linux_ebus_device *parent;
struct linux_ebus *bus;
int prom_node;
char prom_name[64];
struct resource resource[PROMREG_MAX];
int num_addrs;
unsigned int irqs[PROMINTR_MAX];
int num_irqs;
};
struct linux_ebus_device {
struct linux_ebus_device *next;
struct linux_ebus_child *children;
struct linux_ebus *bus;
int prom_node;
char prom_name[64];
struct resource resource[PROMREG_MAX];
int num_addrs;
unsigned int irqs[PROMINTR_MAX];
int num_irqs;
};
struct linux_ebus {
struct linux_ebus *next;
struct linux_ebus_device *devices;
struct linux_pbm_info *parent;
struct pci_dev *self;
int prom_node;
char prom_name[64];
struct linux_prom_ebus_ranges ebus_ranges[PROMREG_MAX];
int num_ebus_ranges;
};
struct linux_ebus_dma {
unsigned int dcsr;
unsigned int dacr;
unsigned int dbcr;
};
#define EBUS_DCSR_INT_PEND 0x00000001
#define EBUS_DCSR_ERR_PEND 0x00000002
#define EBUS_DCSR_DRAIN 0x00000004
#define EBUS_DCSR_INT_EN 0x00000010
#define EBUS_DCSR_RESET 0x00000080
#define EBUS_DCSR_WRITE 0x00000100
#define EBUS_DCSR_EN_DMA 0x00000200
#define EBUS_DCSR_CYC_PEND 0x00000400
#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
#define EBUS_DCSR_EN_CNT 0x00002000
#define EBUS_DCSR_TC 0x00004000
#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
#define EBUS_DCSR_BURST_SZ_1 0x00080000
#define EBUS_DCSR_BURST_SZ_4 0x00000000
#define EBUS_DCSR_BURST_SZ_8 0x00040000
#define EBUS_DCSR_BURST_SZ_16 0x000c0000
#define EBUS_DCSR_DIAG_EN 0x00100000
#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
#define EBUS_DCSR_TCI_DIS 0x00800000
#define EBUS_DCSR_EN_NEXT 0x01000000
#define EBUS_DCSR_DMA_ON 0x02000000
#define EBUS_DCSR_A_LOADED 0x04000000
#define EBUS_DCSR_NA_LOADED 0x08000000
#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
extern struct linux_ebus *ebus_chain;
extern void ebus_init(void);
#define for_each_ebus(bus) \
for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
#define for_each_ebusdev(dev, bus) \
for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
#define for_each_edevchild(dev, child) \
for((child) = (dev)->children; (child); (child) = (child)->next)
#endif /* !(__SPARC_EBUS_H) */

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/* $Id: ecc.h,v 1.3 1996/04/25 06:12:57 davem Exp $
* ecc.h: Definitions and defines for the external cache/memory
* controller on the sun4m.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_ECC_H
#define _SPARC_ECC_H
/* These registers are accessed through the SRMMU passthrough ASI 0x20 */
#define ECC_ENABLE 0x00000000 /* ECC enable register */
#define ECC_FSTATUS 0x00000008 /* ECC fault status register */
#define ECC_FADDR 0x00000010 /* ECC fault address register */
#define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
#define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
#define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
/* ECC MBus Arbiter Enable register:
*
* ----------------------------------------
* | |SBUS|MOD3|MOD2|MOD1|RSV|
* ----------------------------------------
* 31 5 4 3 2 1 0
*
* SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
* MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
* MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
* MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
*/
#define ECC_MBAE_SBUS 0x00000010
#define ECC_MBAE_MOD3 0x00000008
#define ECC_MBAE_MOD2 0x00000004
#define ECC_MBAE_MOD1 0x00000002
/* ECC Fault Control Register layout:
*
* -----------------------------
* | RESV | ECHECK | EINT |
* -----------------------------
* 31 2 1 0
*
* ECHECK: Enable ECC checking. 0=off 1=on
* EINT: Enable Interrupts for correctable errors. 0=off 1=on
*/
#define ECC_FCR_CHECK 0x00000002
#define ECC_FCR_INTENAB 0x00000001
/* ECC Fault Address Register Zero layout:
*
* -----------------------------------------------------
* | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
* -----------------------------------------------------
* 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
*
* MID: ModuleID of the faulting processor. ie. who did it?
* S: Supervisor/Privileged access? 0=no 1=yes
* VA: Bits 19-12 of the virtual faulting address, these are the
* superset bits in the virtual cache and can be used for
* a flush operation if necessary.
* BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
* mode bit.
* AT: Did this fault happen during an atomic instruction? 0=no
* 1=yes. This means either an 'ldstub' or 'swap' instruction
* was in progress (but not finished) when this fault happened.
* This indicated whether the bus was locked when the fault
* occurred.
* C: Did the pte for this access indicate that it was cacheable?
* 0=no 1=yes
* SZ: The size of the transaction.
* TYP: The transaction type.
* PADDR: Bits 35-32 of the physical address for the fault.
*/
#define ECC_FADDR0_MIDMASK 0xf0000000
#define ECC_FADDR0_S 0x08000000
#define ECC_FADDR0_VADDR 0x003fc000
#define ECC_FADDR0_BMODE 0x00002000
#define ECC_FADDR0_ATOMIC 0x00001000
#define ECC_FADDR0_CACHE 0x00000800
#define ECC_FADDR0_SIZE 0x00000700
#define ECC_FADDR0_TYPE 0x000000f0
#define ECC_FADDR0_PADDR 0x0000000f
/* ECC Fault Address Register One layout:
*
* -------------------------------------
* | Physical Address 31-0 |
* -------------------------------------
* 31 0
*
* You get the upper 4 bits of the physical address from the
* PADDR field in ECC Fault Address Zero register.
*/
/* ECC Fault Status Register layout:
*
* ----------------------------------------------
* | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
* ----------------------------------------------
* 31-18 17 16 15-8 7-4 3 2 1 0
*
* C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
* MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
* SYNDROME: Controller is mentally unstable.
* DWORD:
* UNC: Uncorrectable error. 0=no 1=yes
* TIMEO: Timeout occurred. 0=no 1=yes
* BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
* C: Correctable error? 0=no 1=yes
*/
#define ECC_FSR_C2ERR 0x00020000
#define ECC_FSR_MULT 0x00010000
#define ECC_FSR_SYND 0x0000ff00
#define ECC_FSR_DWORD 0x000000f0
#define ECC_FSR_UNC 0x00000008
#define ECC_FSR_TIMEO 0x00000004
#define ECC_FSR_BADSLOT 0x00000002
#define ECC_FSR_C 0x00000001
#endif /* !(_SPARC_ECC_H) */

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/* $Id: eeprom.h,v 1.3 1995/11/25 02:31:38 davem Exp $
* eeprom.h: Definitions for the Sun eeprom.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* The EEPROM and the Mostek Mk48t02 use the same IO address space
* for their registers/data areas. The IDPROM lives here too.
*/

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/* $Id: elf.h,v 1.22 2000/07/12 01:27:08 davem Exp $ */
#ifndef __ASMSPARC_ELF_H
#define __ASMSPARC_ELF_H
/*
* ELF register definitions..
*/
#include <linux/config.h>
#include <asm/ptrace.h>
#ifdef __KERNEL__
#include <asm/mbus.h>
#include <asm/uaccess.h>
#endif
/*
* Sparc section types
*/
#define STT_REGISTER 13
/*
* Sparc ELF relocation types
*/
#define R_SPARC_NONE 0
#define R_SPARC_8 1
#define R_SPARC_16 2
#define R_SPARC_32 3
#define R_SPARC_DISP8 4
#define R_SPARC_DISP16 5
#define R_SPARC_DISP32 6
#define R_SPARC_WDISP30 7
#define R_SPARC_WDISP22 8
#define R_SPARC_HI22 9
#define R_SPARC_22 10
#define R_SPARC_13 11
#define R_SPARC_LO10 12
#define R_SPARC_GOT10 13
#define R_SPARC_GOT13 14
#define R_SPARC_GOT22 15
#define R_SPARC_PC10 16
#define R_SPARC_PC22 17
#define R_SPARC_WPLT30 18
#define R_SPARC_COPY 19
#define R_SPARC_GLOB_DAT 20
#define R_SPARC_JMP_SLOT 21
#define R_SPARC_RELATIVE 22
#define R_SPARC_UA32 23
#define R_SPARC_PLT32 24
#define R_SPARC_HIPLT22 25
#define R_SPARC_LOPLT10 26
#define R_SPARC_PCPLT32 27
#define R_SPARC_PCPLT22 28
#define R_SPARC_PCPLT10 29
#define R_SPARC_10 30
#define R_SPARC_11 31
#define R_SPARC_64 32
#define R_SPARC_OLO10 33
#define R_SPARC_WDISP16 40
#define R_SPARC_WDISP19 41
#define R_SPARC_7 43
#define R_SPARC_5 44
#define R_SPARC_6 45
/* Bits present in AT_HWCAP, primarily for Sparc32. */
#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
#define HWCAP_SPARC_STBAR 2
#define HWCAP_SPARC_SWAP 4
#define HWCAP_SPARC_MULDIV 8
#define HWCAP_SPARC_V9 16
#define HWCAP_SPARC_ULTRA3 32
/* For the most part we present code dumps in the format
* Solaris does.
*/
typedef unsigned long elf_greg_t;
#define ELF_NGREG 38
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
/* Format is:
* G0 --> G7
* O0 --> O7
* L0 --> L7
* I0 --> I7
* PSR, PC, nPC, Y, WIM, TBR
*/
#define ELF_CORE_COPY_REGS(__elf_regs, __pt_regs) \
do { unsigned long *dest = &(__elf_regs[0]); \
struct pt_regs *src = (__pt_regs); \
unsigned long __user *sp; \
memcpy(&dest[0], &src->u_regs[0], \
sizeof(unsigned long) * 16); \
/* Don't try this at home kids... */ \
sp = (unsigned long __user *) src->u_regs[14]; \
copy_from_user(&dest[16], sp, \
sizeof(unsigned long) * 16); \
dest[32] = src->psr; \
dest[33] = src->pc; \
dest[34] = src->npc; \
dest[35] = src->y; \
dest[36] = dest[37] = 0; /* XXX */ \
} while(0); /* Janitors: Don't touch this colon. */
typedef struct {
union {
unsigned long pr_regs[32];
double pr_dregs[16];
} pr_fr;
unsigned long __unused;
unsigned long pr_fsr;
unsigned char pr_qcnt;
unsigned char pr_q_entrysize;
unsigned char pr_en;
unsigned int pr_q[64];
} elf_fpregset_t;
#define ELF_CORE_COPY_TASK_REGS(__tsk, __elf_regs) \
({ ELF_CORE_COPY_REGS((*(__elf_regs)), (__tsk)->thread.kregs); 1; })
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_SPARC)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_ARCH EM_SPARC
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define USE_ELF_CORE_DUMP
#ifndef CONFIG_SUN4
#define ELF_EXEC_PAGESIZE 4096
#else
#define ELF_EXEC_PAGESIZE 8192
#endif
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE)
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. This can NOT be done in userspace
on Sparc. */
/* Sun4c has none of the capabilities, most sun4m's have them all.
* XXX This is gross, set some global variable at boot time. -DaveM
*/
#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \
(HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
HWCAP_SPARC_SWAP | \
((srmmu_modtype != Cypress && \
srmmu_modtype != Cypress_vE && \
srmmu_modtype != Cypress_vD) ? \
HWCAP_SPARC_MULDIV : 0)))
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#ifdef __KERNEL__
#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
#endif
#endif /* !(__ASMSPARC_ELF_H) */

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/* $Id: errno.h,v 1.6 1997/04/15 09:03:38 davem Exp $ */
#ifndef _SPARC_ERRNO_H
#define _SPARC_ERRNO_H
/* These match the SunOS error numbering scheme. */
#include <asm-generic/errno-base.h>
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define EINPROGRESS 36 /* Operation now in progress */
#define EALREADY 37 /* Operation already in progress */
#define ENOTSOCK 38 /* Socket operation on non-socket */
#define EDESTADDRREQ 39 /* Destination address required */
#define EMSGSIZE 40 /* Message too long */
#define EPROTOTYPE 41 /* Protocol wrong type for socket */
#define ENOPROTOOPT 42 /* Protocol not available */
#define EPROTONOSUPPORT 43 /* Protocol not supported */
#define ESOCKTNOSUPPORT 44 /* Socket type not supported */
#define EOPNOTSUPP 45 /* Op not supported on transport endpoint */
#define EPFNOSUPPORT 46 /* Protocol family not supported */
#define EAFNOSUPPORT 47 /* Address family not supported by protocol */
#define EADDRINUSE 48 /* Address already in use */
#define EADDRNOTAVAIL 49 /* Cannot assign requested address */
#define ENETDOWN 50 /* Network is down */
#define ENETUNREACH 51 /* Network is unreachable */
#define ENETRESET 52 /* Net dropped connection because of reset */
#define ECONNABORTED 53 /* Software caused connection abort */
#define ECONNRESET 54 /* Connection reset by peer */
#define ENOBUFS 55 /* No buffer space available */
#define EISCONN 56 /* Transport endpoint is already connected */
#define ENOTCONN 57 /* Transport endpoint is not connected */
#define ESHUTDOWN 58 /* No send after transport endpoint shutdown */
#define ETOOMANYREFS 59 /* Too many references: cannot splice */
#define ETIMEDOUT 60 /* Connection timed out */
#define ECONNREFUSED 61 /* Connection refused */
#define ELOOP 62 /* Too many symbolic links encountered */
#define ENAMETOOLONG 63 /* File name too long */
#define EHOSTDOWN 64 /* Host is down */
#define EHOSTUNREACH 65 /* No route to host */
#define ENOTEMPTY 66 /* Directory not empty */
#define EPROCLIM 67 /* SUNOS: Too many processes */
#define EUSERS 68 /* Too many users */
#define EDQUOT 69 /* Quota exceeded */
#define ESTALE 70 /* Stale NFS file handle */
#define EREMOTE 71 /* Object is remote */
#define ENOSTR 72 /* Device not a stream */
#define ETIME 73 /* Timer expired */
#define ENOSR 74 /* Out of streams resources */
#define ENOMSG 75 /* No message of desired type */
#define EBADMSG 76 /* Not a data message */
#define EIDRM 77 /* Identifier removed */
#define EDEADLK 78 /* Resource deadlock would occur */
#define ENOLCK 79 /* No record locks available */
#define ENONET 80 /* Machine is not on the network */
#define ERREMOTE 81 /* SunOS: Too many lvls of remote in path */
#define ENOLINK 82 /* Link has been severed */
#define EADV 83 /* Advertise error */
#define ESRMNT 84 /* Srmount error */
#define ECOMM 85 /* Communication error on send */
#define EPROTO 86 /* Protocol error */
#define EMULTIHOP 87 /* Multihop attempted */
#define EDOTDOT 88 /* RFS specific error */
#define EREMCHG 89 /* Remote address changed */
#define ENOSYS 90 /* Function not implemented */
/* The rest have no SunOS equivalent. */
#define ESTRPIPE 91 /* Streams pipe error */
#define EOVERFLOW 92 /* Value too large for defined data type */
#define EBADFD 93 /* File descriptor in bad state */
#define ECHRNG 94 /* Channel number out of range */
#define EL2NSYNC 95 /* Level 2 not synchronized */
#define EL3HLT 96 /* Level 3 halted */
#define EL3RST 97 /* Level 3 reset */
#define ELNRNG 98 /* Link number out of range */
#define EUNATCH 99 /* Protocol driver not attached */
#define ENOCSI 100 /* No CSI structure available */
#define EL2HLT 101 /* Level 2 halted */
#define EBADE 102 /* Invalid exchange */
#define EBADR 103 /* Invalid request descriptor */
#define EXFULL 104 /* Exchange full */
#define ENOANO 105 /* No anode */
#define EBADRQC 106 /* Invalid request code */
#define EBADSLT 107 /* Invalid slot */
#define EDEADLOCK 108 /* File locking deadlock error */
#define EBFONT 109 /* Bad font file format */
#define ELIBEXEC 110 /* Cannot exec a shared library directly */
#define ENODATA 111 /* No data available */
#define ELIBBAD 112 /* Accessing a corrupted shared library */
#define ENOPKG 113 /* Package not installed */
#define ELIBACC 114 /* Can not access a needed shared library */
#define ENOTUNIQ 115 /* Name not unique on network */
#define ERESTART 116 /* Interrupted syscall should be restarted */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EILSEQ 122 /* Illegal byte sequence */
#define ELIBMAX 123 /* Atmpt to link in too many shared libs */
#define ELIBSCN 124 /* .lib section in a.out corrupted */
#define ENOMEDIUM 125 /* No medium found */
#define EMEDIUMTYPE 126 /* Wrong medium type */
#define ECANCELED 127 /* Operation Cancelled */
#define ENOKEY 128 /* Required key not available */
#define EKEYEXPIRED 129 /* Key has expired */
#define EKEYREVOKED 130 /* Key has been revoked */
#define EKEYREJECTED 131 /* Key was rejected by service */
#endif

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#ifndef __LINUX_FBIO_H
#define __LINUX_FBIO_H
/* Constants used for fbio SunOS compatibility */
/* (C) 1996 Miguel de Icaza */
/* Frame buffer types */
#define FBTYPE_NOTYPE -1
#define FBTYPE_SUN1BW 0 /* mono */
#define FBTYPE_SUN1COLOR 1
#define FBTYPE_SUN2BW 2
#define FBTYPE_SUN2COLOR 3
#define FBTYPE_SUN2GP 4
#define FBTYPE_SUN5COLOR 5
#define FBTYPE_SUN3COLOR 6
#define FBTYPE_MEMCOLOR 7
#define FBTYPE_SUN4COLOR 8
#define FBTYPE_NOTSUN1 9
#define FBTYPE_NOTSUN2 10
#define FBTYPE_NOTSUN3 11
#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
#define FBTYPE_SUNROP_COLOR 13
#define FBTYPE_SUNFB_VIDEO 14
#define FBTYPE_SUNGIFB 15
#define FBTYPE_SUNGPLAS 16
#define FBTYPE_SUNGP3 17
#define FBTYPE_SUNGT 18
#define FBTYPE_SUNLEO 19 /* zx Leo card */
#define FBTYPE_MDICOLOR 20 /* cg14 */
#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
/* Does not seem to be listed in the Sun file either */
#define FBTYPE_CREATOR 22
#define FBTYPE_PCI_IGA1682 23
#define FBTYPE_P9100COLOR 24
/* fbio ioctls */
/* Returned by FBIOGTYPE */
struct fbtype {
int fb_type; /* fb type, see above */
int fb_height; /* pixels */
int fb_width; /* pixels */
int fb_depth;
int fb_cmsize; /* color map entries */
int fb_size; /* fb size in bytes */
};
#define FBIOGTYPE _IOR('F', 0, struct fbtype)
struct fbcmap {
int index; /* first element (0 origin) */
int count;
unsigned char __user *red;
unsigned char __user *green;
unsigned char __user *blue;
};
#ifdef __KERNEL__
#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
#else
#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
#endif
/* # of device specific values */
#define FB_ATTR_NDEVSPECIFIC 8
/* # of possible emulations */
#define FB_ATTR_NEMUTYPES 4
struct fbsattr {
int flags;
int emu_type; /* -1 if none */
int dev_specific[FB_ATTR_NDEVSPECIFIC];
};
struct fbgattr {
int real_type; /* real frame buffer type */
int owner; /* unknown */
struct fbtype fbtype; /* real frame buffer fbtype */
struct fbsattr sattr;
int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
};
#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
#define FBIOSVIDEO _IOW('F', 7, int)
#define FBIOGVIDEO _IOR('F', 8, int)
struct fbcursor {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
char *image; /* cursor image bits */
char *mask; /* cursor mask bits */
};
/* set/get cursor attributes/shape */
#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
/* set/get cursor position */
#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
/* get max cursor size */
#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
/* wid manipulation */
struct fb_wid_alloc {
#define FB_WID_SHARED_8 0
#define FB_WID_SHARED_24 1
#define FB_WID_DBL_8 2
#define FB_WID_DBL_24 3
__u32 wa_type;
__s32 wa_index; /* Set on return */
__u32 wa_count;
};
struct fb_wid_item {
__u32 wi_type;
__s32 wi_index;
__u32 wi_attrs;
__u32 wi_values[32];
};
struct fb_wid_list {
__u32 wl_flags;
__u32 wl_count;
struct fb_wid_item *wl_list;
};
#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
/* Creator ioctls */
#define FFB_IOCTL ('F'<<8)
#define FFB_SYS_INFO (FFB_IOCTL|80)
#define FFB_CLUTREAD (FFB_IOCTL|81)
#define FFB_CLUTPOST (FFB_IOCTL|82)
#define FFB_SETDIAGMODE (FFB_IOCTL|83)
#define FFB_GETMONITORID (FFB_IOCTL|84)
#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
#define FFB_SETSERVER (FFB_IOCTL|87)
#define FFB_SETOVCTL (FFB_IOCTL|88)
#define FFB_GETOVCTL (FFB_IOCTL|89)
#define FFB_GETSAXNUM (FFB_IOCTL|90)
#define FFB_FBDEBUG (FFB_IOCTL|91)
/* Cg14 ioctls */
#define MDI_IOCTL ('M'<<8)
#define MDI_RESET (MDI_IOCTL|1)
#define MDI_GET_CFGINFO (MDI_IOCTL|2)
#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
# define MDI_32_PIX 32
# define MDI_16_PIX 16
# define MDI_8_PIX 8
struct mdi_cfginfo {
int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
int mdi_type; /* FBTYPE name */
int mdi_height; /* height */
int mdi_width; /* widht */
int mdi_size; /* available ram */
int mdi_mode; /* 8bpp, 16bpp or 32bpp */
int mdi_pixfreq; /* pixel clock (from PROM) */
};
/* SparcLinux specific ioctl for the MDI, should be replaced for
* the SET_XLUT/SET_CLUTn ioctls instead
*/
#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
/* leo & ffb ioctls */
struct fb_clut_alloc {
__u32 clutid; /* Set on return */
__u32 flag;
__u32 index;
};
struct fb_clut {
#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
char * red;
char * green;
char * blue;
};
struct fb_clut32 {
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
__u32 red;
__u32 green;
__u32 blue;
};
#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
#ifdef __KERNEL__
/* Addresses on the fd of a cgsix that are mappable */
#define CG6_FBC 0x70000000
#define CG6_TEC 0x70001000
#define CG6_BTREGS 0x70002000
#define CG6_FHC 0x70004000
#define CG6_THC 0x70005000
#define CG6_ROM 0x70006000
#define CG6_RAM 0x70016000
#define CG6_DHC 0x80000000
#define CG3_MMAP_OFFSET 0x4000000
/* Addresses on the fd of a tcx that are mappable */
#define TCX_RAM8BIT 0x00000000
#define TCX_RAM24BIT 0x01000000
#define TCX_UNK3 0x10000000
#define TCX_UNK4 0x20000000
#define TCX_CONTROLPLANE 0x28000000
#define TCX_UNK6 0x30000000
#define TCX_UNK7 0x38000000
#define TCX_TEC 0x70000000
#define TCX_BTREGS 0x70002000
#define TCX_THC 0x70004000
#define TCX_DHC 0x70008000
#define TCX_ALT 0x7000a000
#define TCX_SYNC 0x7000e000
#define TCX_UNK2 0x70010000
/* CG14 definitions */
/* Offsets into the OBIO space: */
#define CG14_REGS 0 /* registers */
#define CG14_CURSORREGS 0x1000 /* cursor registers */
#define CG14_DACREGS 0x2000 /* DAC registers */
#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
#define CG14_CLUT1 0x4000 /* Color Look Up Table */
#define CG14_CLUT2 0x5000 /* Color Look Up Table */
#define CG14_CLUT3 0x6000 /* Color Look Up Table */
#define CG14_AUTO 0xf000
#endif /* KERNEL */
/* These are exported to userland for applications to use */
/* Mappable offsets for the cg14: control registers */
#define MDI_DIRECT_MAP 0x10000000
#define MDI_CTLREG_MAP 0x20000000
#define MDI_CURSOR_MAP 0x30000000
#define MDI_SHDW_VRT_MAP 0x40000000
/* Mappable offsets for the cg14: frame buffer resolutions */
/* 32 bits */
#define MDI_CHUNKY_XBGR_MAP 0x50000000
#define MDI_CHUNKY_BGR_MAP 0x60000000
/* 16 bits */
#define MDI_PLANAR_X16_MAP 0x70000000
#define MDI_PLANAR_C16_MAP 0x80000000
/* 8 bit is done as CG3 MMAP offset */
/* 32 bits, planar */
#define MDI_PLANAR_X32_MAP 0x90000000
#define MDI_PLANAR_B32_MAP 0xa0000000
#define MDI_PLANAR_G32_MAP 0xb0000000
#define MDI_PLANAR_R32_MAP 0xc0000000
/* Mappable offsets on leo */
#define LEO_SS0_MAP 0x00000000
#define LEO_LC_SS0_USR_MAP 0x00800000
#define LEO_LD_SS0_MAP 0x00801000
#define LEO_LX_CURSOR_MAP 0x00802000
#define LEO_SS1_MAP 0x00803000
#define LEO_LC_SS1_USR_MAP 0x01003000
#define LEO_LD_SS1_MAP 0x01004000
#define LEO_UNK_MAP 0x01005000
#define LEO_LX_KRN_MAP 0x01006000
#define LEO_LC_SS0_KRN_MAP 0x01007000
#define LEO_LC_SS1_KRN_MAP 0x01008000
#define LEO_LD_GBL_MAP 0x01009000
#define LEO_UNK2_MAP 0x0100a000
#endif /* __LINUX_FBIO_H */

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/* $Id: fcntl.h,v 1.16 2001/09/20 00:35:33 davem Exp $ */
#ifndef _SPARC_FCNTL_H
#define _SPARC_FCNTL_H
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
#define O_RDONLY 0x0000
#define O_WRONLY 0x0001
#define O_RDWR 0x0002
#define O_ACCMODE 0x0003
#define O_APPEND 0x0008
#define FASYNC 0x0040 /* fcntl, for BSD compatibility */
#define O_CREAT 0x0200 /* not fcntl */
#define O_TRUNC 0x0400 /* not fcntl */
#define O_EXCL 0x0800 /* not fcntl */
#define O_SYNC 0x2000
#define O_NONBLOCK 0x4000
#define O_NDELAY (0x0004 | O_NONBLOCK)
#define O_NOCTTY 0x8000 /* not fcntl */
#define O_DIRECTORY 0x10000 /* must be a directory */
#define O_NOFOLLOW 0x20000 /* don't follow links */
#define O_LARGEFILE 0x40000
#define O_DIRECT 0x100000 /* direct disk access hint */
#define O_NOATIME 0x200000
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get close_on_exec */
#define F_SETFD 2 /* set/clear close_on_exec */
#define F_GETFL 3 /* get file->f_flags */
#define F_SETFL 4 /* set file->f_flags */
#define F_GETOWN 5 /* for sockets. */
#define F_SETOWN 6 /* for sockets. */
#define F_GETLK 7
#define F_SETLK 8
#define F_SETLKW 9
#define F_SETSIG 10 /* for sockets. */
#define F_GETSIG 11 /* for sockets. */
#define F_GETLK64 12 /* using 'struct flock64' */
#define F_SETLK64 13
#define F_SETLKW64 14
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
/* for posix fcntl() and lockf() */
#define F_RDLCK 1
#define F_WRLCK 2
#define F_UNLCK 3
/* for old implementation of bsd flock () */
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
/* for leases */
#define F_INPROGRESS 16
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
#define LOCK_MAND 32 /* This is a mandatory flock */
#define LOCK_READ 64 /* ... Which allows concurrent read operations */
#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
struct flock {
short l_type;
short l_whence;
off_t l_start;
off_t l_len;
pid_t l_pid;
short __unused;
};
struct flock64 {
short l_type;
short l_whence;
loff_t l_start;
loff_t l_len;
pid_t l_pid;
short __unused;
};
#define F_LINUX_SPECIFIC_BASE 1024
#endif

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/*
* fixmap.h: compile-time virtual memory allocation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Ingo Molnar
*
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
*/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/page.h>
#ifdef CONFIG_HIGHMEM
#include <linux/threads.h>
#include <asm/kmap_types.h>
#endif
/*
* Here we define all the compile-time 'special' virtual
* addresses. The point is to have a constant address at
* compile time, but to set the physical address only
* in the boot process. We allocate these special addresses
* from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
* Also this lets us do fail-safe vmalloc(), we
* can guarantee that these special addresses and
* vmalloc()-ed addresses never overlap.
*
* these 'compile-time allocated' memory buffers are
* fixed-size 4k pages. (or larger if used with an increment
* highger than 1) use fixmap_set(idx,phys) to associate
* physical memory with fixmap indices.
*
* TLB entries of such buffers will not be flushed across
* task switches.
*/
/*
* on UP currently we will have no trace of the fixmap mechanism,
* no page table allocations, etc. This might change in the
* future, say framebuffers for the console driver(s) could be
* fix-mapped?
*/
enum fixed_addresses {
FIX_HOLE,
#ifdef CONFIG_HIGHMEM
FIX_KMAP_BEGIN,
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
#endif
__end_of_fixed_addresses
};
extern void __set_fixmap (enum fixed_addresses idx,
unsigned long phys, pgprot_t flags);
#define set_fixmap(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL)
/*
* Some hardware wants to get fixmapped without caching.
*/
#define set_fixmap_nocache(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
/*
* used by vmalloc.c.
*
* Leave one empty page between IO pages at 0xfd000000 and
* the start of the fixmap.
*/
#define FIXADDR_TOP (0xfcfff000UL)
#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
extern void __this_fixmap_does_not_exist(void);
/*
* 'index to address' translation. If anyone tries to use the idx
* directly without tranlation, we catch the bug with a NULL-deference
* kernel oops. Illegal ranges of incoming indices are caught too.
*/
static inline unsigned long fix_to_virt(const unsigned int idx)
{
/*
* this branch gets completely eliminated after inlining,
* except when someone tries to use fixaddr indices in an
* illegal way. (such as mixing up address types or using
* out-of-range indices).
*
* If it doesn't get removed, the linker will complain
* loudly with a reasonably clear error message..
*/
if (idx >= __end_of_fixed_addresses)
__this_fixmap_does_not_exist();
return __fix_to_virt(idx);
}
static inline unsigned long virt_to_fix(const unsigned long vaddr)
{
BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
return __virt_to_fix(vaddr);
}
#endif

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/* asm-sparc/floppy.h: Sparc specific parts of the Floppy driver.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef __ASM_SPARC_FLOPPY_H
#define __ASM_SPARC_FLOPPY_H
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/idprom.h>
#include <asm/machines.h>
#include <asm/oplib.h>
#include <asm/auxio.h>
#include <asm/irq.h>
/* We don't need no stinkin' I/O port allocation crap. */
#undef release_region
#undef check_region
#undef request_region
#define release_region(X, Y) do { } while(0)
#define check_region(X, Y) (0)
#define request_region(X, Y, Z) (1)
/* References:
* 1) Netbsd Sun floppy driver.
* 2) NCR 82077 controller manual
* 3) Intel 82077 controller manual
*/
struct sun_flpy_controller {
volatile unsigned char status_82072; /* Main Status reg. */
#define dcr_82072 status_82072 /* Digital Control reg. */
#define status1_82077 status_82072 /* Auxiliary Status reg. 1 */
volatile unsigned char data_82072; /* Data fifo. */
#define status2_82077 data_82072 /* Auxiliary Status reg. 2 */
volatile unsigned char dor_82077; /* Digital Output reg. */
volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
volatile unsigned char status_82077; /* Main Status Register. */
#define drs_82077 status_82077 /* Digital Rate Select reg. */
volatile unsigned char data_82077; /* Data fifo. */
volatile unsigned char ___unused;
volatile unsigned char dir_82077; /* Digital Input reg. */
#define dcr_82077 dir_82077 /* Config Control reg. */
};
/* You'll only ever find one controller on a SparcStation anyways. */
static struct sun_flpy_controller *sun_fdc = NULL;
volatile unsigned char *fdc_status;
struct sun_floppy_ops {
unsigned char (*fd_inb)(int port);
void (*fd_outb)(unsigned char value, int port);
};
static struct sun_floppy_ops sun_fdops;
#define fd_inb(port) sun_fdops.fd_inb(port)
#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
#define fd_enable_dma() sun_fd_enable_dma()
#define fd_disable_dma() sun_fd_disable_dma()
#define fd_request_dma() (0) /* nothing... */
#define fd_free_dma() /* nothing... */
#define fd_clear_dma_ff() /* nothing... */
#define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode)
#define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr)
#define fd_set_dma_count(count) sun_fd_set_dma_count(count)
#define fd_enable_irq() /* nothing... */
#define fd_disable_irq() /* nothing... */
#define fd_cacheflush(addr, size) /* nothing... */
#define fd_request_irq() sun_fd_request_irq()
#define fd_free_irq() /* nothing... */
#if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
#define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size))
#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
#endif
#define FLOPPY_MOTOR_MASK 0x10
/* XXX This isn't really correct. XXX */
#define get_dma_residue(x) (0)
#define FLOPPY0_TYPE 4
#define FLOPPY1_TYPE 0
/* Super paranoid... */
#undef HAVE_DISABLE_HLT
/* Here is where we catch the floppy driver trying to initialize,
* therefore this is where we call the PROM device tree probing
* routine etc. on the Sparc.
*/
#define FDC1 sun_floppy_init()
#define N_FDC 1
#define N_DRIVE 8
/* No 64k boundary crossing problems on the Sparc. */
#define CROSS_64KB(a,s) (0)
/* Routines unique to each controller type on a Sun. */
static unsigned char sun_82072_fd_inb(int port)
{
udelay(5);
switch(port & 7) {
default:
printk("floppy: Asked to read unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 4: /* FD_STATUS */
return sun_fdc->status_82072 & ~STATUS_DMA;
case 5: /* FD_DATA */
return sun_fdc->data_82072;
case 7: /* FD_DIR */
return (get_auxio() & AUXIO_FLPY_DCHG)? 0x80: 0;
};
panic("sun_82072_fd_inb: How did I get here?");
}
static void sun_82072_fd_outb(unsigned char value, int port)
{
udelay(5);
switch(port & 7) {
default:
printk("floppy: Asked to write to unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 2: /* FD_DOR */
/* Oh geese, 82072 on the Sun has no DOR register,
* the functionality is implemented via the AUXIO
* I/O register. So we must emulate the behavior.
*
* ASSUMPTIONS: There will only ever be one floppy
* drive attached to a Sun controller
* and it will be at drive zero.
*/
{
unsigned bits = 0;
if (value & 0x10) bits |= AUXIO_FLPY_DSEL;
if ((value & 0x80) == 0) bits |= AUXIO_FLPY_EJCT;
set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
}
break;
case 5: /* FD_DATA */
sun_fdc->data_82072 = value;
break;
case 7: /* FD_DCR */
sun_fdc->dcr_82072 = value;
break;
case 4: /* FD_STATUS */
sun_fdc->status_82072 = value;
break;
};
return;
}
static unsigned char sun_82077_fd_inb(int port)
{
udelay(5);
switch(port & 7) {
default:
printk("floppy: Asked to read unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 4: /* FD_STATUS */
return sun_fdc->status_82077 & ~STATUS_DMA;
case 5: /* FD_DATA */
return sun_fdc->data_82077;
case 7: /* FD_DIR */
/* XXX: Is DCL on 0x80 in sun4m? */
return sun_fdc->dir_82077;
};
panic("sun_82072_fd_inb: How did I get here?");
}
static void sun_82077_fd_outb(unsigned char value, int port)
{
udelay(5);
switch(port & 7) {
default:
printk("floppy: Asked to write to unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 2: /* FD_DOR */
/* Happily, the 82077 has a real DOR register. */
sun_fdc->dor_82077 = value;
break;
case 5: /* FD_DATA */
sun_fdc->data_82077 = value;
break;
case 7: /* FD_DCR */
sun_fdc->dcr_82077 = value;
break;
case 4: /* FD_STATUS */
sun_fdc->status_82077 = value;
break;
};
return;
}
/* For pseudo-dma (Sun floppy drives have no real DMA available to
* them so we must eat the data fifo bytes directly ourselves) we have
* three state variables. doing_pdma tells our inline low-level
* assembly floppy interrupt entry point whether it should sit and eat
* bytes from the fifo or just transfer control up to the higher level
* floppy interrupt c-code. I tried very hard but I could not get the
* pseudo-dma to work in c-code without getting many overruns and
* underruns. If non-zero, doing_pdma encodes the direction of
* the transfer for debugging. 1=read 2=write
*/
char *pdma_vaddr;
unsigned long pdma_size;
volatile int doing_pdma = 0;
/* This is software state */
char *pdma_base = NULL;
unsigned long pdma_areasize;
/* Common routines to all controller types on the Sparc. */
static __inline__ void virtual_dma_init(void)
{
/* nothing... */
}
static __inline__ void sun_fd_disable_dma(void)
{
doing_pdma = 0;
if (pdma_base) {
mmu_unlockarea(pdma_base, pdma_areasize);
pdma_base = 0;
}
}
static __inline__ void sun_fd_set_dma_mode(int mode)
{
switch(mode) {
case DMA_MODE_READ:
doing_pdma = 1;
break;
case DMA_MODE_WRITE:
doing_pdma = 2;
break;
default:
printk("Unknown dma mode %d\n", mode);
panic("floppy: Giving up...");
}
}
static __inline__ void sun_fd_set_dma_addr(char *buffer)
{
pdma_vaddr = buffer;
}
static __inline__ void sun_fd_set_dma_count(int length)
{
pdma_size = length;
}
static __inline__ void sun_fd_enable_dma(void)
{
pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
pdma_base = pdma_vaddr;
pdma_areasize = pdma_size;
}
/* Our low-level entry point in arch/sparc/kernel/entry.S */
irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs);
static int sun_fd_request_irq(void)
{
static int once = 0;
int error;
if(!once) {
once = 1;
error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, SA_INTERRUPT, "floppy");
return ((error == 0) ? 0 : -1);
} else return 0;
}
static struct linux_prom_registers fd_regs[2];
static int sun_floppy_init(void)
{
char state[128];
int tnode, fd_node, num_regs;
struct resource r;
use_virtual_dma = 1;
FLOPPY_IRQ = 11;
/* Forget it if we aren't on a machine that could possibly
* ever have a floppy drive.
*/
if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
(idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
/* We certainly don't have a floppy controller. */
goto no_sun_fdc;
}
/* Well, try to find one. */
tnode = prom_getchild(prom_root_node);
fd_node = prom_searchsiblings(tnode, "obio");
if(fd_node != 0) {
tnode = prom_getchild(fd_node);
fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
} else {
fd_node = prom_searchsiblings(tnode, "fd");
}
if(fd_node == 0) {
goto no_sun_fdc;
}
/* The sun4m lets us know if the controller is actually usable. */
if(sparc_cpu_model == sun4m &&
prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
if(!strcmp(state, "disabled")) {
goto no_sun_fdc;
}
}
num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
num_regs = (num_regs / sizeof(fd_regs[0]));
prom_apply_obio_ranges(fd_regs, num_regs);
memset(&r, 0, sizeof(r));
r.flags = fd_regs[0].which_io;
r.start = fd_regs[0].phys_addr;
sun_fdc = (struct sun_flpy_controller *)
sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
/* Last minute sanity check... */
if(sun_fdc->status_82072 == 0xff) {
sun_fdc = NULL;
goto no_sun_fdc;
}
if(sparc_cpu_model == sun4c) {
sun_fdops.fd_inb = sun_82072_fd_inb;
sun_fdops.fd_outb = sun_82072_fd_outb;
fdc_status = &sun_fdc->status_82072;
/* printk("AUXIO @0x%lx\n", auxio_register); */ /* P3 */
} else {
sun_fdops.fd_inb = sun_82077_fd_inb;
sun_fdops.fd_outb = sun_82077_fd_outb;
fdc_status = &sun_fdc->status_82077;
/* printk("DOR @0x%p\n", &sun_fdc->dor_82077); */ /* P3 */
}
/* Success... */
allowed_drive_mask = 0x01;
return (int) sun_fdc;
no_sun_fdc:
return -1;
}
static int sparc_eject(void)
{
set_dor(0x00, 0xff, 0x90);
udelay(500);
set_dor(0x00, 0x6f, 0x00);
udelay(500);
return 0;
}
#define fd_eject(drive) sparc_eject()
#define EXTRA_FLOPPY_PARAMS
#endif /* !(__ASM_SPARC_FLOPPY_H) */

24
include/asm-sparc/hardirq.h Normal file
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/* hardirq.h: 32-bit Sparc hard IRQ support.
*
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
*/
#ifndef __SPARC_HARDIRQ_H
#define __SPARC_HARDIRQ_H
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/spinlock.h>
#include <linux/cache.h>
/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#define HARDIRQ_BITS 8
#endif /* __SPARC_HARDIRQ_H */

1
include/asm-sparc/hdreg.h Normal file
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#include <asm-generic/hdreg.h>

125
include/asm-sparc/head.h Normal file
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/* $Id: head.h,v 1.39 2000/05/26 22:18:45 ecd Exp $ */
#ifndef __SPARC_HEAD_H
#define __SPARC_HEAD_H
#define KERNBASE 0xf0000000 /* First address the kernel will eventually be */
#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
#define SUN4C_SEGSZ (1 << 18)
#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */
#define INTS_ENAB 0x01 /* entry.S uses this. */
#define SUN4_PROM_VECTOR 0xFFE81000 /* SUN4 PROM needs to be hardwired */
#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
#define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */
/* Here are some trap goodies */
/* Generic trap entry. */
#define TRAP_ENTRY(type, label) \
rd %psr, %l0; b label; rd %wim, %l3; nop;
/* Data/text faults. Defaults to sun4c version at boot time. */
#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
/* This is for traps we should NEVER get. */
#define BAD_TRAP(num) \
rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
/* This is for traps when we want just skip the instruction which caused it */
#define SKIP_TRAP(type, name) \
jmpl %l2, %g0; rett %l2 + 4; nop; nop;
/* Notice that for the system calls we pull a trick. We load up a
* different pointer to the system call vector table in %l7, but call
* the same generic system call low-level entry point. The trap table
* entry sequences are also HyperSparc pipeline friendly ;-)
*/
/* Software trap for Linux system calls. */
#define LINUX_SYSCALL_TRAP \
sethi %hi(sys_call_table), %l7; \
or %l7, %lo(sys_call_table), %l7; \
b linux_sparc_syscall; \
rd %psr, %l0;
/* Software trap for SunOS4.1.x system calls. */
#define SUNOS_SYSCALL_TRAP \
rd %psr, %l0; \
sethi %hi(sunos_sys_table), %l7; \
b linux_sparc_syscall; \
or %l7, %lo(sunos_sys_table), %l7;
#define SUNOS_NO_SYSCALL_TRAP \
b sunos_syscall; \
rd %psr, %l0; \
nop; \
nop;
/* Software trap for Slowaris system calls. */
#define SOLARIS_SYSCALL_TRAP \
b solaris_syscall; \
rd %psr, %l0; \
nop; \
nop;
#define INDIRECT_SOLARIS_SYSCALL(x) \
mov x, %g1; \
b solaris_syscall; \
rd %psr, %l0; \
nop;
#define BREAKPOINT_TRAP \
b breakpoint_trap; \
rd %psr,%l0; \
nop; \
nop;
/* Software trap for Sparc-netbsd system calls. */
#define NETBSD_SYSCALL_TRAP \
sethi %hi(sys_call_table), %l7; \
or %l7, %lo(sys_call_table), %l7; \
b bsd_syscall; \
rd %psr, %l0;
/* The Get Condition Codes software trap for userland. */
#define GETCC_TRAP \
b getcc_trap_handler; mov %psr, %l0; nop; nop;
/* The Set Condition Codes software trap for userland. */
#define SETCC_TRAP \
b setcc_trap_handler; mov %psr, %l0; nop; nop;
/* The Get PSR software trap for userland. */
#define GETPSR_TRAP \
mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
/* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
* gets handled with another macro.
*/
#define TRAP_ENTRY_INTERRUPT(int_level) \
mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
/* NMI's (Non Maskable Interrupts) are special, you can't keep them
* from coming in, and basically if you get one, the shows over. ;(
* On the sun4c they are usually asynchronous memory errors, on the
* the sun4m they could be either due to mem errors or a software
* initiated interrupt from the prom/kern on an SMP box saying "I
* command you to do CPU tricks, read your mailbox for more info."
*/
#define NMI_TRAP \
rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
/* Window overflows/underflows are special and we need to try to be as
* efficient as possible here....
*/
#define WINDOW_SPILL \
rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
#define WINDOW_FILL \
rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
#endif /* __SPARC_HEAD_H */

81
include/asm-sparc/highmem.h Normal file
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/*
* highmem.h: virtual kernel memory mappings for high memory
*
* Used in CONFIG_HIGHMEM systems for memory pages which
* are not addressable by direct kernel virtual addresses.
*
* Copyright (C) 1999 Gerhard Wichert, Siemens AG
* Gerhard.Wichert@pdb.siemens.de
*
*
* Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terrabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/interrupt.h>
#include <asm/fixmap.h>
#include <asm/vaddrs.h>
#include <asm/kmap_types.h>
#include <asm/pgtable.h>
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;
extern pte_t *kmap_pte;
extern pgprot_t kmap_prot;
extern pte_t *pkmap_page_table;
extern void kmap_init(void) __init;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM. Currently the simplest way to do this is to align the
* pkmap region on a pagetable boundary (4MB).
*/
#define LAST_PKMAP 1024
#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
#define PKMAP_BASE PMD_ALIGN(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
#define PKMAP_END (PKMAP_ADDR(LAST_PKMAP))
extern void *kmap_high(struct page *page);
extern void kunmap_high(struct page *page);
static inline void *kmap(struct page *page)
{
BUG_ON(in_interrupt());
if (!PageHighMem(page))
return page_address(page);
return kmap_high(page);
}
static inline void kunmap(struct page *page)
{
BUG_ON(in_interrupt());
if (!PageHighMem(page))
return;
kunmap_high(page);
}
extern void *kmap_atomic(struct page *page, enum km_type type);
extern void kunmap_atomic(void *kvaddr, enum km_type type);
extern struct page *kmap_atomic_to_page(void *vaddr);
#define flush_cache_kmaps() flush_cache_all()
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */

6
include/asm-sparc/hw_irq.h Normal file
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#ifndef __ASM_SPARC_HW_IRQ_H
#define __ASM_SPARC_HW_IRQ_H
/* Dummy include. */
#endif

100
include/asm-sparc/ide.h Normal file
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/* $Id: ide.h,v 1.7 2002/01/16 20:58:40 davem Exp $
* ide.h: SPARC PCI specific IDE glue.
*
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
* Adaptation from sparc64 version to sparc by Pete Zaitcev.
*/
#ifndef _SPARC_IDE_H
#define _SPARC_IDE_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/psr.h>
#undef MAX_HWIFS
#define MAX_HWIFS 2
#define IDE_ARCH_OBSOLETE_INIT
#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
#define __ide_insl(data_reg, buffer, wcount) \
__ide_insw(data_reg, buffer, (wcount)<<1)
#define __ide_outsl(data_reg, buffer, wcount) \
__ide_outsw(data_reg, buffer, (wcount)<<1)
/* On sparc, I/O ports and MMIO registers are accessed identically. */
#define __ide_mm_insw __ide_insw
#define __ide_mm_insl __ide_insl
#define __ide_mm_outsw __ide_outsw
#define __ide_mm_outsl __ide_outsl
static __inline__ void __ide_insw(unsigned long port,
void *dst,
unsigned long count)
{
volatile unsigned short *data_port;
/* unsigned long end = (unsigned long)dst + (count << 1); */ /* P3 */
u16 *ps = dst;
u32 *pi;
data_port = (volatile unsigned short *)port;
if(((unsigned long)ps) & 0x2) {
*ps++ = *data_port;
count--;
}
pi = (u32 *)ps;
while(count >= 2) {
u32 w;
w = (*data_port) << 16;
w |= (*data_port);
*pi++ = w;
count -= 2;
}
ps = (u16 *)pi;
if(count)
*ps++ = *data_port;
/* __flush_dcache_range((unsigned long)dst, end); */ /* P3 see hme */
}
static __inline__ void __ide_outsw(unsigned long port,
const void *src,
unsigned long count)
{
volatile unsigned short *data_port;
/* unsigned long end = (unsigned long)src + (count << 1); */
const u16 *ps = src;
const u32 *pi;
data_port = (volatile unsigned short *)port;
if(((unsigned long)src) & 0x2) {
*data_port = *ps++;
count--;
}
pi = (const u32 *)ps;
while(count >= 2) {
u32 w;
w = *pi++;
*data_port = (w >> 16);
*data_port = w;
count -= 2;
}
ps = (const u16 *)pi;
if(count)
*data_port = *ps;
/* __flush_dcache_range((unsigned long)src, end); */ /* P3 see hme */
}
#endif /* __KERNEL__ */
#endif /* _SPARC_IDE_H */

33
include/asm-sparc/idprom.h Normal file
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/* $Id: idprom.h,v 1.6 1996/08/04 10:35:07 ecd Exp $
* idprom.h: Macros and defines for idprom routines
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_IDPROM_H
#define _SPARC_IDPROM_H
/* Offset into the EEPROM where the id PROM is located on the 4c */
#define IDPROM_OFFSET 0x7d8
/* On sun4m; physical. */
/* MicroSPARC(-II) does not decode 31rd bit, but it works. */
#define IDPROM_OFFSET_M 0xfd8
struct idprom
{
unsigned char id_format; /* Format identifier (always 0x01) */
unsigned char id_machtype; /* Machine type */
unsigned char id_ethaddr[6]; /* Hardware ethernet address */
long id_date; /* Date of manufacture */
unsigned int id_sernum:24; /* Unique serial number */
unsigned char id_cksum; /* Checksum - xor of the data bytes */
unsigned char reserved[16];
};
extern struct idprom *idprom;
extern void idprom_init(void);
#define IDPROM_SIZE (sizeof(struct idprom))
#endif /* !(_SPARC_IDPROM_H) */

62
include/asm-sparc/io-unit.h Normal file
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/* io-unit.h: Definitions for the sun4d IO-UNIT.
*
* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
*/
#ifndef _SPARC_IO_UNIT_H
#define _SPARC_IO_UNIT_H
#include <linux/spinlock.h>
#include <asm/page.h>
#include <asm/pgtable.h>
/* The io-unit handles all virtual to physical address translations
* that occur between the SBUS and physical memory. Access by
* the cpu to IO registers and similar go over the xdbus so are
* translated by the on chip SRMMU. The io-unit and the srmmu do
* not need to have the same translations at all, in fact most
* of the time the translations they handle are a disjunct set.
* Basically the io-unit handles all dvma sbus activity.
*/
/* AIEEE, unlike the nice sun4m, these monsters have
fixed DMA range 64M */
#define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */
#define IOUNIT_DMA_SIZE 0x04000000 /* 64M */
/* We use last 1M for sparc_dvma_malloc */
#define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */
/* The format of an iopte in the external page tables */
#define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
#define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */
/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
* XXX Actually, all you should need to do is find out where the registers
* XXX are and copy over the sparc64 implementation I wrote. There may be
* XXX some horrible hwbugs though, so be careful. -DaveM
*/
#define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */
#define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */
#define IOUPTE_WRITE 0x00000004 /* Writeable */
#define IOUPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */
struct iounit_struct {
unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
spinlock_t lock;
iopte_t *page_table;
unsigned long rotor[3];
unsigned long limit[4];
};
#define IOUNIT_BMAP1_START 0x00000000
#define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
#define IOUNIT_BMAP2_START IOUNIT_BMAP1_END
#define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
#endif /* !(_SPARC_IO_UNIT_H) */

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/*
* $Id: io.h,v 1.30 2001/12/21 01:23:21 davem Exp $
*/
#ifndef __SPARC_IO_H
#define __SPARC_IO_H
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h> /* struct resource */
#include <asm/page.h> /* IO address mapping routines need this */
#include <asm/system.h>
#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT)
static inline u32 flip_dword (u32 l)
{
return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
}
static inline u16 flip_word (u16 w)
{
return ((w&0xff) << 8) | ((w>>8)&0xff);
}
#define mmiowb()
/*
* Memory mapped I/O to PCI
*/
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
return *(__force volatile u8 *)addr;
}
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
return *(__force volatile u16 *)addr;
}
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
return *(__force volatile u32 *)addr;
}
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
*(__force volatile u8 *)addr = b;
}
static inline void __raw_writew(u16 w, volatile void __iomem *addr)
{
*(__force volatile u16 *)addr = w;
}
static inline void __raw_writel(u32 l, volatile void __iomem *addr)
{
*(__force volatile u32 *)addr = l;
}
static inline u8 __readb(const volatile void __iomem *addr)
{
return *(__force volatile u8 *)addr;
}
static inline u16 __readw(const volatile void __iomem *addr)
{
return flip_word(*(__force volatile u16 *)addr);
}
static inline u32 __readl(const volatile void __iomem *addr)
{
return flip_dword(*(__force volatile u32 *)addr);
}
static inline void __writeb(u8 b, volatile void __iomem *addr)
{
*(__force volatile u8 *)addr = b;
}
static inline void __writew(u16 w, volatile void __iomem *addr)
{
*(__force volatile u16 *)addr = flip_word(w);
}
static inline void __writel(u32 l, volatile void __iomem *addr)
{
*(__force volatile u32 *)addr = flip_dword(l);
}
#define readb(__addr) __readb(__addr)
#define readw(__addr) __readw(__addr)
#define readl(__addr) __readl(__addr)
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define writeb(__b, __addr) __writeb((__b),(__addr))
#define writew(__w, __addr) __writew((__w),(__addr))
#define writel(__l, __addr) __writel((__l),(__addr))
/*
* I/O space operations
*
* Arrangement on a Sun is somewhat complicated.
*
* First of all, we want to use standard Linux drivers
* for keyboard, PC serial, etc. These drivers think
* they access I/O space and use inb/outb.
* On the other hand, EBus bridge accepts PCI *memory*
* cycles and converts them into ISA *I/O* cycles.
* Ergo, we want inb & outb to generate PCI memory cycles.
*
* If we want to issue PCI *I/O* cycles, we do this
* with a low 64K fixed window in PCIC. This window gets
* mapped somewhere into virtual kernel space and we
* can use inb/outb again.
*/
#define inb_local(__addr) __readb((void __iomem *)(unsigned long)(__addr))
#define inb(__addr) __readb((void __iomem *)(unsigned long)(__addr))
#define inw(__addr) __readw((void __iomem *)(unsigned long)(__addr))
#define inl(__addr) __readl((void __iomem *)(unsigned long)(__addr))
#define outb_local(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
#define outb(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
#define outw(__w, __addr) __writew(__w, (void __iomem *)(unsigned long)(__addr))
#define outl(__l, __addr) __writel(__l, (void __iomem *)(unsigned long)(__addr))
#define inb_p(__addr) inb(__addr)
#define outb_p(__b, __addr) outb(__b, __addr)
#define inw_p(__addr) inw(__addr)
#define outw_p(__w, __addr) outw(__w, __addr)
#define inl_p(__addr) inl(__addr)
#define outl_p(__l, __addr) outl(__l, __addr)
void outsb(unsigned long addr, const void *src, unsigned long cnt);
void outsw(unsigned long addr, const void *src, unsigned long cnt);
void outsl(unsigned long addr, const void *src, unsigned long cnt);
void insb(unsigned long addr, void *dst, unsigned long count);
void insw(unsigned long addr, void *dst, unsigned long count);
void insl(unsigned long addr, void *dst, unsigned long count);
#define IO_SPACE_LIMIT 0xffffffff
/*
* SBus accessors.
*
* SBus has only one, memory mapped, I/O space.
* We do not need to flip bytes for SBus of course.
*/
static inline u8 _sbus_readb(const volatile void __iomem *addr)
{
return *(__force volatile u8 *)addr;
}
static inline u16 _sbus_readw(const volatile void __iomem *addr)
{
return *(__force volatile u16 *)addr;
}
static inline u32 _sbus_readl(const volatile void __iomem *addr)
{
return *(__force volatile u32 *)addr;
}
static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{
*(__force volatile u8 *)addr = b;
}
static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{
*(__force volatile u16 *)addr = w;
}
static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{
*(__force volatile u32 *)addr = l;
}
/*
* The only reason for #define's is to hide casts to unsigned long.
*/
#define sbus_readb(__addr) _sbus_readb(__addr)
#define sbus_readw(__addr) _sbus_readw(__addr)
#define sbus_readl(__addr) _sbus_readl(__addr)
#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
static inline void sbus_memset_io(volatile void __iomem *__dst, int c, __kernel_size_t n)
{
while(n--) {
sbus_writeb(c, __dst);
__dst++;
}
}
static inline void
_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
volatile void __iomem *d = dst;
while (n--) {
writeb(c, d);
d++;
}
}
#define memset_io(d,c,sz) _memset_io(d,c,sz)
static inline void
_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
{
char *d = dst;
while (n--) {
char tmp = readb(src);
*d++ = tmp;
src++;
}
}
#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
static inline void
_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
{
const char *s = src;
volatile void __iomem *d = dst;
while (n--) {
char tmp = *s++;
writeb(tmp, d);
d++;
}
}
#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
#ifdef __KERNEL__
/*
* Bus number may be embedded in the higher bits of the physical address.
* This is why we have no bus number argument to ioremap().
*/
extern void __iomem *ioremap(unsigned long offset, unsigned long size);
#define ioremap_nocache(X,Y) ioremap((X),(Y))
extern void iounmap(volatile void __iomem *addr);
/*
* Bus number may be in res->flags... somewhere.
*/
extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
unsigned long size, char *name);
extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
/*
* At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
* so rtc_port is static in it. This should not change unless a new
* hardware pops up.
*/
#define RTC_PORT(x) (rtc_port + (x))
#define RTC_ALWAYS_BCD 0
/* Nothing to do */
/* P3: Only IDE DMA may need these. XXX Verify that it still does... */
#define dma_cache_inv(_start,_size) do { } while (0)
#define dma_cache_wback(_start,_size) do { } while (0)
#define dma_cache_wback_inv(_start,_size) do { } while (0)
#endif
#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#endif /* !(__SPARC_IO_H) */

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/* $Id: ioctl.h,v 1.6 1999/12/01 23:58:36 davem Exp $ */
#ifndef _SPARC_IOCTL_H
#define _SPARC_IOCTL_H
/*
* Our DIR and SIZE overlap in order to simulteneously provide
* a non-zero _IOC_NONE (for binary compatibility) and
* 14 bits of size as on i386. Here's the layout:
*
* 0xE0000000 DIR
* 0x80000000 DIR = WRITE
* 0x40000000 DIR = READ
* 0x20000000 DIR = NONE
* 0x3FFF0000 SIZE (overlaps NONE bit)
* 0x0000FF00 TYPE
* 0x000000FF NR (CMD)
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 13 /* Actually 14, see below. */
#define _IOC_DIRBITS 3
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_XSIZEMASK ((1 << (_IOC_SIZEBITS+1))-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT + _IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT + _IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT + _IOC_SIZEBITS)
#define _IOC_NONE 1U
#define _IOC_READ 2U
#define _IOC_WRITE 4U
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* Used to decode ioctl numbers in drivers despite the leading underscore... */
#define _IOC_DIR(nr) \
( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)? \
(((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)): \
(((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) \
((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)? \
0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
/* ...and for the PCMCIA and sound. */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif /* !(_SPARC_IOCTL_H) */

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#ifndef _ASM_SPARC_IOCTLS_H
#define _ASM_SPARC_IOCTLS_H
#include <asm/ioctl.h>
/* Big T */
#define TCGETA _IOR('T', 1, struct termio)
#define TCSETA _IOW('T', 2, struct termio)
#define TCSETAW _IOW('T', 3, struct termio)
#define TCSETAF _IOW('T', 4, struct termio)
#define TCSBRK _IO('T', 5)
#define TCXONC _IO('T', 6)
#define TCFLSH _IO('T', 7)
#define TCGETS _IOR('T', 8, struct termios)
#define TCSETS _IOW('T', 9, struct termios)
#define TCSETSW _IOW('T', 10, struct termios)
#define TCSETSF _IOW('T', 11, struct termios)
/* Note that all the ioctls that are not available in Linux have a
* double underscore on the front to: a) avoid some programs to
* thing we support some ioctls under Linux (autoconfiguration stuff)
*/
/* Little t */
#define TIOCGETD _IOR('t', 0, int)
#define TIOCSETD _IOW('t', 1, int)
#define __TIOCHPCL _IO('t', 2) /* SunOS Specific */
#define __TIOCMODG _IOR('t', 3, int) /* SunOS Specific */
#define __TIOCMODS _IOW('t', 4, int) /* SunOS Specific */
#define __TIOCGETP _IOR('t', 8, struct sgttyb) /* SunOS Specific */
#define __TIOCSETP _IOW('t', 9, struct sgttyb) /* SunOS Specific */
#define __TIOCSETN _IOW('t', 10, struct sgttyb) /* SunOS Specific */
#define TIOCEXCL _IO('t', 13)
#define TIOCNXCL _IO('t', 14)
#define __TIOCFLUSH _IOW('t', 16, int) /* SunOS Specific */
#define __TIOCSETC _IOW('t', 17, struct tchars) /* SunOS Specific */
#define __TIOCGETC _IOR('t', 18, struct tchars) /* SunOS Specific */
#define __TIOCTCNTL _IOW('t', 32, int) /* SunOS Specific */
#define __TIOCSIGNAL _IOW('t', 33, int) /* SunOS Specific */
#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
#define TIOCCONS _IO('t', 36)
#define __TIOCSSIZE _IOW('t', 37, struct sunos_ttysize) /* SunOS Specific */
#define __TIOCGSIZE _IOR('t', 38, struct sunos_ttysize) /* SunOS Specific */
#define TIOCGSOFTCAR _IOR('t', 100, int)
#define TIOCSSOFTCAR _IOW('t', 101, int)
#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
#define __TIOCREMOTE _IOW('t', 105, int) /* SunOS Specific */
#define TIOCMGET _IOR('t', 106, int)
#define TIOCMBIC _IOW('t', 107, int)
#define TIOCMBIS _IOW('t', 108, int)
#define TIOCMSET _IOW('t', 109, int)
#define TIOCSTART _IO('t', 110)
#define TIOCSTOP _IO('t', 111)
#define TIOCPKT _IOW('t', 112, int)
#define TIOCNOTTY _IO('t', 113)
#define TIOCSTI _IOW('t', 114, char)
#define TIOCOUTQ _IOR('t', 115, int)
#define __TIOCGLTC _IOR('t', 116, struct ltchars) /* SunOS Specific */
#define __TIOCSLTC _IOW('t', 117, struct ltchars) /* SunOS Specific */
/* 118 is the non-posix setpgrp tty ioctl */
/* 119 is the non-posix getpgrp tty ioctl */
#define __TIOCCDTR _IO('t', 120) /* SunOS Specific */
#define __TIOCSDTR _IO('t', 121) /* SunOS Specific */
#define TIOCCBRK _IO('t', 122)
#define TIOCSBRK _IO('t', 123)
#define __TIOCLGET _IOW('t', 124, int) /* SunOS Specific */
#define __TIOCLSET _IOW('t', 125, int) /* SunOS Specific */
#define __TIOCLBIC _IOW('t', 126, int) /* SunOS Specific */
#define __TIOCLBIS _IOW('t', 127, int) /* SunOS Specific */
#define __TIOCISPACE _IOR('t', 128, int) /* SunOS Specific */
#define __TIOCISIZE _IOR('t', 129, int) /* SunOS Specific */
#define TIOCSPGRP _IOW('t', 130, int)
#define TIOCGPGRP _IOR('t', 131, int)
#define TIOCSCTTY _IO('t', 132)
#define TIOCGSID _IOR('t', 133, int)
/* Get minor device of a pty master's FD -- Solaris equiv is ISPTM */
#define TIOCGPTN _IOR('t', 134, unsigned int) /* Get Pty Number */
#define TIOCSPTLCK _IOW('t', 135, int) /* Lock/unlock PTY */
/* Little f */
#define FIOCLEX _IO('f', 1)
#define FIONCLEX _IO('f', 2)
#define FIOASYNC _IOW('f', 125, int)
#define FIONBIO _IOW('f', 126, int)
#define FIONREAD _IOR('f', 127, int)
#define TIOCINQ FIONREAD
#define FIOQSIZE _IOR('f', 128, loff_t)
/* SCARY Rutgers local SunOS kernel hackery, perhaps I will support it
* someday. This is completely bogus, I know...
*/
#define __TCGETSTAT _IO('T', 200) /* Rutgers specific */
#define __TCSETSTAT _IO('T', 201) /* Rutgers specific */
/* Linux specific, no SunOS equivalent. */
#define TIOCLINUX 0x541C
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TCSBRKP 0x5425
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
#define TIOCSERGETLSR 0x5459 /* Get line status register */
#define TIOCSERGETMULTI 0x545A /* Get multiport config */
#define TIOCSERSETMULTI 0x545B /* Set multiport config */
#define TIOCMIWAIT 0x545C /* Wait input */
#define TIOCGICOUNT 0x545D /* Read serial port inline interrupt counts */
/* Kernel definitions */
#ifdef __KERNEL__
#define TIOCGETC __TIOCGETC
#define TIOCGETP __TIOCGETP
#define TIOCGLTC __TIOCGLTC
#define TIOCSLTC __TIOCSLTC
#define TIOCSETP __TIOCSETP
#define TIOCSETN __TIOCSETN
#define TIOCSETC __TIOCSETC
#endif
/* Used for packet mode */
#define TIOCPKT_DATA 0
#define TIOCPKT_FLUSHREAD 1
#define TIOCPKT_FLUSHWRITE 2
#define TIOCPKT_STOP 4
#define TIOCPKT_START 8
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
#endif /* !(_ASM_SPARC_IOCTLS_H) */

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/* iommu.h: Definitions for the sun4m IOMMU.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_IOMMU_H
#define _SPARC_IOMMU_H
#include <asm/page.h>
#include <asm/bitext.h>
/* The iommu handles all virtual to physical address translations
* that occur between the SBUS and physical memory. Access by
* the cpu to IO registers and similar go over the mbus so are
* translated by the on chip SRMMU. The iommu and the srmmu do
* not need to have the same translations at all, in fact most
* of the time the translations they handle are a disjunct set.
* Basically the iommu handles all dvma sbus activity.
*/
/* The IOMMU registers occupy three pages in IO space. */
struct iommu_regs {
/* First page */
volatile unsigned long control; /* IOMMU control */
volatile unsigned long base; /* Physical base of iopte page table */
volatile unsigned long _unused1[3];
volatile unsigned long tlbflush; /* write only */
volatile unsigned long pageflush; /* write only */
volatile unsigned long _unused2[1017];
/* Second page */
volatile unsigned long afsr; /* Async-fault status register */
volatile unsigned long afar; /* Async-fault physical address */
volatile unsigned long _unused3[2];
volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
volatile unsigned long sbuscfg1;
volatile unsigned long sbuscfg2;
volatile unsigned long sbuscfg3;
volatile unsigned long mfsr; /* Memory-fault status register */
volatile unsigned long mfar; /* Memory-fault physical address */
volatile unsigned long _unused4[1014];
/* Third page */
volatile unsigned long mid; /* IOMMU module-id */
};
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
produced by this device as pure
physical. */
#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
on the even word of the access, low bit
indicated odd word caused the parity error */
#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
/* The format of an iopte in the page tables */
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
struct iommu_struct {
struct iommu_regs *regs;
iopte_t *page_table;
/* For convenience */
unsigned long start; /* First managed virtual address */
unsigned long end; /* Last managed virtual address */
struct bit_map usemap;
};
extern __inline__ void iommu_invalidate(struct iommu_regs *regs)
{
regs->tlbflush = 0;
}
extern __inline__ void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
{
regs->pageflush = (ba & PAGE_MASK);
}
#endif /* !(_SPARC_IOMMU_H) */

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#include <asm-generic/ipc.h>

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include/asm-sparc/ipcbuf.h Normal file
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#ifndef _SPARC_IPCBUF_H
#define _SPARC_IPCBUF_H
/*
* The ipc64_perm structure for sparc architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 32-bit mode
* - 32-bit seq
* - 2 miscellaneous 64-bit values (so that this structure matches
* sparc64 ipc64_perm)
*/
struct ipc64_perm
{
__kernel_key_t key;
__kernel_uid32_t uid;
__kernel_gid32_t gid;
__kernel_uid32_t cuid;
__kernel_gid32_t cgid;
unsigned short __pad1;
__kernel_mode_t mode;
unsigned short __pad2;
unsigned short seq;
unsigned long long __unused1;
unsigned long long __unused2;
};
#endif /* _SPARC_IPCBUF_H */

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/* $Id: irq.h,v 1.32 2000/08/26 02:42:28 anton Exp $
* irq.h: IRQ registers on the Sparc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_IRQ_H
#define _SPARC_IRQ_H
#include <linux/config.h>
#include <linux/linkage.h>
#include <linux/threads.h> /* For NR_CPUS */
#include <linux/interrupt.h>
#include <asm/system.h> /* For SUN4M_NCPUS */
#include <asm/btfixup.h>
#define __irq_ino(irq) irq
#define __irq_pil(irq) irq
BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
#define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
#define NR_IRQS 16
#define irq_canonicalize(irq) (irq)
/* Dave Redman (djhr@tadpole.co.uk)
* changed these to function pointers.. it saves cycles and will allow
* the irq dependencies to be split into different files at a later date
* sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
* Jakub Jelinek (jj@sunsite.mff.cuni.cz)
* Changed these to btfixup entities... It saves cycles :)
*/
BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
BTFIXUPDEF_CALL(void, clear_clock_irq, void)
BTFIXUPDEF_CALL(void, clear_profile_irq, int)
BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
static inline void disable_irq_nosync(unsigned int irq)
{
BTFIXUP_CALL(disable_irq)(irq);
}
static inline void disable_irq(unsigned int irq)
{
BTFIXUP_CALL(disable_irq)(irq);
}
static inline void enable_irq(unsigned int irq)
{
BTFIXUP_CALL(enable_irq)(irq);
}
static inline void disable_pil_irq(unsigned int irq)
{
BTFIXUP_CALL(disable_pil_irq)(irq);
}
static inline void enable_pil_irq(unsigned int irq)
{
BTFIXUP_CALL(enable_pil_irq)(irq);
}
static inline void clear_clock_irq(void)
{
BTFIXUP_CALL(clear_clock_irq)();
}
static inline void clear_profile_irq(int irq)
{
BTFIXUP_CALL(clear_profile_irq)(irq);
}
static inline void load_profile_irq(int cpu, int limit)
{
BTFIXUP_CALL(load_profile_irq)(cpu, limit);
}
extern void (*sparc_init_timers)(irqreturn_t (*lvl10_irq)(int, void *, struct pt_regs *));
extern void claim_ticker14(irqreturn_t (*irq_handler)(int, void *, struct pt_regs *),
int irq,
unsigned int timeout);
#ifdef CONFIG_SMP
BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
BTFIXUPDEF_CALL(void, set_irq_udt, int)
#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
#endif
extern int request_fast_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
/* On the sun4m, just like the timers, we have both per-cpu and master
* interrupt registers.
*/
/* These registers are used for sending/receiving irqs from/to
* different cpu's.
*/
struct sun4m_intreg_percpu {
unsigned int tbt; /* Interrupts still pending for this cpu. */
/* These next two registers are WRITE-ONLY and are only
* "on bit" sensitive, "off bits" written have NO affect.
*/
unsigned int clear; /* Clear this cpus irqs here. */
unsigned int set; /* Set this cpus irqs here. */
unsigned char space[PAGE_SIZE - 12];
};
/*
* djhr
* Actually the clear and set fields in this struct are misleading..
* according to the SLAVIO manual (and the same applies for the SEC)
* the clear field clears bits in the mask which will ENABLE that IRQ
* the set field sets bits in the mask to DISABLE the IRQ.
*
* Also the undirected_xx address in the SLAVIO is defined as
* RESERVED and write only..
*
* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
* sun4m machines, for MP the layout makes more sense.
*/
struct sun4m_intregs {
struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
unsigned int tbt; /* IRQ's that are still pending. */
unsigned int irqs; /* Master IRQ bits. */
/* Again, like the above, two these registers are WRITE-ONLY. */
unsigned int clear; /* Clear master IRQ's by setting bits here. */
unsigned int set; /* Set master IRQ's by setting bits here. */
/* This register is both READ and WRITE. */
unsigned int undirected_target; /* Which cpu gets undirected irqs. */
};
extern struct sun4m_intregs *sun4m_interrupts;
/*
* Bit field defines for the interrupt registers on various
* Sparc machines.
*/
/* The sun4c interrupt register. */
#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
/* Dave Redman (djhr@tadpole.co.uk)
* The sun4m interrupt registers.
*/
#define SUN4M_INT_ENABLE 0x80000000
#define SUN4M_INT_E14 0x00000080
#define SUN4M_INT_E10 0x00080000
#define SUN4M_HARD_INT(x) (0x000000001 << (x))
#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
#define SUN4M_INT_SBUS(x) (1 << (x+7))
#define SUN4M_INT_VME(x) (1 << (x))
struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
#endif

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/*
* jsflash.h: OS Flash SIMM support for JavaStations.
*
* Copyright (C) 1999 Pete Zaitcev
*/
#ifndef _SPARC_JSFLASH_H
#define _SPARC_JSFLASH_H
#ifndef _SPARC_TYPES_H
#include <asm/types.h>
#endif
/*
* Semantics of the offset is a full address.
* Hardcode it or get it from probe ioctl.
*
* We use full bus address, so that we would be
* automatically compatible with possible future systems.
*/
#define JSFLASH_IDENT (('F'<<8)|54)
struct jsflash_ident_arg {
__u64 off; /* 0x20000000 is included */
__u32 size;
char name[32]; /* With trailing zero */
};
#define JSFLASH_ERASE (('F'<<8)|55)
/* Put 0 as argument, may be flags or sector number... */
#define JSFLASH_PROGRAM (('F'<<8)|56)
struct jsflash_program_arg {
__u64 data; /* char* for sparc and sparc64 */
__u64 off;
__u32 size;
};
#endif /* _SPARC_JSFLASH_H */

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#ifndef __LINUX_KBIO_H
#define __LINUX_KBIO_H
/* Return keyboard type */
#define KIOCTYPE _IOR('k', 9, int)
/* Return Keyboard layout */
#define KIOCLAYOUT _IOR('k', 20, int)
enum {
TR_NONE,
TR_ASCII, /* keyboard is in regular state */
TR_EVENT, /* keystrokes sent as firm events */
TR_UNTRANS_EVENT /* EVENT+up and down+no translation */
};
/* Return the current keyboard translation */
#define KIOCGTRANS _IOR('k', 5, int)
/* Set the keyboard translation */
#define KIOCTRANS _IOW('k', 0, int)
/* Send a keyboard command */
#define KIOCCMD _IOW('k', 8, int)
/* Return if keystrokes are being sent to /dev/kbd */
/* Set routing of keystrokes to /dev/kbd */
#define KIOCSDIRECT _IOW('k', 10, int)
/* Set keyboard leds */
#define KIOCSLED _IOW('k', 14, unsigned char)
/* Get keyboard leds */
#define KIOCGLED _IOR('k', 15, unsigned char)
/* Used by KIOC[GS]RATE */
struct kbd_rate {
unsigned char delay; /* Delay in Hz before first repeat. */
unsigned char rate; /* In characters per second (0..50). */
};
/* Set keyboard rate */
#define KIOCSRATE _IOW('k', 40, struct kbd_rate)
/* Get keyboard rate */
#define KIOCGRATE _IOW('k', 41, struct kbd_rate)
/* Top bit records if the key is up or down */
#define KBD_UP 0x80
/* Usable information */
#define KBD_KEYMASK 0x7f
/* All keys up */
#define KBD_IDLE 0x75
#endif /* __LINUX_KBIO_H */

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/* $Id: kdebug.h,v 1.11 2000/06/04 06:23:53 anton Exp $
* kdebug.h: Defines and definitions for debugging the Linux kernel
* under various kernel debuggers.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_KDEBUG_H
#define _SPARC_KDEBUG_H
#include <asm/openprom.h>
#include <asm/vaddrs.h>
/* Breakpoints are enter through trap table entry 126. So in sparc assembly
* if you want to drop into the debugger you do:
*
* t DEBUG_BP_TRAP
*/
#define DEBUG_BP_TRAP 126
#ifndef __ASSEMBLY__
/* The debug vector is passed in %o1 at boot time. It is a pointer to
* a structure in the debuggers address space. Here is its format.
*/
typedef unsigned int (*debugger_funct)(void);
struct kernel_debug {
/* First the entry point into the debugger. You jump here
* to give control over to the debugger.
*/
unsigned long kdebug_entry;
unsigned long kdebug_trapme; /* Figure out later... */
/* The following is the number of pages that the debugger has
* taken from to total pool.
*/
unsigned long *kdebug_stolen_pages;
/* Ok, after you remap yourself and/or change the trap table
* from what you were left with at boot time you have to call
* this synchronization function so the debugger can check out
* what you have done.
*/
debugger_funct teach_debugger;
}; /* I think that is it... */
extern struct kernel_debug *linux_dbvec;
/* Use this macro in C-code to enter the debugger. */
extern __inline__ void sp_enter_debugger(void)
{
__asm__ __volatile__("jmpl %0, %%o7\n\t"
"nop\n\t" : :
"r" (linux_dbvec) : "o7", "memory");
}
#define SP_ENTER_DEBUGGER do { \
if((linux_dbvec!=0) && ((*(short *)linux_dbvec)!=-1)) \
sp_enter_debugger(); \
} while(0)
#endif /* !(__ASSEMBLY__) */
/* Some nice offset defines for assembler code. */
#define KDEBUG_ENTRY_OFF 0x0
#define KDEBUG_DUNNO_OFF 0x4
#define KDEBUG_DUNNO2_OFF 0x8
#define KDEBUG_TEACH_OFF 0xc
#endif /* !(_SPARC_KDEBUG_H) */

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/* $Id: kgdb.h,v 1.8 1998/01/07 06:33:44 baccala Exp $
* kgdb.h: Defines and declarations for serial line source level
* remote debugging of the Linux kernel using gdb.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_KGDB_H
#define _SPARC_KGDB_H
#ifndef __ASSEMBLY__
/* To init the kgdb engine. */
extern void set_debug_traps(void);
/* To enter the debugger explicitly. */
extern void breakpoint(void);
/* For convenience we define the format of a kgdb trap breakpoint
* frame here also.
*/
struct kgdb_frame {
unsigned long globals[8];
unsigned long outs[8];
unsigned long locals[8];
unsigned long ins[8];
unsigned long fpregs[32];
unsigned long y;
unsigned long psr;
unsigned long wim;
unsigned long tbr;
unsigned long pc;
unsigned long npc;
unsigned long fpsr;
unsigned long cpsr;
};
#endif /* !(__ASSEMBLY__) */
/* Macros for assembly usage of the kgdb breakpoint frame. */
#define KGDB_G0 0x000
#define KGDB_G1 0x004
#define KGDB_G2 0x008
#define KGDB_G4 0x010
#define KGDB_G6 0x018
#define KGDB_I0 0x020
#define KGDB_I2 0x028
#define KGDB_I4 0x030
#define KGDB_I6 0x038
#define KGDB_Y 0x100
#define KGDB_PSR 0x104
#define KGDB_WIM 0x108
#define KGDB_TBR 0x10c
#define KGDB_PC 0x110
#define KGDB_NPC 0x114
#define SAVE_KGDB_GLOBALS(reg) \
std %g0, [%reg + STACKFRAME_SZ + KGDB_G0]; \
std %g2, [%reg + STACKFRAME_SZ + KGDB_G2]; \
std %g4, [%reg + STACKFRAME_SZ + KGDB_G4]; \
std %g6, [%reg + STACKFRAME_SZ + KGDB_G6];
#define SAVE_KGDB_INS(reg) \
std %i0, [%reg + STACKFRAME_SZ + KGDB_I0]; \
std %i2, [%reg + STACKFRAME_SZ + KGDB_I2]; \
std %i4, [%reg + STACKFRAME_SZ + KGDB_I4]; \
std %i6, [%reg + STACKFRAME_SZ + KGDB_I6];
#define SAVE_KGDB_SREGS(reg, reg_y, reg_psr, reg_wim, reg_tbr, reg_pc, reg_npc) \
st %reg_y, [%reg + STACKFRAME_SZ + KGDB_Y]; \
st %reg_psr, [%reg + STACKFRAME_SZ + KGDB_PSR]; \
st %reg_wim, [%reg + STACKFRAME_SZ + KGDB_WIM]; \
st %reg_tbr, [%reg + STACKFRAME_SZ + KGDB_TBR]; \
st %reg_pc, [%reg + STACKFRAME_SZ + KGDB_PC]; \
st %reg_npc, [%reg + STACKFRAME_SZ + KGDB_NPC];
#define LOAD_KGDB_GLOBALS(reg) \
ld [%reg + STACKFRAME_SZ + KGDB_G1], %g1; \
ldd [%reg + STACKFRAME_SZ + KGDB_G2], %g2; \
ldd [%reg + STACKFRAME_SZ + KGDB_G4], %g4; \
ldd [%reg + STACKFRAME_SZ + KGDB_G6], %g6;
#define LOAD_KGDB_INS(reg) \
ldd [%reg + STACKFRAME_SZ + KGDB_I0], %i0; \
ldd [%reg + STACKFRAME_SZ + KGDB_I2], %i2; \
ldd [%reg + STACKFRAME_SZ + KGDB_I4], %i4; \
ldd [%reg + STACKFRAME_SZ + KGDB_I6], %i6;
#define LOAD_KGDB_SREGS(reg, reg_y, reg_psr, reg_wim, reg_tbr, reg_pc, reg_npc) \
ld [%reg + STACKFRAME_SZ + KGDB_Y], %reg_y; \
ld [%reg + STACKFRAME_SZ + KGDB_PSR], %reg_psr; \
ld [%reg + STACKFRAME_SZ + KGDB_WIM], %reg_wim; \
ld [%reg + STACKFRAME_SZ + KGDB_TBR], %reg_tbr; \
ld [%reg + STACKFRAME_SZ + KGDB_PC], %reg_pc; \
ld [%reg + STACKFRAME_SZ + KGDB_NPC], %reg_npc;
#endif /* !(_SPARC_KGDB_H) */

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#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BIO_SRC_IRQ,
KM_BIO_DST_IRQ,
KM_PTE0,
KM_PTE1,
KM_IRQ0,
KM_IRQ1,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};
#endif

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#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
/* Nothing to see here... */
#endif

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#ifndef _SPARC_LOCAL_H
#define _SPARC_LOCAL_H
#include <asm-generic/local.h>
#endif

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/* $Id: machines.h,v 1.4 1995/11/25 02:31:58 davem Exp $
* machines.h: Defines for taking apart the machine type value in the
* idprom and determining the kind of machine we are on.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_MACHINES_H
#define _SPARC_MACHINES_H
struct Sun_Machine_Models {
char *name;
unsigned char id_machtype;
};
/* Current number of machines we know about that has an IDPROM
* machtype entry including one entry for the 0x80 OBP machines.
*/
#define NUM_SUN_MACHINES 15
extern struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES];
/* The machine type in the idprom area looks like this:
*
* ---------------
* | ARCH | MACH |
* ---------------
* 7 4 3 0
*
* The ARCH field determines the architecture line (sun4, sun4c, etc).
* The MACH field determines the machine make within that architecture.
*/
#define SM_ARCH_MASK 0xf0
#define SM_SUN4 0x20
#define SM_SUN4C 0x50
#define SM_SUN4M 0x70
#define SM_SUN4M_OBP 0x80
#define SM_TYP_MASK 0x0f
/* Sun4 machines */
#define SM_4_260 0x01 /* Sun 4/200 series */
#define SM_4_110 0x02 /* Sun 4/100 series */
#define SM_4_330 0x03 /* Sun 4/300 series */
#define SM_4_470 0x04 /* Sun 4/400 series */
/* Sun4c machines Full Name - PROM NAME */
#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
/* Sun4m machines, these predate the OpenBoot. These values only mean
* something if the value in the ARCH field is SM_SUN4M, if it is
* SM_SUN4M_OBP then you have the following situation:
* 1) You either have a sun4d, a sun4e, or a recently made sun4m.
* 2) You have to consult OpenBoot to determine which machine this is.
*/
#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
/* Sun4d machines -- N/A */
/* Sun4e machines -- N/A */
/* Sun4u machines -- N/A */
#endif /* !(_SPARC_MACHINES_H) */

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/* $Id: mbus.h,v 1.9 1997/06/24 15:48:12 jj Exp $
* mbus.h: Various defines for MBUS modules.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_MBUS_H
#define _SPARC_MBUS_H
#include <asm/ross.h> /* HyperSparc stuff */
#include <asm/cypress.h> /* Cypress Chips */
#include <asm/viking.h> /* Ugh, bug city... */
enum mbus_module {
HyperSparc = 0,
Cypress = 1,
Cypress_vE = 2,
Cypress_vD = 3,
Swift_ok = 4,
Swift_bad_c = 5,
Swift_lots_o_bugs = 6,
Tsunami = 7,
Viking_12 = 8,
Viking_2x = 9,
Viking_30 = 10,
Viking_35 = 11,
Viking_new = 12,
TurboSparc = 13,
SRMMU_INVAL_MOD = 14,
};
extern enum mbus_module srmmu_modtype;
extern unsigned int viking_rev, swift_rev, cypress_rev;
/* HW Mbus module bugs we have to deal with */
#define HWBUG_COPYBACK_BROKEN 0x00000001
#define HWBUG_ASIFLUSH_BROKEN 0x00000002
#define HWBUG_VACFLUSH_BITROT 0x00000004
#define HWBUG_KERN_ACCBROKEN 0x00000008
#define HWBUG_KERN_CBITBROKEN 0x00000010
#define HWBUG_MODIFIED_BITROT 0x00000020
#define HWBUG_PC_BADFAULT_ADDR 0x00000040
#define HWBUG_SUPERSCALAR_BAD 0x00000080
#define HWBUG_PACINIT_BITROT 0x00000100
extern unsigned int hwbug_bitmask;
/* First the module type values. To find out which you have, just load
* the mmu control register from ASI_M_MMUREG alternate address space and
* shift the value right 28 bits.
*/
/* IMPL field means the company which produced the chip. */
#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
#define MBUS_LSI 0x3 /* LSI Logics */
#define MBUS_ROSS 0x1 /* Ross is nice */
#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
/* Ross Module versions */
#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
#define ROSS_604_REV_F 0x1 /* revision f */
#define ROSS_605 0xf /* revision a, a.1, and a.2 */
#define ROSS_605_REV_B 0xe /* revision b */
/* TI Viking Module versions */
#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
#define VIKING_REV_30 0x3 /* Version 3.0 */
#define VIKING_REV_35 0x4 /* Version 3.5 */
/* LSI Logics. */
#define LSI_L64815 0x0
/* Fujitsu */
#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
#define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
/* For multiprocessor support we need to be able to obtain the CPU id and
* the MBUS Module id.
*/
/* The CPU ID is encoded in the trap base register, 20 bits to the left of
* bit zero, with 2 bits being significant.
*/
#define TBR_ID_SHIFT 20
extern __inline__ int get_cpuid(void)
{
register int retval;
__asm__ __volatile__("rd %%tbr, %0\n\t"
"srl %0, %1, %0\n\t" :
"=r" (retval) :
"i" (TBR_ID_SHIFT));
return (retval & 3);
}
extern __inline__ int get_modid(void)
{
return (get_cpuid() | 0x8);
}
#endif /* !(_SPARC_MBUS_H) */

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/*
* Machine dependent access functions for RTC registers.
*/
#ifndef __ASM_SPARC_MC146818RTC_H
#define __ASM_SPARC_MC146818RTC_H
#include <asm/io.h>
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
#endif
/*
* The yet supported machines all access the RTC index register via
* an ISA port access but the way to access the date register differs ...
*/
#define CMOS_READ(addr) ({ \
outb_p((addr),RTC_PORT(0)); \
inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
outb_p((addr),RTC_PORT(0)); \
outb_p((val),RTC_PORT(1)); \
})
#define RTC_IRQ 8
#endif /* __ASM_SPARC_MC146818RTC_H */

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/* $Id: memreg.h,v 1.8 1996/08/29 09:48:23 davem Exp $ */
#ifndef _SPARC_MEMREG_H
#define _SPARC_MEMREG_H
/* memreg.h: Definitions of the values found in the synchronous
* and asynchronous memory error registers when a fault
* occurs on the sun4c.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* First the synchronous error codes, these are usually just
* normal page faults.
*/
#define SUN4C_SYNC_WDRESET 0x0001 /* watchdog reset */
#define SUN4C_SYNC_SIZE 0x0002 /* bad access size? whuz this? */
#define SUN4C_SYNC_PARITY 0x0008 /* bad ram chips caused a parity error */
#define SUN4C_SYNC_SBUS 0x0010 /* the SBUS had some problems... */
#define SUN4C_SYNC_NOMEM 0x0020 /* translation to non-existent ram */
#define SUN4C_SYNC_PROT 0x0040 /* access violated pte protections */
#define SUN4C_SYNC_NPRESENT 0x0080 /* pte said that page was not present */
#define SUN4C_SYNC_BADWRITE 0x8000 /* while writing something went bogus */
#define SUN4C_SYNC_BOLIXED \
(SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
/* Now the asynchronous error codes, these are almost always produced
* by the cache writing things back to memory and getting a bad translation.
* Bad DVMA transactions can cause these faults too.
*/
#define SUN4C_ASYNC_BADDVMA 0x0010 /* error during DVMA access */
#define SUN4C_ASYNC_NOMEM 0x0020 /* write back pointed to bad phys addr */
#define SUN4C_ASYNC_BADWB 0x0080 /* write back points to non-present page */
/* Memory parity error register with associated bit constants. */
#ifndef __ASSEMBLY__
extern __volatile__ unsigned long *sun4c_memerr_reg;
#endif
#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */
#define SUN4C_MPE_MULTI 0x40 /* Multiple parity errors detected. (ro) */
#define SUN4C_MPE_TEST 0x20 /* Write inverse parity. (rw) */
#define SUN4C_MPE_CHECK 0x10 /* Enable parity checking. (rw) */
#define SUN4C_MPE_ERR00 0x08 /* Parity error in bits 0-7. (ro) */
#define SUN4C_MPE_ERR08 0x04 /* Parity error in bits 8-15. (ro) */
#define SUN4C_MPE_ERR16 0x02 /* Parity error in bits 16-23. (ro) */
#define SUN4C_MPE_ERR24 0x01 /* Parity error in bits 24-31. (ro) */
#define SUN4C_MPE_ERRS 0x0F /* Bit mask for the error bits. (ro) */
#endif /* !(_SPARC_MEMREG_H) */

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/* $Id: mman.h,v 1.9 2000/03/15 02:44:23 davem Exp $ */
#ifndef __SPARC_MMAN_H__
#define __SPARC_MMAN_H__
/* SunOS'ified... */
#define PROT_READ 0x1 /* page can be read */
#define PROT_WRITE 0x2 /* page can be written */
#define PROT_EXEC 0x4 /* page can be executed */
#define PROT_SEM 0x8 /* page may be used for atomic ops */
#define PROT_NONE 0x0 /* page can not be accessed */
#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
#define MAP_SHARED 0x01 /* Share changes */
#define MAP_PRIVATE 0x02 /* Changes are private */
#define MAP_TYPE 0x0f /* Mask for type of mapping */
#define MAP_FIXED 0x10 /* Interpret addr exactly */
#define MAP_ANONYMOUS 0x20 /* don't use a file */
#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
#define MAP_INHERIT 0x80 /* SunOS doesn't do this, but... */
#define MAP_LOCKED 0x100 /* lock the mapping */
#define _MAP_NEW 0x80000000 /* Binary compatibility is fun... */
#define MAP_GROWSDOWN 0x0200 /* stack-like segment */
#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_INVALIDATE 2 /* invalidate the caches */
#define MS_SYNC 4 /* synchronous memory sync */
#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
#define MCL_FUTURE 0x4000 /* lock all additions to address space */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
/* XXX Need to add flags to SunOS's mctl, mlockall, and madvise system
* XXX calls.
*/
/* SunOS sys_mctl() stuff... */
#define MC_SYNC 1 /* Sync pages in memory with storage (usu. a file) */
#define MC_LOCK 2 /* Lock pages into core ram, do not allow swapping of them */
#define MC_UNLOCK 3 /* Unlock pages locked via previous mctl() with MC_LOCK arg */
#define MC_LOCKAS 5 /* Lock an entire address space of the calling process */
#define MC_UNLOCKAS 6 /* Unlock entire address space of calling process */
#define MADV_NORMAL 0x0 /* default page-in behavior */
#define MADV_RANDOM 0x1 /* page-in minimum required */
#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
#define MADV_WILLNEED 0x3 /* pre-fault pages */
#define MADV_DONTNEED 0x4 /* discard these pages */
#define MADV_FREE 0x5 /* (Solaris) contents can be freed */
/* compatibility flags */
#define MAP_ANON MAP_ANONYMOUS
#define MAP_FILE 0
#endif /* __SPARC_MMAN_H__ */

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#ifndef __MMU_H
#define __MMU_H
/* Default "unsigned long" context */
typedef unsigned long mm_context_t;
#endif

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#ifndef __SPARC_MMU_CONTEXT_H
#define __SPARC_MMU_CONTEXT_H
#include <asm/btfixup.h>
#ifndef __ASSEMBLY__
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
/*
* Initialize a new mmu context. This is invoked when a new
* address space instance (unique or shared) is instantiated.
*/
#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
/*
* Destroy a dead context. This occurs when mmput drops the
* mm_users count to zero, the mmaps have been released, and
* all the page tables have been flushed. Our job is to destroy
* any remaining processor-specific state.
*/
BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
/* Switch the current MM context. */
BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
#define deactivate_mm(tsk,mm) do { } while (0)
/* Activate a new MM instance for the current task. */
#define activate_mm(active_mm, mm) switch_mm((active_mm), (mm), NULL)
#endif /* !(__ASSEMBLY__) */
#endif /* !(__SPARC_MMU_CONTEXT_H) */

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#ifndef _ASM_SPARC_MODULE_H
#define _ASM_SPARC_MODULE_H
struct mod_arch_specific { };
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Ehdr Elf32_Ehdr
#endif /* _ASM_SPARC_MODULE_H */

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/* $Id: mostek.h,v 1.13 2001/01/11 15:07:09 davem Exp $
* mostek.h: Describes the various Mostek time of day clock registers.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
* Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
*/
#ifndef _SPARC_MOSTEK_H
#define _SPARC_MOSTEK_H
#include <linux/config.h>
#include <asm/idprom.h>
#include <asm/io.h>
/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
*
* Data
* Address Function
* Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
* 7ff - - - - - - - - Year 00-99
* 7fe 0 0 0 - - - - - Month 01-12
* 7fd 0 0 - - - - - - Date 01-31
* 7fc 0 FT 0 0 0 - - - Day 01-07
* 7fb KS 0 - - - - - - Hours 00-23
* 7fa 0 - - - - - - - Minutes 00-59
* 7f9 ST - - - - - - - Seconds 00-59
* 7f8 W R S - - - - - Control
*
* * ST is STOP BIT
* * W is WRITE BIT
* * R is READ BIT
* * S is SIGN BIT
* * FT is FREQ TEST BIT
* * KS is KICK START BIT
*/
/* The Mostek 48t02 real time clock and NVRAM chip. The registers
* other than the control register are in binary coded decimal. Some
* control bits also live outside the control register.
*/
#define mostek_read(_addr) readb(_addr)
#define mostek_write(_addr,_val) writeb(_val, _addr)
#define MOSTEK_EEPROM 0x0000UL
#define MOSTEK_IDPROM 0x07d8UL
#define MOSTEK_CREG 0x07f8UL
#define MOSTEK_SEC 0x07f9UL
#define MOSTEK_MIN 0x07faUL
#define MOSTEK_HOUR 0x07fbUL
#define MOSTEK_DOW 0x07fcUL
#define MOSTEK_DOM 0x07fdUL
#define MOSTEK_MONTH 0x07feUL
#define MOSTEK_YEAR 0x07ffUL
struct mostek48t02 {
volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
struct idprom idprom; /* The idprom lives here. */
volatile unsigned char creg; /* Control register */
volatile unsigned char sec; /* Seconds (0-59) */
volatile unsigned char min; /* Minutes (0-59) */
volatile unsigned char hour; /* Hour (0-23) */
volatile unsigned char dow; /* Day of the week (1-7) */
volatile unsigned char dom; /* Day of the month (1-31) */
volatile unsigned char month; /* Month of year (1-12) */
volatile unsigned char year; /* Year (0-99) */
};
extern spinlock_t mostek_lock;
extern void __iomem *mstk48t02_regs;
/* Control register values. */
#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
/* Control bits that live in the other registers. */
#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
/* Masks that define how much space each value takes up. */
#define MSTK_SEC_MASK 0x7f
#define MSTK_MIN_MASK 0x7f
#define MSTK_HOUR_MASK 0x3f
#define MSTK_DOW_MASK 0x07
#define MSTK_DOM_MASK 0x3f
#define MSTK_MONTH_MASK 0x1f
#define MSTK_YEAR_MASK 0xff
/* Binary coded decimal conversion macros. */
#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
/* Generic register set and get macros for internal use. */
#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
/* Macros to make register access easier on our fingers. These give you
* the decimal value of the register requested if applicable. You pass
* the a pointer to a 'struct mostek48t02'.
*/
#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
* same (basically) layout of the 48t02 chip except for the extra
* NVRAM on board (8 KB against the 48t02's 2 KB).
*/
struct mostek48t08 {
char offset[6*1024]; /* Magic things may be here, who knows? */
struct mostek48t02 regs; /* Here is what we are interested in. */
};
extern enum sparc_clock_type sp_clock_typ;
#ifdef CONFIG_SUN4
enum sparc_clock_type { MSTK48T02, MSTK48T08, \
INTERSIL, MSTK_INVALID };
#else
enum sparc_clock_type { MSTK48T02, MSTK48T08, \
MSTK_INVALID };
#endif
#ifdef CONFIG_SUN4
/* intersil on a sun 4/260 code data from harris doc */
struct intersil_dt {
volatile unsigned char int_csec;
volatile unsigned char int_hour;
volatile unsigned char int_min;
volatile unsigned char int_sec;
volatile unsigned char int_month;
volatile unsigned char int_day;
volatile unsigned char int_year;
volatile unsigned char int_dow;
};
struct intersil {
struct intersil_dt clk;
struct intersil_dt cmp;
volatile unsigned char int_intr_reg;
volatile unsigned char int_cmd_reg;
};
#define INTERSIL_STOP 0x0
#define INTERSIL_START 0x8
#define INTERSIL_INTR_DISABLE 0x0
#define INTERSIL_INTR_ENABLE 0x10
#define INTERSIL_32K 0x0
#define INTERSIL_NORMAL 0x0
#define INTERSIL_24H 0x4
#define INTERSIL_INT_100HZ 0x2
/* end of intersil info */
#endif
#endif /* !(_SPARC_MOSTEK_H) */

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/* $Id: mpmbox.h,v 1.4 1996/04/25 06:13:19 davem Exp $
* mpmbox.h: Interface and defines for the OpenProm mailbox
* facilities for MP machines under Linux.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_MPMBOX_H
#define _SPARC_MPMBOX_H
/* The prom allocates, for each CPU on the machine an unsigned
* byte in physical ram. You probe the device tree prom nodes
* for these values. The purpose of this byte is to be able to
* pass messages from one cpu to another.
*/
/* These are the main message types we have to look for in our
* Cpu mailboxes, based upon these values we decide what course
* of action to take.
*/
/* The CPU is executing code in the kernel. */
#define MAILBOX_ISRUNNING 0xf0
/* Another CPU called romvec->pv_exit(), you should call
* prom_stopcpu() when you see this in your mailbox.
*/
#define MAILBOX_EXIT 0xfb
/* Another CPU called romvec->pv_enter(), you should call
* prom_cpuidle() when this is seen.
*/
#define MAILBOX_GOSPIN 0xfc
/* Another CPU has hit a breakpoint either into kadb or the prom
* itself. Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
* at this point.
*/
#define MAILBOX_BPT_SPIN 0xfd
/* Oh geese, some other nitwit got a damn watchdog reset. The party's
* over so go call prom_stopcpu().
*/
#define MAILBOX_WDOG_STOP 0xfe
#ifndef __ASSEMBLY__
/* Handy macro's to determine a cpu's state. */
/* Is the cpu still in Power On Self Test? */
#define MBOX_POST_P(letter) ((letter) >= 0x00 && (letter) <= 0x7f)
/* Is the cpu at the 'ok' prompt of the PROM? */
#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
/* Is the cpu spinning in the PROM? */
#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
/* Sanity check... This is junk mail, throw it out. */
#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
/* Is the cpu actively running an application/kernel-code? */
#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_MPMBOX_H) */

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#ifndef _SPARC64_MSGBUF_H
#define _SPARC64_MSGBUF_H
/*
* The msqid64_ds structure for sparc64 architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 64-bit time_t to solve y2038 problem
* - 2 miscellaneous 32-bit values
*/
struct msqid64_ds {
struct ipc64_perm msg_perm;
unsigned int __pad1;
__kernel_time_t msg_stime; /* last msgsnd time */
unsigned int __pad2;
__kernel_time_t msg_rtime; /* last msgrcv time */
unsigned int __pad3;
__kernel_time_t msg_ctime; /* last change time */
unsigned long msg_cbytes; /* current number of bytes on queue */
unsigned long msg_qnum; /* number of messages in queue */
unsigned long msg_qbytes; /* max number of bytes on queue */
__kernel_pid_t msg_lspid; /* pid of last msgsnd */
__kernel_pid_t msg_lrpid; /* last receive pid */
unsigned long __unused1;
unsigned long __unused2;
};
#endif /* _SPARC64_MSGBUF_H */

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/* $Id: msi.h,v 1.3 1996/08/29 09:48:25 davem Exp $
* msi.h: Defines specific to the MBus - Sbus - Interface.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
*/
#ifndef _SPARC_MSI_H
#define _SPARC_MSI_H
/*
* Locations of MSI Registers.
*/
#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
/*
* Useful bits in the MSI Registers.
*/
#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
extern __inline__ void msi_set_sync(void)
{
__asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
"andn %%g3, %2, %%g3\n\t"
"sta %%g3, [%0] %1\n\t" : :
"r" (MSI_MBUS_ARBEN),
"i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
}
#endif /* !(_SPARC_MSI_H) */

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/* $Id: mxcc.h,v 1.7 1997/04/20 14:11:46 ecd Exp $
* mxcc.h: Definitions of the Viking MXCC registers
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_MXCC_H
#define _SPARC_MXCC_H
/* These registers are accessed through ASI 0x2. */
#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
#define MXCC_STEST 0x1C00804 /* Internal self-test */
#define MXCC_CREG 0x1C00A04 /* Control register */
#define MXCC_SREG 0x1C00B00 /* Status register */
#define MXCC_RREG 0x1C00C04 /* Reset register */
#define MXCC_EREG 0x1C00E00 /* Error code register */
#define MXCC_PREG 0x1C00F04 /* Address port register */
/* Some MXCC constants. */
#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
/* The MXCC Control Register:
*
* ----------------------------------------------------------------------
* | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
* ----------------------------------------------------------------------
* 31 10 9 8-6 5 4 3 2 1-0
*
* RRC: Controls what you read from MXCC_RMCOUNT reg.
* 0=Misses 1=References
* PRE: Prefetch enable
* MCE: Multiple Command Enable
* PARE: Parity enable
* ECE: External cache enable
*/
#define MXCC_CTL_RRC 0x00000200
#define MXCC_CTL_PRE 0x00000020
#define MXCC_CTL_MCE 0x00000010
#define MXCC_CTL_PARE 0x00000008
#define MXCC_CTL_ECE 0x00000004
/* The MXCC Error Register:
*
* --------------------------------------------------------
* |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
* --------------------------------------------------------
* 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
*
* ME: Multiple Errors have occurred
* CE: Cache consistency Error
* PEW: Parity Error during a Write operation
* PEE: Parity Error involving the External cache
* ASE: ASynchronous Error
* EIV: This register is toast
* MOPC: MXCC Operation Code for instance causing error
* ECODE: The Error CODE
* PRIV: A privileged mode error? 0=no 1=yes
* HPADDR: High PhysicalADDRess bits (35-32)
*/
#define MXCC_ERR_ME 0x80000000
#define MXCC_ERR_CE 0x20000000
#define MXCC_ERR_PEW 0x10000000
#define MXCC_ERR_PEE 0x08000000
#define MXCC_ERR_ASE 0x04000000
#define MXCC_ERR_EIV 0x02000000
#define MXCC_ERR_MOPC 0x01FF8000
#define MXCC_ERR_ECODE 0x00007F80
#define MXCC_ERR_PRIV 0x00000040
#define MXCC_ERR_HPADDR 0x0000000f
/* The MXCC Port register:
*
* -----------------------------------------------------
* | | MID | |
* -----------------------------------------------------
* 31 21 20-18 17 0
*
* MID: The moduleID of the cpu your read this from.
*/
#ifndef __ASSEMBLY__
extern __inline__ void mxcc_set_stream_src(unsigned long *paddr)
{
unsigned long data0 = paddr[0];
unsigned long data1 = paddr[1];
__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
"or %%g0, %1, %%g3\n\t"
"stda %%g2, [%2] %3\n\t" : :
"r" (data0), "r" (data1),
"r" (MXCC_SRCSTREAM),
"i" (ASI_M_MXCC) : "g2", "g3");
}
extern __inline__ void mxcc_set_stream_dst(unsigned long *paddr)
{
unsigned long data0 = paddr[0];
unsigned long data1 = paddr[1];
__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
"or %%g0, %1, %%g3\n\t"
"stda %%g2, [%2] %3\n\t" : :
"r" (data0), "r" (data1),
"r" (MXCC_DESSTREAM),
"i" (ASI_M_MXCC) : "g2", "g3");
}
extern __inline__ unsigned long mxcc_get_creg(void)
{
unsigned long mxcc_control;
__asm__ __volatile__("set -1, %%g2\n\t"
"set -1, %%g3\n\t"
"stda %%g2, [%1] %2\n\t"
"lda [%3] %2, %0\n\t" :
"=r" (mxcc_control) :
"r" (MXCC_EREG), "i" (ASI_M_MXCC),
"r" (MXCC_CREG) : "g2", "g3");
return mxcc_control;
}
extern __inline__ void mxcc_set_creg(unsigned long mxcc_control)
{
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (mxcc_control), "r" (MXCC_CREG),
"i" (ASI_M_MXCC));
}
#endif /* !__ASSEMBLY__ */
#endif /* !(_SPARC_MXCC_H) */

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/* $Id: namei.h,v 1.16 2000/04/13 00:55:54 davem Exp $
* linux/include/asm-sparc/namei.h
*
* Routines to handle famous /usr/gnemul/s*.
* Included from linux/fs/namei.c
*/
#ifndef __SPARC_NAMEI_H
#define __SPARC_NAMEI_H
#define SPARC_BSD_EMUL "/usr/gnemul/sunos/"
#define SPARC_SOL_EMUL "/usr/gnemul/solaris/"
static inline char * __emul_prefix(void)
{
switch (current->personality) {
case PER_SUNOS:
return SPARC_BSD_EMUL;
case PER_SVR4:
return SPARC_SOL_EMUL;
default:
return NULL;
}
}
#endif /* __SPARC_NAMEI_H */

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/* $Id: obio.h,v 1.4 1998/03/09 14:04:55 jj Exp $
* obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
*
* Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
*/
#ifndef _SPARC_OBIO_H
#define _SPARC_OBIO_H
#include <asm/asi.h>
/* This weird monster likes to use the very upper parts of
36bit PA for these things :) */
/* CSR space (for each XDBUS)
* ------------------------------------------------------------------------
* | 0xFE | DEVID | | XDBUS ID | |
* ------------------------------------------------------------------------
* 35 28 27 20 19 10 9 8 7 0
*/
#define CSR_BASE_ADDR 0xe0000000
#define CSR_CPU_SHIFT (32 - 4 - 5)
#define CSR_XDBUS_SHIFT 8
#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
/* ECSR space (not for each XDBUS)
* ------------------------------------------------------------------------
* | 0xF | DEVID[7:1] | |
* ------------------------------------------------------------------------
* 35 32 31 25 24 0
*/
#define ECSR_BASE_ADDR 0x00000000
#define ECSR_CPU_SHIFT (32 - 5)
#define ECSR_DEV_SHIFT (32 - 8)
#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
/* Bus Watcher */
#define BW_LOCAL_BASE 0xfff00000
#define BW_CID 0x00000000
#define BW_DBUS_CTRL 0x00000008
#define BW_DBUS_DATA 0x00000010
#define BW_CTRL 0x00001000
#define BW_INTR_TABLE 0x00001040
#define BW_INTR_TABLE_CLEAR 0x00001080
#define BW_PRESCALER 0x000010c0
#define BW_PTIMER_LIMIT 0x00002000
#define BW_PTIMER_COUNTER2 0x00002004
#define BW_PTIMER_NDLIMIT 0x00002008
#define BW_PTIMER_CTRL 0x0000200c
#define BW_PTIMER_COUNTER 0x00002010
#define BW_TIMER_LIMIT 0x00003000
#define BW_TIMER_COUNTER2 0x00003004
#define BW_TIMER_NDLIMIT 0x00003008
#define BW_TIMER_CTRL 0x0000300c
#define BW_TIMER_COUNTER 0x00003010
/* BW Control */
#define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
/* Boot Bus */
#define BB_LOCAL_BASE 0xf0000000
#define BB_STAT1 0x00100000
#define BB_STAT2 0x00120000
#define BB_STAT3 0x00140000
#define BB_LEDS 0x002e0000
/* Bits in BB_STAT2 */
#define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
#define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
#define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
#define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
#define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
/* Cache Controller */
#define CC_BASE 0x1F00000
#define CC_DATSTREAM 0x1F00000 /* Data stream register */
#define CC_DATSIZE 0x1F0003F /* Size */
#define CC_SRCSTREAM 0x1F00100 /* Source stream register */
#define CC_DESSTREAM 0x1F00200 /* Destination stream register */
#define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
#define CC_IPEN 0x1F00406 /* Pending Interrupts */
#define CC_IMSK 0x1F00506 /* Interrupt Mask */
#define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
#define CC_IGEN 0x1F00704 /* Generate Interrupt register */
#define CC_STEST 0x1F00804 /* Internal self-test */
#define CC_CREG 0x1F00A04 /* Control register */
#define CC_SREG 0x1F00B00 /* Status register */
#define CC_RREG 0x1F00C04 /* Reset register */
#define CC_EREG 0x1F00E00 /* Error code register */
#define CC_CID 0x1F00F04 /* Component ID */
#ifndef __ASSEMBLY__
extern __inline__ int bw_get_intr_mask(int sbus_level)
{
int mask;
__asm__ __volatile__ ("lduha [%1] %2, %0" :
"=r" (mask) :
"r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
"i" (ASI_M_CTL));
return mask;
}
extern __inline__ void bw_clear_intr_mask(int sbus_level, int mask)
{
__asm__ __volatile__ ("stha %0, [%1] %2" : :
"r" (mask),
"r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
"i" (ASI_M_CTL));
}
extern __inline__ unsigned bw_get_prof_limit(int cpu)
{
unsigned limit;
__asm__ __volatile__ ("lda [%1] %2, %0" :
"=r" (limit) :
"r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
"i" (ASI_M_CTL));
return limit;
}
extern __inline__ void bw_set_prof_limit(int cpu, unsigned limit)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (limit),
"r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
"i" (ASI_M_CTL));
}
extern __inline__ unsigned bw_get_ctrl(int cpu)
{
unsigned ctrl;
__asm__ __volatile__ ("lda [%1] %2, %0" :
"=r" (ctrl) :
"r" (CSR_BASE(cpu) + BW_CTRL),
"i" (ASI_M_CTL));
return ctrl;
}
extern __inline__ void bw_set_ctrl(int cpu, unsigned ctrl)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (ctrl),
"r" (CSR_BASE(cpu) + BW_CTRL),
"i" (ASI_M_CTL));
}
extern unsigned char cpu_leds[32];
extern __inline__ void show_leds(int cpuid)
{
cpuid &= 0x1e;
__asm__ __volatile__ ("stba %0, [%1] %2" : :
"r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
"r" (ECSR_BASE(cpuid) | BB_LEDS),
"i" (ASI_M_CTL));
}
extern __inline__ unsigned cc_get_ipen(void)
{
unsigned pending;
__asm__ __volatile__ ("lduha [%1] %2, %0" :
"=r" (pending) :
"r" (CC_IPEN),
"i" (ASI_M_MXCC));
return pending;
}
extern __inline__ void cc_set_iclr(unsigned clear)
{
__asm__ __volatile__ ("stha %0, [%1] %2" : :
"r" (clear),
"r" (CC_ICLR),
"i" (ASI_M_MXCC));
}
extern __inline__ unsigned cc_get_imsk(void)
{
unsigned mask;
__asm__ __volatile__ ("lduha [%1] %2, %0" :
"=r" (mask) :
"r" (CC_IMSK),
"i" (ASI_M_MXCC));
return mask;
}
extern __inline__ void cc_set_imsk(unsigned mask)
{
__asm__ __volatile__ ("stha %0, [%1] %2" : :
"r" (mask),
"r" (CC_IMSK),
"i" (ASI_M_MXCC));
}
extern __inline__ unsigned cc_get_imsk_other(int cpuid)
{
unsigned mask;
__asm__ __volatile__ ("lduha [%1] %2, %0" :
"=r" (mask) :
"r" (ECSR_BASE(cpuid) | CC_IMSK),
"i" (ASI_M_CTL));
return mask;
}
extern __inline__ void cc_set_imsk_other(int cpuid, unsigned mask)
{
__asm__ __volatile__ ("stha %0, [%1] %2" : :
"r" (mask),
"r" (ECSR_BASE(cpuid) | CC_IMSK),
"i" (ASI_M_CTL));
}
extern __inline__ void cc_set_igen(unsigned gen)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (gen),
"r" (CC_IGEN),
"i" (ASI_M_MXCC));
}
/* +-------+-------------+-----------+------------------------------------+
* | bcast | devid | sid | levels mask |
* +-------+-------------+-----------+------------------------------------+
* 31 30 23 22 15 14 0
*/
#define IGEN_MESSAGE(bcast, devid, sid, levels) \
(((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
extern __inline__ void sun4d_send_ipi(int cpu, int level)
{
cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
}
#endif /* !__ASSEMBLY__ */
#endif /* !(_SPARC_OBIO_H) */

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/* $Id: openprom.h,v 1.24 2000/06/04 06:23:53 anton Exp $ */
#ifndef __SPARC_OPENPROM_H
#define __SPARC_OPENPROM_H
/* openprom.h: Prom structures and defines for access to the OPENBOOT
* prom routines and data areas.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#include <asm/vaddrs.h>
/* Empirical constants... */
#define LINUX_OPPROM_MAGIC 0x10010407
#ifndef __ASSEMBLY__
/* V0 prom device operations. */
struct linux_dev_v0_funcs {
int (*v0_devopen)(char *device_str);
int (*v0_devclose)(int dev_desc);
int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
};
/* V2 and later prom device operations. */
struct linux_dev_v2_funcs {
int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
void (*v2_dumb_mem_free)(char *va, unsigned sz);
/* To map devices into virtual I/O space. */
char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
void (*v2_dumb_munmap)(char *virta, unsigned size);
int (*v2_dev_open)(char *devpath);
void (*v2_dev_close)(int d);
int (*v2_dev_read)(int d, char *buf, int nbytes);
int (*v2_dev_write)(int d, char *buf, int nbytes);
int (*v2_dev_seek)(int d, int hi, int lo);
/* Never issued (multistage load support) */
void (*v2_wheee2)(void);
void (*v2_wheee3)(void);
};
struct linux_mlist_v0 {
struct linux_mlist_v0 *theres_more;
char *start_adr;
unsigned num_bytes;
};
struct linux_mem_v0 {
struct linux_mlist_v0 **v0_totphys;
struct linux_mlist_v0 **v0_prommap;
struct linux_mlist_v0 **v0_available; /* What we can use */
};
/* Arguments sent to the kernel from the boot prompt. */
struct linux_arguments_v0 {
char *argv[8];
char args[100];
char boot_dev[2];
int boot_dev_ctrl;
int boot_dev_unit;
int dev_partition;
char *kernel_file_name;
void *aieee1; /* XXX */
};
/* V2 and up boot things. */
struct linux_bootargs_v2 {
char **bootpath;
char **bootargs;
int *fd_stdin;
int *fd_stdout;
};
/* The top level PROM vector. */
struct linux_romvec {
/* Version numbers. */
unsigned int pv_magic_cookie;
unsigned int pv_romvers;
unsigned int pv_plugin_revision;
unsigned int pv_printrev;
/* Version 0 memory descriptors. */
struct linux_mem_v0 pv_v0mem;
/* Node operations. */
struct linux_nodeops *pv_nodeops;
char **pv_bootstr;
struct linux_dev_v0_funcs pv_v0devops;
char *pv_stdin;
char *pv_stdout;
#define PROMDEV_KBD 0 /* input from keyboard */
#define PROMDEV_SCREEN 0 /* output to screen */
#define PROMDEV_TTYA 1 /* in/out to ttya */
#define PROMDEV_TTYB 2 /* in/out to ttyb */
/* Blocking getchar/putchar. NOT REENTRANT! (grr) */
int (*pv_getchar)(void);
void (*pv_putchar)(int ch);
/* Non-blocking variants. */
int (*pv_nbgetchar)(void);
int (*pv_nbputchar)(int ch);
void (*pv_putstr)(char *str, int len);
/* Miscellany. */
void (*pv_reboot)(char *bootstr);
void (*pv_printf)(__const__ char *fmt, ...);
void (*pv_abort)(void);
__volatile__ int *pv_ticks;
void (*pv_halt)(void);
void (**pv_synchook)(void);
/* Evaluate a forth string, not different proto for V0 and V2->up. */
union {
void (*v0_eval)(int len, char *str);
void (*v2_eval)(char *str);
} pv_fortheval;
struct linux_arguments_v0 **pv_v0bootargs;
/* Get ether address. */
unsigned int (*pv_enaddr)(int d, char *enaddr);
struct linux_bootargs_v2 pv_v2bootargs;
struct linux_dev_v2_funcs pv_v2devops;
int filler[15];
/* This one is sun4c/sun4 only. */
void (*pv_setctxt)(int ctxt, char *va, int pmeg);
/* Prom version 3 Multiprocessor routines. This stuff is crazy.
* No joke. Calling these when there is only one cpu probably
* crashes the machine, have to test this. :-)
*/
/* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
* 'thiscontext' executing at address 'prog_counter'
*/
int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
int thiscontext, char *prog_counter);
/* v3_cpustop() will cause cpu 'whichcpu' to stop executing
* until a resume cpu call is made.
*/
int (*v3_cpustop)(unsigned int whichcpu);
/* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
* resume cpu call is made.
*/
int (*v3_cpuidle)(unsigned int whichcpu);
/* v3_cpuresume() will resume processor 'whichcpu' executing
* starting with whatever 'pc' and 'npc' were left at the
* last 'idle' or 'stop' call.
*/
int (*v3_cpuresume)(unsigned int whichcpu);
};
/* Routines for traversing the prom device tree. */
struct linux_nodeops {
int (*no_nextnode)(int node);
int (*no_child)(int node);
int (*no_proplen)(int node, char *name);
int (*no_getprop)(int node, char *name, char *val);
int (*no_setprop)(int node, char *name, char *val, int len);
char * (*no_nextprop)(int node, char *name);
};
/* More fun PROM structures for device probing. */
#define PROMREG_MAX 16
#define PROMVADDR_MAX 16
#define PROMINTR_MAX 15
struct linux_prom_registers {
unsigned int which_io; /* is this in OBIO space? */
unsigned int phys_addr; /* The physical address of this register */
unsigned int reg_size; /* How many bytes does this register take up? */
};
struct linux_prom_irqs {
int pri; /* IRQ priority */
int vector; /* This is foobar, what does it do? */
};
/* Element of the "ranges" vector */
struct linux_prom_ranges {
unsigned int ot_child_space;
unsigned int ot_child_base; /* Bus feels this */
unsigned int ot_parent_space;
unsigned int ot_parent_base; /* CPU looks from here */
unsigned int or_size;
};
/* Ranges and reg properties are a bit different for PCI. */
struct linux_prom_pci_registers {
/*
* We don't know what information this field contain.
* We guess, PCI device function is in bits 15:8
* So, ...
*/
unsigned int which_io; /* Let it be which_io */
unsigned int phys_hi;
unsigned int phys_lo;
unsigned int size_hi;
unsigned int size_lo;
};
struct linux_prom_pci_ranges {
unsigned int child_phys_hi; /* Only certain bits are encoded here. */
unsigned int child_phys_mid;
unsigned int child_phys_lo;
unsigned int parent_phys_hi;
unsigned int parent_phys_lo;
unsigned int size_hi;
unsigned int size_lo;
};
struct linux_prom_pci_assigned_addresses {
unsigned int which_io;
unsigned int phys_hi;
unsigned int phys_lo;
unsigned int size_hi;
unsigned int size_lo;
};
struct linux_prom_ebus_ranges {
unsigned int child_phys_hi;
unsigned int child_phys_lo;
unsigned int parent_phys_hi;
unsigned int parent_phys_mid;
unsigned int parent_phys_lo;
unsigned int size;
};
#endif /* !(__ASSEMBLY__) */
#endif /* !(__SPARC_OPENPROM_H) */

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#ifndef _SPARC_OPENPROMIO_H
#define _SPARC_OPENPROMIO_H
#include <linux/compiler.h>
#include <linux/ioctl.h>
#include <linux/types.h>
/*
* SunOS and Solaris /dev/openprom definitions. The ioctl values
* were chosen to be exactly equal to the SunOS equivalents.
*/
struct openpromio
{
u_int oprom_size; /* Actual size of the oprom_array. */
char oprom_array[1]; /* Holds property names and values. */
};
#define OPROMMAXPARAM 4096 /* Maximum size of oprom_array. */
#define OPROMGETOPT 0x20004F01
#define OPROMSETOPT 0x20004F02
#define OPROMNXTOPT 0x20004F03
#define OPROMSETOPT2 0x20004F04
#define OPROMNEXT 0x20004F05
#define OPROMCHILD 0x20004F06
#define OPROMGETPROP 0x20004F07
#define OPROMNXTPROP 0x20004F08
#define OPROMU2P 0x20004F09
#define OPROMGETCONS 0x20004F0A
#define OPROMGETFBNAME 0x20004F0B
#define OPROMGETBOOTARGS 0x20004F0C
/* Linux extensions */ /* Arguments in oprom_array: */
#define OPROMSETCUR 0x20004FF0 /* int node - Sets current node */
#define OPROMPCI2NODE 0x20004FF1 /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
#define OPROMPATH2NODE 0x20004FF2 /* char path[] - Set current node from fully qualified PROM path */
/*
* Return values from OPROMGETCONS:
*/
#define OPROMCONS_NOT_WSCONS 0
#define OPROMCONS_STDIN_IS_KBD 0x1 /* stdin device is kbd */
#define OPROMCONS_STDOUT_IS_FB 0x2 /* stdout is a framebuffer */
#define OPROMCONS_OPENPROM 0x4 /* supports openboot */
/*
* NetBSD/OpenBSD /dev/openprom definitions.
*/
struct opiocdesc
{
int op_nodeid; /* PROM Node ID (value-result) */
int op_namelen; /* Length of op_name. */
char __user *op_name; /* Pointer to the property name. */
int op_buflen; /* Length of op_buf (value-result) */
char __user *op_buf; /* Pointer to buffer. */
};
#define OPIOCGET _IOWR('O', 1, struct opiocdesc)
#define OPIOCSET _IOW('O', 2, struct opiocdesc)
#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc)
#define OPIOCGETOPTNODE _IOR('O', 4, int)
#define OPIOCGETNEXT _IOWR('O', 5, int)
#define OPIOCGETCHILD _IOWR('O', 6, int)
#endif /* _SPARC_OPENPROMIO_H */

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/* $Id: oplib.h,v 1.23 2001/12/21 00:54:31 davem Exp $
* oplib.h: Describes the interface and available routines in the
* Linux Prom library.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef __SPARC_OPLIB_H
#define __SPARC_OPLIB_H
#include <asm/openprom.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
/* The master romvec pointer... */
extern struct linux_romvec *romvec;
/* Enumeration to describe the prom major version we have detected. */
enum prom_major_version {
PROM_V0, /* Original sun4c V0 prom */
PROM_V2, /* sun4c and early sun4m V2 prom */
PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
PROM_AP1000, /* actually no prom at all */
PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
};
extern enum prom_major_version prom_vers;
/* Revision, and firmware revision. */
extern unsigned int prom_rev, prom_prev;
/* Root node of the prom device tree, this stays constant after
* initialization is complete.
*/
extern int prom_root_node;
/* PROM stdin and stdout */
extern int prom_stdin, prom_stdout;
/* Pointer to prom structure containing the device tree traversal
* and usage utility functions. Only prom-lib should use these,
* users use the interface defined by the library only!
*/
extern struct linux_nodeops *prom_nodeops;
/* The functions... */
/* You must call prom_init() before using any of the library services,
* preferably as early as possible. Pass it the romvec pointer.
*/
extern void prom_init(struct linux_romvec *rom_ptr);
/* Boot argument acquisition, returns the boot command line string. */
extern char *prom_getbootargs(void);
/* Device utilities. */
/* Map and unmap devices in IO space at virtual addresses. Note that the
* virtual address you pass is a request and the prom may put your mappings
* somewhere else, so check your return value as that is where your new
* mappings really are!
*
* Another note, these are only available on V2 or higher proms!
*/
extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
/* Device operations. */
/* Open the device described by the passed string. Note, that the format
* of the string is different on V0 vs. V2->higher proms. The caller must
* know what he/she is doing! Returns the device descriptor, an int.
*/
extern int prom_devopen(char *device_string);
/* Close a previously opened device described by the passed integer
* descriptor.
*/
extern int prom_devclose(int device_handle);
/* Do a seek operation on the device described by the passed integer
* descriptor.
*/
extern void prom_seek(int device_handle, unsigned int seek_hival,
unsigned int seek_lowval);
/* Machine memory configuration routine. */
/* This function returns a V0 format memory descriptor table, it has three
* entries. One for the total amount of physical ram on the machine, one
* for the amount of physical ram available, and one describing the virtual
* areas which are allocated by the prom. So, in a sense the physical
* available is a calculation of the total physical minus the physical mapped
* by the prom with virtual mappings.
*
* These lists are returned pre-sorted, this should make your life easier
* since the prom itself is way too lazy to do such nice things.
*/
extern struct linux_mem_v0 *prom_meminfo(void);
/* Miscellaneous routines, don't really fit in any category per se. */
/* Reboot the machine with the command line passed. */
extern void prom_reboot(char *boot_command);
/* Evaluate the forth string passed. */
extern void prom_feval(char *forth_string);
/* Enter the prom, with possibility of continuation with the 'go'
* command in newer proms.
*/
extern void prom_cmdline(void);
/* Enter the prom, with no chance of continuation for the stand-alone
* which calls this.
*/
extern void prom_halt(void) __attribute__ ((noreturn));
/* Set the PROM 'sync' callback function to the passed function pointer.
* When the user gives the 'sync' command at the prom prompt while the
* kernel is still active, the prom will call this routine.
*
* XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
*/
typedef void (*sync_func_t)(void);
extern void prom_setsync(sync_func_t func_ptr);
/* Acquire the IDPROM of the root node in the prom device tree. This
* gets passed a buffer where you would like it stuffed. The return value
* is the format type of this idprom or 0xff on error.
*/
extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
/* Get the prom major version. */
extern int prom_version(void);
/* Get the prom plugin revision. */
extern int prom_getrev(void);
/* Get the prom firmware revision. */
extern int prom_getprev(void);
/* Character operations to/from the console.... */
/* Non-blocking get character from console. */
extern int prom_nbgetchar(void);
/* Non-blocking put character to console. */
extern int prom_nbputchar(char character);
/* Blocking get character from console. */
extern char prom_getchar(void);
/* Blocking put character to console. */
extern void prom_putchar(char character);
/* Prom's internal routines, don't use in kernel/boot code. */
extern void prom_printf(char *fmt, ...);
extern void prom_write(const char *buf, unsigned int len);
/* Query for input device type */
enum prom_input_device {
PROMDEV_IKBD, /* input from keyboard */
PROMDEV_ITTYA, /* input from ttya */
PROMDEV_ITTYB, /* input from ttyb */
PROMDEV_I_UNK,
};
extern enum prom_input_device prom_query_input_device(void);
/* Query for output device type */
enum prom_output_device {
PROMDEV_OSCREEN, /* to screen */
PROMDEV_OTTYA, /* to ttya */
PROMDEV_OTTYB, /* to ttyb */
PROMDEV_O_UNK,
};
extern enum prom_output_device prom_query_output_device(void);
/* Multiprocessor operations... */
/* Start the CPU with the given device tree node, context table, and context
* at the passed program counter.
*/
extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
int context, char *program_counter);
/* Stop the CPU with the passed device tree node. */
extern int prom_stopcpu(int cpunode);
/* Idle the CPU with the passed device tree node. */
extern int prom_idlecpu(int cpunode);
/* Re-Start the CPU with the passed device tree node. */
extern int prom_restartcpu(int cpunode);
/* PROM memory allocation facilities... */
/* Allocated at possibly the given virtual address a chunk of the
* indicated size.
*/
extern char *prom_alloc(char *virt_hint, unsigned int size);
/* Free a previously allocated chunk. */
extern void prom_free(char *virt_addr, unsigned int size);
/* Sun4/sun4c specific memory-management startup hook. */
/* Map the passed segment in the given context at the passed
* virtual address.
*/
extern void prom_putsegment(int context, unsigned long virt_addr,
int physical_segment);
/* PROM device tree traversal functions... */
#ifdef PROMLIB_INTERNAL
/* Internal version of prom_getchild. */
extern int __prom_getchild(int parent_node);
/* Internal version of prom_getsibling. */
extern int __prom_getsibling(int node);
#endif
/* Get the child node of the given node, or zero if no child exists. */
extern int prom_getchild(int parent_node);
/* Get the next sibling node of the given node, or zero if no further
* siblings exist.
*/
extern int prom_getsibling(int node);
/* Get the length, at the passed node, of the given property type.
* Returns -1 on error (ie. no such property at this node).
*/
extern int prom_getproplen(int thisnode, char *property);
/* Fetch the requested property using the given buffer. Returns
* the number of bytes the prom put into your buffer or -1 on error.
*/
extern int __must_check prom_getproperty(int thisnode, char *property,
char *prop_buffer, int propbuf_size);
/* Acquire an integer property. */
extern int prom_getint(int node, char *property);
/* Acquire an integer property, with a default value. */
extern int prom_getintdefault(int node, char *property, int defval);
/* Acquire a boolean property, 0=FALSE 1=TRUE. */
extern int prom_getbool(int node, char *prop);
/* Acquire a string property, null string on error. */
extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
/* Does the passed node have the given "name"? YES=1 NO=0 */
extern int prom_nodematch(int thisnode, char *name);
/* Puts in buffer a prom name in the form name@x,y or name (x for which_io
* and y for first regs phys address
*/
extern int prom_getname(int node, char *buf, int buflen);
/* Search all siblings starting at the passed node for "name" matching
* the given string. Returns the node on success, zero on failure.
*/
extern int prom_searchsiblings(int node_start, char *name);
/* Return the first property type, as a string, for the given node.
* Returns a null string on error.
*/
extern char *prom_firstprop(int node, char *buffer);
/* Returns the next property after the passed property for the given
* node. Returns null string on failure.
*/
extern char *prom_nextprop(int node, char *prev_property, char *buffer);
/* Returns phandle of the path specified */
extern int prom_finddevice(char *name);
/* Returns 1 if the specified node has given property. */
extern int prom_node_has_property(int node, char *property);
/* Set the indicated property at the given node with the passed value.
* Returns the number of bytes of your value that the prom took.
*/
extern int prom_setprop(int node, char *prop_name, char *prop_value,
int value_size);
extern int prom_pathtoinode(char *path);
extern int prom_inst2pkg(int);
/* Dorking with Bus ranges... */
/* Apply promlib probes OBIO ranges to registers. */
extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
extern void prom_apply_generic_ranges(int node, int parent,
struct linux_prom_registers *sbusregs, int nregs);
/* CPU probing helpers. */
int cpu_find_by_instance(int instance, int *prom_node, int *mid);
int cpu_find_by_mid(int mid, int *prom_node);
int cpu_get_hwmid(int prom_node);
extern spinlock_t prom_lock;
#endif /* !(__SPARC_OPLIB_H) */

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/* $Id: page.h,v 1.55 2000/10/30 21:01:41 davem Exp $
* page.h: Various defines and such for MMU operations on the Sparc for
* the Linux kernel.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_PAGE_H
#define _SPARC_PAGE_H
#include <linux/config.h>
#ifdef CONFIG_SUN4
#define PAGE_SHIFT 13
#else
#define PAGE_SHIFT 12
#endif
#ifndef __ASSEMBLY__
/* I have my suspicions... -DaveM */
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#else
#define PAGE_SIZE (1 << PAGE_SHIFT)
#endif
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifdef __KERNEL__
#include <asm/btfixup.h>
#ifndef __ASSEMBLY__
#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
#define clear_user_page(addr, vaddr, page) \
do { clear_page(addr); \
sparc_flush_page_to_ram(page); \
} while (0)
#define copy_user_page(to, from, vaddr, page) \
do { copy_page(to, from); \
sparc_flush_page_to_ram(page); \
} while (0)
/* The following structure is used to hold the physical
* memory configuration of the machine. This is filled in
* probe_memory() and is later used by mem_init() to set up
* mem_map[]. We statically allocate SPARC_PHYS_BANKS of
* these structs, this is arbitrary. The entry after the
* last valid one has num_bytes==0.
*/
struct sparc_phys_banks {
unsigned long base_addr;
unsigned long num_bytes;
};
#define SPARC_PHYS_BANKS 32
extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
/* Cache alias structure. Entry is valid if context != -1. */
struct cache_palias {
unsigned long vaddr;
int context;
};
extern struct cache_palias *sparc_aliases;
/* passing structs on the Sparc slow us down tremendously... */
/* #define STRICT_MM_TYPECHECKS */
#ifdef STRICT_MM_TYPECHECKS
/*
* These are used to make use of C type-checking..
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long iopte; } iopte_t;
typedef struct { unsigned long pmdv[16]; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long ctxd; } ctxd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
typedef struct { unsigned long iopgprot; } iopgprot_t;
#define pte_val(x) ((x).pte)
#define iopte_val(x) ((x).iopte)
#define pmd_val(x) ((x).pmdv[0])
#define pgd_val(x) ((x).pgd)
#define ctxd_val(x) ((x).ctxd)
#define pgprot_val(x) ((x).pgprot)
#define iopgprot_val(x) ((x).iopgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __iopte(x) ((iopte_t) { (x) } )
/* #define __pmd(x) ((pmd_t) { (x) } ) */ /* XXX procedure with loop */
#define __pgd(x) ((pgd_t) { (x) } )
#define __ctxd(x) ((ctxd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
#define __iopgprot(x) ((iopgprot_t) { (x) } )
#else
/*
* .. while these make it easier on the compiler
*/
typedef unsigned long pte_t;
typedef unsigned long iopte_t;
typedef struct { unsigned long pmdv[16]; } pmd_t;
typedef unsigned long pgd_t;
typedef unsigned long ctxd_t;
typedef unsigned long pgprot_t;
typedef unsigned long iopgprot_t;
#define pte_val(x) (x)
#define iopte_val(x) (x)
#define pmd_val(x) ((x).pmdv[0])
#define pgd_val(x) (x)
#define ctxd_val(x) (x)
#define pgprot_val(x) (x)
#define iopgprot_val(x) (x)
#define __pte(x) (x)
#define __iopte(x) (x)
/* #define __pmd(x) (x) */ /* XXX later */
#define __pgd(x) (x)
#define __ctxd(x) (x)
#define __pgprot(x) (x)
#define __iopgprot(x) (x)
#endif
extern unsigned long sparc_unmapped_base;
BTFIXUPDEF_SETHI(sparc_unmapped_base)
#define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base)
/* Pure 2^n version of get_order */
extern __inline__ int get_order(unsigned long size)
{
int order;
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
#else /* !(__ASSEMBLY__) */
#define __pgprot(x) (x)
#endif /* !(__ASSEMBLY__) */
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
#define PAGE_OFFSET 0xf0000000
#ifndef __ASSEMBLY__
extern unsigned long phys_base;
extern unsigned long pfn_base;
#endif
#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + phys_base)
#define __va(x) ((void *)((unsigned long) (x) - phys_base + PAGE_OFFSET))
#define virt_to_phys __pa
#define phys_to_virt __va
#define pfn_to_page(pfn) (mem_map + ((pfn)-(pfn_base)))
#define page_to_pfn(page) ((unsigned long)(((page) - mem_map) + pfn_base))
#define virt_to_page(kaddr) (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#endif /* __KERNEL__ */
#endif /* _SPARC_PAGE_H */

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/* $Id: param.h,v 1.4 2000/10/30 21:01:41 davem Exp $ */
#ifndef _ASMSPARC_PARAM_H
#define _ASMSPARC_PARAM_H
#ifdef __KERNEL__
# define HZ 100 /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ)
#endif
#ifndef HZ
#define HZ 100
#endif
#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */
#ifndef NOGROUP
#define NOGROUP (-1)
#endif
#define MAXHOSTNAMELEN 64 /* max length of hostname */
#endif

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/* $Id: pbm.h,v 1.3 1999/12/20 17:06:35 zaitcev Exp $
*
* pbm.h: PCI bus module pseudo driver software state
* Adopted from sparc64 by V. Roganov and G. Raiko
*
* Original header:
* pbm.h: U2P PCI bus module pseudo driver software state.
*
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
*
* To put things into perspective, consider sparc64 with a few PCI controllers.
* Each type would have an own structure, with instances related one to one.
* We have only pcic on sparc, but we want to be compatible with sparc64 pbm.h.
* All three represent different abstractions.
* pci_bus - Linux PCI subsystem view of a PCI bus (including bridged buses)
* pbm - Arch-specific view of a PCI bus (sparc or sparc64)
* pcic - Chip-specific information for PCIC.
*/
#ifndef __SPARC_PBM_H
#define __SPARC_PBM_H
#include <linux/pci.h>
#include <asm/oplib.h>
struct linux_pbm_info {
int prom_node;
char prom_name[64];
/* struct linux_prom_pci_ranges pbm_ranges[PROMREG_MAX]; */
/* int num_pbm_ranges; */
/* Now things for the actual PCI bus probes. */
unsigned int pci_first_busno; /* Can it be nonzero? */
struct pci_bus *pci_bus; /* Was inline, MJ allocs now */
};
/* PCI devices which are not bridges have this placed in their pci_dev
* sysdata member. This makes OBP aware PCI device drivers easier to
* code.
*/
struct pcidev_cookie {
struct linux_pbm_info *pbm;
int prom_node;
};
#endif /* !(__SPARC_PBM_H) */

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#ifndef __SPARC_PCI_H
#define __SPARC_PCI_H
#ifdef __KERNEL__
/* Can be used to override the logic in pci_scan_bus for skipping
* already-configured bus numbers - to be used for buggy BIOSes
* or architectures with incomplete PCI setup by the loader.
*/
#define pcibios_assign_all_busses() 0
#define pcibios_scan_all_fns(a, b) 0
#define PCIBIOS_MIN_IO 0UL
#define PCIBIOS_MIN_MEM 0UL
#define PCI_IRQ_NONE 0xffffffff
extern inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
}
extern inline void pcibios_penalize_isa_irq(int irq)
{
/* We don't do dynamic PCI IRQ allocation */
}
/* Dynamic DMA mapping stuff.
*/
#define PCI_DMA_BUS_IS_PHYS (0)
#include <asm/scatterlist.h>
struct pci_dev;
/* Allocate and map kernel buffer using consistent mode DMA for a device.
* hwdev should be valid struct pci_dev pointer for PCI devices.
*/
extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
/* Free and unmap a consistent DMA buffer.
* cpu_addr is what was returned from pci_alloc_consistent,
* size must be the same as what as passed into pci_alloc_consistent,
* and likewise dma_addr must be the same as what *dma_addrp was set to.
*
* References to the memory and mappings assosciated with cpu_addr/dma_addr
* past this call are illegal.
*/
extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
/* Map a single buffer of the indicated size for DMA in streaming mode.
* The 32-bit bus address to use is returned.
*
* Once the device is given the dma address, the device owns this memory
* until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
*/
extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
/* Unmap a single streaming mode DMA translation. The dma_addr and size
* must match what was provided for in a previous pci_map_single call. All
* other usages are undefined.
*
* After this call, reads by the cpu to the buffer are guaranteed to see
* whatever the device wrote there.
*/
extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
/* pci_unmap_{single,page} is not a nop, thus... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME) \
((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME) \
((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
(((PTR)->LEN_NAME) = (VAL))
/*
* Same as above, only with pages instead of mapped addresses.
*/
extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
unsigned long offset, size_t size, int direction);
extern void pci_unmap_page(struct pci_dev *hwdev,
dma_addr_t dma_address, size_t size, int direction);
/* Map a set of buffers described by scatterlist in streaming
* mode for DMA. This is the scather-gather version of the
* above pci_map_single interface. Here the scatter gather list
* elements are each tagged with the appropriate dma address
* and length. They are obtained via sg_dma_{address,length}(SG).
*
* NOTE: An implementation may be able to use a smaller number of
* DMA address/length pairs than there are SG table elements.
* (for example via virtual mapping capabilities)
* The routine returns the number of addr/length pairs actually
* used, at most nents.
*
* Device ownership issues as mentioned above for pci_map_single are
* the same here.
*/
extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
/* Unmap a set of streaming mode DMA translations.
* Again, cpu read rules concerning calls here are the same as for
* pci_unmap_single() above.
*/
extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
/* Make physical memory consistent for a single
* streaming mode DMA translation after a transfer.
*
* If you perform a pci_map_single() but wish to interrogate the
* buffer using the cpu, yet do not wish to teardown the PCI dma
* mapping, you must call this function before doing so. At the
* next point you give the PCI dma address back to the card, you
* must first perform a pci_dma_sync_for_device, and then the device
* again owns the buffer.
*/
extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
/* Make physical memory consistent for a set of streaming
* mode DMA translations after a transfer.
*
* The same as pci_dma_sync_single_* but for a scatter-gather list,
* same rules and usage.
*/
extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
/* Return whether the given PCI device DMA address mask can
* be supported properly. For example, if your device can
* only drive the low 24-bits during PCI bus mastering, then
* you would pass 0x00ffffff as the mask to this function.
*/
extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
{
return 1;
}
#define pci_dac_dma_supported(dev, mask) (0)
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
{
}
#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
{
return (dma_addr == PCI_DMA_ERROR_CODE);
}
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __SPARC_PCI_H */

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/* $Id: pcic.h,v 1.4 1999/11/17 07:34:20 zaitcev Exp $
* pcic.h: JavaEngine 1 specific PCI definitions.
*
* Copyright (C) 1998 V. Roganov and G. Raiko
*/
#ifndef __SPARC_PCIC_H
#define __SPARC_PCIC_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <linux/smp.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <asm/pbm.h>
struct linux_pcic {
void * __iomem pcic_regs;
unsigned long pcic_io;
void * __iomem pcic_config_space_addr;
void * __iomem pcic_config_space_data;
struct resource pcic_res_regs;
struct resource pcic_res_io;
struct resource pcic_res_cfg_addr;
struct resource pcic_res_cfg_data;
struct linux_pbm_info pbm;
struct pcic_ca2irq *pcic_imap;
int pcic_imdim;
};
extern int pcic_probe(void);
/* Erm... MJ redefined pcibios_present() so that it does not work early. */
extern int pcic_present(void);
extern void sun4m_pci_init_IRQ(void);
#endif
/* Size of PCI I/O space which we relocate. */
#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
/* PCIC Register Set. */
#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
#define PCI_SIZE_0 0x44 /* 32 bits */
#define PCI_SIZE_1 0x48 /* 32 bits */
#define PCI_SIZE_2 0x4c /* 32 bits */
#define PCI_SIZE_3 0x50 /* 32 bits */
#define PCI_SIZE_4 0x54 /* 32 bits */
#define PCI_SIZE_5 0x58 /* 32 bits */
#define PCI_PIO_CONTROL 0x60 /* 8 bits */
#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
#define PCI_SYS_INT_PENDING_PIO 0x40000000
#define PCI_SYS_INT_PENDING_DMA 0x20000000
#define PCI_SYS_INT_PENDING_PCI 0x10000000
#define PCI_SYS_INT_PENDING_APSR 0x08000000
#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
#define PCI_SMBAR0 0xa0 /* 8 bits */
#define PCI_MSIZE0 0xa1 /* 8 bits */
#define PCI_PMBAR0 0xa2 /* 8 bits */
#define PCI_SMBAR1 0xa4 /* 8 bits */
#define PCI_MSIZE1 0xa5 /* 8 bits */
#define PCI_PMBAR1 0xa6 /* 8 bits */
#define PCI_SIBAR 0xa8 /* 8 bits */
#define PCI_SIBAR_ADDRESS_MASK 0xf
#define PCI_ISIZE 0xa9 /* 8 bits */
#define PCI_ISIZE_16M 0xf
#define PCI_ISIZE_32M 0xe
#define PCI_ISIZE_64M 0xc
#define PCI_ISIZE_128M 0x8
#define PCI_ISIZE_256M 0x0
#define PCI_PIBAR 0xaa /* 8 bits */
#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
#define PCI_SYS_COUNTER 0xbc /* 32 bits */
#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
((cpu_irq) & 0xf))
#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
#define PCI_SYS_STATUS 0xd0 /* 8 bits */
#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
#define PCI_SYS_STATUS_RESET (1<<1)
#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
#define PCI_SYS_STATUS_PCI_RESET (1<<5)
#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
#endif /* !(__SPARC_PCIC_H) */

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/* $Id: pconf.h,v 1.3 1996/04/25 06:13:25 davem Exp $
* pconf.h: pathconf() and fpathconf() defines for SunOS
* system call compatibility.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_PCONF_H
#define _SPARC_PCONF_H
#include <linux/fs.h>
#include <linux/limits.h>
#define _PCONF_LINK 1 /* Max number of links to an object */
#define _PCONF_CANON 2 /* TTY input buffer line size */
#define _PCONF_INPUT 3 /* Biggest packet a tty can imbibe at once */
#define _PCONF_NAME 4 /* Filename length max */
#define _PCONF_PATH 5 /* Max size of a pathname */
#define _PCONF_PIPE 6 /* Buffer size for a pipe */
#define _PCONF_CHRESTRICT 7 /* Can only root chown files? */
#define _PCONF_NOTRUNC 8 /* Are pathnames truncated if too big? */
#define _PCONF_VDISABLE 9 /* Magic char to disable special tty chars */
#define _PCONF_MAXPCONF 9
#endif /* !(_SPARC_PCONF_H) */

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#ifndef __ARCH_SPARC_PERCPU__
#define __ARCH_SPARC_PERCPU__
#include <asm-generic/percpu.h>
#endif /* __ARCH_SPARC_PERCPU__ */

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/*----------------------------------------
PERFORMANCE INSTRUMENTATION
Guillaume Thouvenin 08/10/98
David S. Miller 10/06/98
---------------------------------------*/
#ifndef PERF_COUNTER_API
#define PERF_COUNTER_API
/* sys_perfctr() interface. First arg is operation code
* from enumeration below. The meaning of further arguments
* are determined by the operation code.
*
* int sys_perfctr(int opcode, unsigned long arg0,
* unsigned long arg1, unsigned long arg2)
*
* Pointers which are passed by the user are pointers to 64-bit
* integers.
*
* Once enabled, performance counter state is retained until the
* process either exits or performs an exec. That is, performance
* counters remain enabled for fork/clone children.
*/
enum perfctr_opcode {
/* Enable UltraSparc performance counters, ARG0 is pointer
* to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
* to 64-bit accumulator for D1 counter. ARG2 is a pointer to
* the initial PCR register value to use.
*/
PERFCTR_ON,
/* Disable UltraSparc performance counters. The PCR is written
* with zero and the user counter accumulator pointers and
* working PCR register value are forgotten.
*/
PERFCTR_OFF,
/* Add current D0 and D1 PIC values into user pointers given
* in PERFCTR_ON operation. The PIC is cleared before returning.
*/
PERFCTR_READ,
/* Clear the PIC register. */
PERFCTR_CLRPIC,
/* Begin using a new PCR value, the pointer to which is passed
* in ARG0. The PIC is also cleared after the new PCR value is
* written.
*/
PERFCTR_SETPCR,
/* Store in pointer given in ARG0 the current PCR register value
* being used.
*/
PERFCTR_GETPCR
};
/* I don't want the kernel's namespace to be polluted with this
* stuff when this file is included. --DaveM
*/
#ifndef __KERNEL__
#define PRIV 0x00000001
#define SYS 0x00000002
#define USR 0x00000004
/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
#define CYCLE_CNT 0x00000000
#define INSTR_CNT 0x00000010
#define DISPATCH0_IC_MISS 0x00000020
#define DISPATCH0_STOREBUF 0x00000030
#define IC_REF 0x00000080
#define DC_RD 0x00000090
#define DC_WR 0x000000A0
#define LOAD_USE 0x000000B0
#define EC_REF 0x000000C0
#define EC_WRITE_HIT_RDO 0x000000D0
#define EC_SNOOP_INV 0x000000E0
#define EC_RD_HIT 0x000000F0
/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
#define US3_CYCLE_CNT 0x00000000
#define US3_INSTR_CNT 0x00000010
#define US3_DISPATCH0_IC_MISS 0x00000020
#define US3_DISPATCH0_BR_TGT 0x00000030
#define US3_DISPATCH0_2ND_BR 0x00000040
#define US3_RSTALL_STOREQ 0x00000050
#define US3_RSTALL_IU_USE 0x00000060
#define US3_IC_REF 0x00000080
#define US3_DC_RD 0x00000090
#define US3_DC_WR 0x000000a0
#define US3_EC_REF 0x000000c0
#define US3_EC_WR_HIT_RTO 0x000000d0
#define US3_EC_SNOOP_INV 0x000000e0
#define US3_EC_RD_MISS 0x000000f0
#define US3_PC_PORT0_RD 0x00000100
#define US3_SI_SNOOP 0x00000110
#define US3_SI_CIQ_FLOW 0x00000120
#define US3_SI_OWNED 0x00000130
#define US3_SW_COUNT_0 0x00000140
#define US3_IU_BR_MISS_TAKEN 0x00000150
#define US3_IU_BR_COUNT_TAKEN 0x00000160
#define US3_DISP_RS_MISPRED 0x00000170
#define US3_FA_PIPE_COMPL 0x00000180
#define US3_MC_READS_0 0x00000200
#define US3_MC_READS_1 0x00000210
#define US3_MC_READS_2 0x00000220
#define US3_MC_READS_3 0x00000230
#define US3_MC_STALLS_0 0x00000240
#define US3_MC_STALLS_2 0x00000250
/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
#define CYCLE_CNT_D1 0x00000000
#define INSTR_CNT_D1 0x00000800
#define DISPATCH0_IC_MISPRED 0x00001000
#define DISPATCH0_FP_USE 0x00001800
#define IC_HIT 0x00004000
#define DC_RD_HIT 0x00004800
#define DC_WR_HIT 0x00005000
#define LOAD_USE_RAW 0x00005800
#define EC_HIT 0x00006000
#define EC_WB 0x00006800
#define EC_SNOOP_CB 0x00007000
#define EC_IT_HIT 0x00007800
/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
#define US3_CYCLE_CNT_D1 0x00000000
#define US3_INSTR_CNT_D1 0x00000800
#define US3_DISPATCH0_MISPRED 0x00001000
#define US3_IC_MISS_CANCELLED 0x00001800
#define US3_RE_ENDIAN_MISS 0x00002000
#define US3_RE_FPU_BYPASS 0x00002800
#define US3_RE_DC_MISS 0x00003000
#define US3_RE_EC_MISS 0x00003800
#define US3_IC_MISS 0x00004000
#define US3_DC_RD_MISS 0x00004800
#define US3_DC_WR_MISS 0x00005000
#define US3_RSTALL_FP_USE 0x00005800
#define US3_EC_MISSES 0x00006000
#define US3_EC_WB 0x00006800
#define US3_EC_SNOOP_CB 0x00007000
#define US3_EC_IC_MISS 0x00007800
#define US3_RE_PC_MISS 0x00008000
#define US3_ITLB_MISS 0x00008800
#define US3_DTLB_MISS 0x00009000
#define US3_WC_MISS 0x00009800
#define US3_WC_SNOOP_CB 0x0000a000
#define US3_WC_SCRUBBED 0x0000a800
#define US3_WC_WB_WO_READ 0x0000b000
#define US3_PC_SOFT_HIT 0x0000c000
#define US3_PC_SNOOP_INV 0x0000c800
#define US3_PC_HARD_HIT 0x0000d000
#define US3_PC_PORT1_RD 0x0000d800
#define US3_SW_COUNT_1 0x0000e000
#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
#define US3_PC_MS_MISSES 0x0000f800
#define US3_MC_WRITES_0 0x00010800
#define US3_MC_WRITES_1 0x00011000
#define US3_MC_WRITES_2 0x00011800
#define US3_MC_WRITES_3 0x00012000
#define US3_MC_STALLS_1 0x00012800
#define US3_MC_STALLS_3 0x00013000
#define US3_RE_RAW_MISS 0x00013800
#define US3_FM_PIPE_COMPLETION 0x00014000
struct vcounter_struct {
unsigned long long vcnt0;
unsigned long long vcnt1;
};
#endif /* !(__KERNEL__) */
#endif /* !(PERF_COUNTER_API) */

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/* $Id: pgalloc.h,v 1.16 2001/12/21 04:56:17 davem Exp $ */
#ifndef _SPARC_PGALLOC_H
#define _SPARC_PGALLOC_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/page.h>
#include <asm/btfixup.h>
struct page;
extern struct pgtable_cache_struct {
unsigned long *pgd_cache;
unsigned long *pte_cache;
unsigned long pgtable_cache_sz;
unsigned long pgd_cache_sz;
} pgt_quicklists;
#define pgd_quicklist (pgt_quicklists.pgd_cache)
#define pmd_quicklist ((unsigned long *)0)
#define pte_quicklist (pgt_quicklists.pte_cache)
#define pgtable_cache_size (pgt_quicklists.pgtable_cache_sz)
#define pgd_cache_size (pgt_quicklists.pgd_cache_sz)
extern void check_pgt_cache(void);
BTFIXUPDEF_CALL(void, do_check_pgt_cache, int, int)
#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
#define get_pgd_fast() BTFIXUP_CALL(get_pgd_fast)()
BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
#define free_pgd_fast(pgd) BTFIXUP_CALL(free_pgd_fast)(pgd)
#define pgd_free(pgd) free_pgd_fast(pgd)
#define pgd_alloc(mm) get_pgd_fast()
BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD)
BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
#define pmd_alloc_one(mm, address) BTFIXUP_CALL(pmd_alloc_one)(mm, address)
BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
#define free_pmd_fast(pmd) BTFIXUP_CALL(free_pmd_fast)(pmd)
#define pmd_free(pmd) free_pmd_fast(pmd)
#define __pmd_free_tlb(tlb, pmd) pmd_free(pmd)
BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE)
BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
BTFIXUPDEF_CALL(struct page *, pte_alloc_one, struct mm_struct *, unsigned long)
#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address)
BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
#define pte_free_kernel(pte) BTFIXUP_CALL(free_pte_fast)(pte)
BTFIXUPDEF_CALL(void, pte_free, struct page *)
#define pte_free(pte) BTFIXUP_CALL(pte_free)(pte)
#define __pte_free_tlb(tlb, pte) pte_free(pte)
#endif /* _SPARC_PGALLOC_H */

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/* $Id: pgtable.h,v 1.110 2001/12/21 04:56:17 davem Exp $ */
#ifndef _SPARC_PGTABLE_H
#define _SPARC_PGTABLE_H
/* asm-sparc/pgtable.h: Defines and functions used to work
* with Sparc page tables.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
*/
#include <asm-generic/4level-fixup.h>
#include <linux/config.h>
#include <linux/spinlock.h>
#include <linux/swap.h>
#include <asm/types.h>
#ifdef CONFIG_SUN4
#include <asm/pgtsun4.h>
#else
#include <asm/pgtsun4c.h>
#endif
#include <asm/pgtsrmmu.h>
#include <asm/vac-ops.h>
#include <asm/oplib.h>
#include <asm/btfixup.h>
#include <asm/system.h>
#ifndef __ASSEMBLY__
struct vm_area_struct;
struct page;
extern void load_mmu(void);
extern unsigned long calc_highpages(void);
BTFIXUPDEF_SIMM13(pgdir_shift)
BTFIXUPDEF_SETHI(pgdir_size)
BTFIXUPDEF_SETHI(pgdir_mask)
BTFIXUPDEF_SIMM13(ptrs_per_pmd)
BTFIXUPDEF_SIMM13(ptrs_per_pgd)
BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
#define pte_ERROR(e) __builtin_trap()
#define pmd_ERROR(e) __builtin_trap()
#define pgd_ERROR(e) __builtin_trap()
BTFIXUPDEF_INT(page_none)
BTFIXUPDEF_INT(page_shared)
BTFIXUPDEF_INT(page_copy)
BTFIXUPDEF_INT(page_readonly)
BTFIXUPDEF_INT(page_kernel)
#define PMD_SHIFT SUN4C_PMD_SHIFT
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
#define PGDIR_SHIFT BTFIXUP_SIMM13(pgdir_shift)
#define PGDIR_SIZE BTFIXUP_SETHI(pgdir_size)
#define PGDIR_MASK BTFIXUP_SETHI(pgdir_mask)
#define PTRS_PER_PTE 1024
#define PTRS_PER_PMD BTFIXUP_SIMM13(ptrs_per_pmd)
#define PTRS_PER_PGD BTFIXUP_SIMM13(ptrs_per_pgd)
#define USER_PTRS_PER_PGD BTFIXUP_SIMM13(user_ptrs_per_pgd)
#define FIRST_USER_PGD_NR 0
#define PTE_SIZE (PTRS_PER_PTE*4)
#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none))
#define PAGE_SHARED __pgprot(BTFIXUP_INT(page_shared))
#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy))
#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly))
extern unsigned long page_kernel;
#ifdef MODULE
#define PAGE_KERNEL page_kernel
#else
#define PAGE_KERNEL __pgprot(BTFIXUP_INT(page_kernel))
#endif
/* Top-level page directory */
extern pgd_t swapper_pg_dir[1024];
/* Page table for 0-4MB for everybody, on the Sparc this
* holds the same as on the i386.
*/
extern pte_t pg0[1024];
extern pte_t pg1[1024];
extern pte_t pg2[1024];
extern pte_t pg3[1024];
extern unsigned long ptr_in_current_pgd;
/* Here is a trick, since mmap.c need the initializer elements for
* protection_map[] to be constant at compile time, I set the following
* to all zeros. I set it to the real values after I link in the
* appropriate MMU page table routines at boot time.
*/
#define __P000 __pgprot(0)
#define __P001 __pgprot(0)
#define __P010 __pgprot(0)
#define __P011 __pgprot(0)
#define __P100 __pgprot(0)
#define __P101 __pgprot(0)
#define __P110 __pgprot(0)
#define __P111 __pgprot(0)
#define __S000 __pgprot(0)
#define __S001 __pgprot(0)
#define __S010 __pgprot(0)
#define __S011 __pgprot(0)
#define __S100 __pgprot(0)
#define __S101 __pgprot(0)
#define __S110 __pgprot(0)
#define __S111 __pgprot(0)
extern int num_contexts;
/* First physical page can be anywhere, the following is needed so that
* va-->pa and vice versa conversions work properly without performance
* hit for all __pa()/__va() operations.
*/
extern unsigned long phys_base;
extern unsigned long pfn_base;
/*
* BAD_PAGETABLE is used when we need a bogus page-table, while
* BAD_PAGE is used for a bogus page.
*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
extern pte_t * __bad_pagetable(void);
extern pte_t __bad_page(void);
extern unsigned long empty_zero_page;
#define BAD_PAGETABLE __bad_pagetable()
#define BAD_PAGE __bad_page()
#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
/*
*/
BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page, pgd_t)
#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
#define pgd_page(pgd) BTFIXUP_CALL(pgd_page)(pgd)
BTFIXUPDEF_SETHI(none_mask)
BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
BTFIXUPDEF_CALL(int, pte_read, pte_t)
extern __inline__ int pte_none(pte_t pte)
{
return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
}
#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
#define pte_read(pte) BTFIXUP_CALL(pte_read)(pte)
BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
extern __inline__ int pmd_none(pmd_t pmd)
{
return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
}
#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
BTFIXUPDEF_HALF(pte_writei)
BTFIXUPDEF_HALF(pte_dirtyi)
BTFIXUPDEF_HALF(pte_youngi)
extern int pte_write(pte_t pte) __attribute_const__;
extern __inline__ int pte_write(pte_t pte)
{
return pte_val(pte) & BTFIXUP_HALF(pte_writei);
}
extern int pte_dirty(pte_t pte) __attribute_const__;
extern __inline__ int pte_dirty(pte_t pte)
{
return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
}
extern int pte_young(pte_t pte) __attribute_const__;
extern __inline__ int pte_young(pte_t pte)
{
return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
}
/*
* The following only work if pte_present() is not true.
*/
BTFIXUPDEF_HALF(pte_filei)
extern int pte_file(pte_t pte) __attribute_const__;
extern __inline__ int pte_file(pte_t pte)
{
return pte_val(pte) & BTFIXUP_HALF(pte_filei);
}
/*
*/
BTFIXUPDEF_HALF(pte_wrprotecti)
BTFIXUPDEF_HALF(pte_mkcleani)
BTFIXUPDEF_HALF(pte_mkoldi)
extern pte_t pte_wrprotect(pte_t pte) __attribute_const__;
extern __inline__ pte_t pte_wrprotect(pte_t pte)
{
return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
}
extern pte_t pte_mkclean(pte_t pte) __attribute_const__;
extern __inline__ pte_t pte_mkclean(pte_t pte)
{
return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
}
extern pte_t pte_mkold(pte_t pte) __attribute_const__;
extern __inline__ pte_t pte_mkold(pte_t pte)
{
return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
}
BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
#define page_pte_prot(page, prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
BTFIXUPDEF_CALL(unsigned long, pte_pfn, pte_t)
#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
BTFIXUPDEF_INT(pte_modify_mask)
extern pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
extern __inline__ pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
pgprot_val(newprot));
}
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
/* to find an entry in a page-table-directory */
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
/* Find an entry in the second-level page table.. */
BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
/* Find an entry in the third-level page table.. */
BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
/*
* This shortcut works on sun4m (and sun4d) because the nocache area is static,
* and sun4c is guaranteed to have no highmem anyway.
*/
#define pte_offset_map(d, a) pte_offset_kernel(d,a)
#define pte_offset_map_nested(d, a) pte_offset_kernel(d,a)
#define pte_unmap(pte) do{}while(0)
#define pte_unmap_nested(pte) do{}while(0)
/* The permissions for pgprot_val to make a page mapped on the obio space */
extern unsigned int pg_iobits;
/* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
struct seq_file;
BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
/* Fault handler stuff... */
#define FAULT_CODE_PROT 0x1
#define FAULT_CODE_WRITE 0x2
#define FAULT_CODE_USER 0x4
BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
unsigned long, unsigned int)
BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
extern int invalid_segment;
/* Encode and de-code a swap entry */
BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x)
#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x)
#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
/* file-offset-in-pte helpers */
BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
/*
* This is made a constant because mm/fremap.c required a constant.
* Note that layout of these bits is different between sun4c.c and srmmu.c.
*/
#define PTE_FILE_MAX_BITS 24
/*
*/
struct ctx_list {
struct ctx_list *next;
struct ctx_list *prev;
unsigned int ctx_number;
struct mm_struct *ctx_mm;
};
extern struct ctx_list *ctx_list_pool; /* Dynamically allocated */
extern struct ctx_list ctx_free; /* Head of free list */
extern struct ctx_list ctx_used; /* Head of used contexts list */
#define NO_CONTEXT -1
extern __inline__ void remove_from_ctx_list(struct ctx_list *entry)
{
entry->next->prev = entry->prev;
entry->prev->next = entry->next;
}
extern __inline__ void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
{
entry->next = head;
(entry->prev = head->prev)->next = entry;
head->prev = entry;
}
#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
extern __inline__ unsigned long
__get_phys (unsigned long addr)
{
switch (sparc_cpu_model){
case sun4:
case sun4c:
return sun4c_get_pte (addr) << PAGE_SHIFT;
case sun4m:
case sun4d:
return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
default:
return 0;
}
}
extern __inline__ int
__get_iospace (unsigned long addr)
{
switch (sparc_cpu_model){
case sun4:
case sun4c:
return -1; /* Don't check iospace on sun4c */
case sun4m:
case sun4d:
return (srmmu_get_pte (addr) >> 28);
default:
return -1;
}
}
extern unsigned long *sparc_valid_addr_bitmap;
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) \
(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
extern int io_remap_page_range(struct vm_area_struct *vma,
unsigned long from, unsigned long to,
unsigned long size, pgprot_t prot, int space);
extern int io_remap_pfn_range(struct vm_area_struct *vma,
unsigned long from, unsigned long pfn,
unsigned long size, pgprot_t prot);
/*
* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
* its high 4 bits. These macros/functions put it there or get it from there.
*/
#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
#include <asm-generic/pgtable.h>
#endif /* !(__ASSEMBLY__) */
/* We provide our own get_unmapped_area to cope with VA holes for userland */
#define HAVE_ARCH_UNMAPPED_AREA
/*
* No page table caches to initialise
*/
#define pgtable_cache_init() do { } while (0)
#endif /* !(_SPARC_PGTABLE_H) */

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/* $Id: pgtsrmmu.h,v 1.31 2000/07/16 21:48:52 anton Exp $
* pgtsrmmu.h: SRMMU page table defines and code.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_PGTSRMMU_H
#define _SPARC_PGTSRMMU_H
#include <asm/page.h>
#ifdef __ASSEMBLY__
#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
#endif
/* Number of contexts is implementation-dependent; 64k is the most we support */
#define SRMMU_MAX_CONTEXTS 65536
/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
#define SRMMU_REAL_PMD_SHIFT 18
#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define SRMMU_PGDIR_SHIFT 24
#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
#define SRMMU_REAL_PTRS_PER_PTE 64
#define SRMMU_REAL_PTRS_PER_PMD 64
#define SRMMU_PTRS_PER_PGD 256
#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
/*
* To support pagetables in highmem, Linux introduces APIs which
* return struct page* and generally manipulate page tables when
* they are not mapped into kernel space. Our hardware page tables
* are smaller than pages. We lump hardware tabes into big, page sized
* software tables.
*
* PMD_SHIFT determines the size of the area a second-level page table entry
* can map, and our pmd_t is 16 times larger than normal. The values which
* were once defined here are now generic for 4c and srmmu, so they're
* found in pgtable.h.
*/
#define SRMMU_PTRS_PER_PMD 4
/* Definition of the values in the ET field of PTD's and PTE's */
#define SRMMU_ET_MASK 0x3
#define SRMMU_ET_INVALID 0x0
#define SRMMU_ET_PTD 0x1
#define SRMMU_ET_PTE 0x2
#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
/* Physical page extraction from PTP's and PTE's. */
#define SRMMU_CTX_PMASK 0xfffffff0
#define SRMMU_PTD_PMASK 0xfffffff0
#define SRMMU_PTE_PMASK 0xffffff00
/* The pte non-page bits. Some notes:
* 1) cache, dirty, valid, and ref are frobbable
* for both supervisor and user pages.
* 2) exec and write will only give the desired effect
* on user pages
* 3) use priv and priv_readonly for changing the
* characteristics of supervisor ptes
*/
#define SRMMU_CACHE 0x80
#define SRMMU_DIRTY 0x40
#define SRMMU_REF 0x20
#define SRMMU_NOREAD 0x10
#define SRMMU_EXEC 0x08
#define SRMMU_WRITE 0x04
#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
#define SRMMU_PRIV 0x1c
#define SRMMU_PRIV_RDONLY 0x18
#define SRMMU_FILE 0x40 /* Implemented in software */
#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
/* SRMMU swap entry encoding
*
* We use 5 bits for the type and 19 for the offset. This gives us
* 32 swapfiles of 4GB each. Encoding looks like:
*
* oooooooooooooooooootttttRRRRRRRR
* fedcba9876543210fedcba9876543210
*
* The bottom 8 bits are reserved for protection and status bits, especially
* FILE and PRESENT.
*/
#define SRMMU_SWP_TYPE_MASK 0x1f
#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
#define SRMMU_SWP_OFF_MASK 0x7ffff
#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
/* Some day I will implement true fine grained access bits for
* user pages because the SRMMU gives us the capabilities to
* enforce all the protection levels that vma's can have.
* XXX But for now...
*/
#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
SRMMU_PRIV | SRMMU_REF)
#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
SRMMU_EXEC | SRMMU_REF)
#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
SRMMU_EXEC | SRMMU_REF)
#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
SRMMU_DIRTY | SRMMU_REF)
/* SRMMU Register addresses in ASI 0x4. These are valid for all
* current SRMMU implementations that exist.
*/
#define SRMMU_CTRL_REG 0x00000000
#define SRMMU_CTXTBL_PTR 0x00000100
#define SRMMU_CTX_REG 0x00000200
#define SRMMU_FAULT_STATUS 0x00000300
#define SRMMU_FAULT_ADDR 0x00000400
#define WINDOW_FLUSH(tmp1, tmp2) \
mov 0, tmp1; \
98: ld [%g6 + TI_UWINMASK], tmp2; \
orcc %g0, tmp2, %g0; \
add tmp1, 1, tmp1; \
bne 98b; \
save %sp, -64, %sp; \
99: subcc tmp1, 1, tmp1; \
bne 99b; \
restore %g0, %g0, %g0;
#ifndef __ASSEMBLY__
/* This makes sense. Honest it does - Anton */
/* XXX Yes but it's ugly as sin. FIXME. -KMW */
extern void *srmmu_nocache_pool;
#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
/* Accessing the MMU control register. */
extern __inline__ unsigned int srmmu_get_mmureg(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
"=r" (retval) :
"i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ void srmmu_set_mmureg(unsigned long regval)
{
__asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
"r" (regval), "i" (ASI_M_MMUREGS) : "memory");
}
extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
{
paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (paddr), "r" (SRMMU_CTXTBL_PTR),
"i" (ASI_M_MMUREGS) :
"memory");
}
extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_CTXTBL_PTR),
"i" (ASI_M_MMUREGS));
return (retval & SRMMU_CTX_PMASK) << 4;
}
extern __inline__ void srmmu_set_context(int context)
{
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (context), "r" (SRMMU_CTX_REG),
"i" (ASI_M_MMUREGS) : "memory");
}
extern __inline__ int srmmu_get_context(void)
{
register int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_CTX_REG),
"i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ unsigned int srmmu_get_fstatus(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ unsigned int srmmu_get_faddr(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
return retval;
}
/* This is guaranteed on all SRMMU's. */
extern __inline__ void srmmu_flush_whole_tlb(void)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (0x400), /* Flush entire TLB!! */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
/* These flush types are not available on all chips... */
extern __inline__ void srmmu_flush_tlb_ctx(void)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (0x300), /* Flush TLB ctx.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
{
addr &= SRMMU_PGDIR_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (addr | 0x200), /* Flush TLB region.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
{
addr &= SRMMU_REAL_PMD_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (addr | 0x100), /* Flush TLB segment.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
{
page &= PAGE_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (page), /* Flush TLB page.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
{
unsigned long retval;
vaddr &= PAGE_MASK;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
return retval;
}
extern __inline__ int
srmmu_get_pte (unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
"=r" (entry):
"r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
return entry;
}
extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_PGTSRMMU_H) */

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/* $Id: pgtsun4.h,v 1.5 2000/06/05 06:08:46 anton Exp $
* pgtsun4.h: Sun4 specific pgtable.h defines and code.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
*/
#ifndef _SPARC_PGTSUN4C_H
#define _SPARC_PGTSUN4C_H
#include <asm/contregs.h>
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define SUN4C_PMD_SHIFT 23
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define SUN4C_PGDIR_SHIFT 23
#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
/* To represent how the sun4c mmu really lays things out. */
#define SUN4C_REAL_PGDIR_SHIFT 18
#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
/* 19 bit PFN on sun4 */
#define SUN4C_PFN_MASK 0x7ffff
/* Don't increase these unless the structures in sun4c.c are fixed */
#define SUN4C_MAX_SEGMAPS 256
#define SUN4C_MAX_CONTEXTS 16
/*
* To be efficient, and not have to worry about allocating such
* a huge pgd, we make the kernel sun4c tables each hold 1024
* entries and the pgd similarly just like the i386 tables.
*/
#define SUN4C_PTRS_PER_PTE 1024
#define SUN4C_PTRS_PER_PMD 1
#define SUN4C_PTRS_PER_PGD 1024
/*
* Sparc SUN4C pte fields.
*/
#define _SUN4C_PAGE_VALID 0x80000000
#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
#define _SUN4C_PAGE_DIRTY 0x40000000
#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
_SUN4C_PAGE_ACCESSED)
#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
_SUN4C_PAGE_MODIFIED)
#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
_SUN4C_PAGE_WRITE)
#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
_SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
/* SUN4C swap entry encoding
*
* We use 5 bits for the type and 19 for the offset. This gives us
* 32 swapfiles of 4GB each. Encoding looks like:
*
* RRRRRRRRooooooooooooooooooottttt
* fedcba9876543210fedcba9876543210
*
* The top 8 bits are reserved for protection and status bits, especially
* FILE and PRESENT.
*/
#define SUN4C_SWP_TYPE_MASK 0x1f
#define SUN4C_SWP_OFF_MASK 0x7ffff
#define SUN4C_SWP_OFF_SHIFT 5
#ifndef __ASSEMBLY__
static inline unsigned long sun4c_get_synchronous_error(void)
{
unsigned long sync_err;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (sync_err) :
"r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
return sync_err;
}
static inline unsigned long sun4c_get_synchronous_address(void)
{
unsigned long sync_addr;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (sync_addr) :
"r" (AC_SYNC_VA), "i" (ASI_CONTROL));
return sync_addr;
}
/* SUN4 pte, segmap, and context manipulation */
static inline unsigned long sun4c_get_segmap(unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
"=r" (entry) :
"r" (addr), "i" (ASI_SEGMAP));
return entry;
}
static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
{
__asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
"r" (addr), "r" (entry),
"i" (ASI_SEGMAP)
: "memory");
}
static inline unsigned long sun4c_get_pte(unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
"=r" (entry) :
"r" (addr), "i" (ASI_PTE));
return entry;
}
static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
{
__asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
"r" (addr),
"r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
: "memory");
}
static inline int sun4c_get_context(void)
{
register int ctx;
__asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
"=r" (ctx) :
"r" (AC_CONTEXT), "i" (ASI_CONTROL));
return ctx;
}
static inline int sun4c_set_context(int ctx)
{
__asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
"r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
: "memory");
return ctx;
}
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_PGTSUN4_H) */

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/* $Id: pgtsun4c.h,v 1.37 2000/06/05 06:08:46 anton Exp $
* pgtsun4c.h: Sun4c specific pgtable.h defines and code.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_PGTSUN4C_H
#define _SPARC_PGTSUN4C_H
#include <asm/contregs.h>
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define SUN4C_PMD_SHIFT 22
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define SUN4C_PGDIR_SHIFT 22
#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
/* To represent how the sun4c mmu really lays things out. */
#define SUN4C_REAL_PGDIR_SHIFT 18
#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
/* 16 bit PFN on sun4c */
#define SUN4C_PFN_MASK 0xffff
/* Don't increase these unless the structures in sun4c.c are fixed */
#define SUN4C_MAX_SEGMAPS 256
#define SUN4C_MAX_CONTEXTS 16
/*
* To be efficient, and not have to worry about allocating such
* a huge pgd, we make the kernel sun4c tables each hold 1024
* entries and the pgd similarly just like the i386 tables.
*/
#define SUN4C_PTRS_PER_PTE 1024
#define SUN4C_PTRS_PER_PMD 1
#define SUN4C_PTRS_PER_PGD 1024
/*
* Sparc SUN4C pte fields.
*/
#define _SUN4C_PAGE_VALID 0x80000000
#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
#define _SUN4C_PAGE_DIRTY 0x40000000
#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
_SUN4C_PAGE_ACCESSED)
#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
_SUN4C_PAGE_MODIFIED)
#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
_SUN4C_PAGE_WRITE)
#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
_SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
/* SUN4C swap entry encoding
*
* We use 5 bits for the type and 19 for the offset. This gives us
* 32 swapfiles of 4GB each. Encoding looks like:
*
* RRRRRRRRooooooooooooooooooottttt
* fedcba9876543210fedcba9876543210
*
* The top 8 bits are reserved for protection and status bits, especially
* FILE and PRESENT.
*/
#define SUN4C_SWP_TYPE_MASK 0x1f
#define SUN4C_SWP_OFF_MASK 0x7ffff
#define SUN4C_SWP_OFF_SHIFT 5
#ifndef __ASSEMBLY__
static inline unsigned long sun4c_get_synchronous_error(void)
{
unsigned long sync_err;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (sync_err) :
"r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
return sync_err;
}
static inline unsigned long sun4c_get_synchronous_address(void)
{
unsigned long sync_addr;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (sync_addr) :
"r" (AC_SYNC_VA), "i" (ASI_CONTROL));
return sync_addr;
}
/* SUN4C pte, segmap, and context manipulation */
static inline unsigned long sun4c_get_segmap(unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
"=r" (entry) :
"r" (addr), "i" (ASI_SEGMAP));
return entry;
}
static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
{
__asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
"r" (addr), "r" (entry),
"i" (ASI_SEGMAP)
: "memory");
}
static inline unsigned long sun4c_get_pte(unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
"=r" (entry) :
"r" (addr), "i" (ASI_PTE));
return entry;
}
static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
{
__asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
"r" (addr),
"r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
: "memory");
}
static inline int sun4c_get_context(void)
{
register int ctx;
__asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
"=r" (ctx) :
"r" (AC_CONTEXT), "i" (ASI_CONTROL));
return ctx;
}
static inline int sun4c_set_context(int ctx)
{
__asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
"r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
: "memory");
return ctx;
}
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_PGTSUN4C_H) */

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#ifndef __SPARC_POLL_H
#define __SPARC_POLL_H
#define POLLIN 1
#define POLLPRI 2
#define POLLOUT 4
#define POLLERR 8
#define POLLHUP 16
#define POLLNVAL 32
#define POLLRDNORM 64
#define POLLWRNORM POLLOUT
#define POLLRDBAND 128
#define POLLWRBAND 256
#define POLLMSG 512
#define POLLREMOVE 1024
struct pollfd {
int fd;
short events;
short revents;
};
#endif

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#ifndef __ARCH_SPARC_POSIX_TYPES_H
#define __ARCH_SPARC_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef long int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_umode_t;
typedef short __kernel_nlink_t;
typedef long __kernel_daddr_t;
typedef long __kernel_off_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
typedef unsigned short __kernel_old_dev_t;
typedef int __kernel_clockid_t;
typedef int __kernel_timer_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
}
/*
* This will unroll the loop for the normal constant cases (8 or 32 longs,
* for 256 and 1024-bit fd_sets respectively)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *p)
{
unsigned long *tmp = p->fds_bits;
int i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 32:
tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
return;
case 16:
tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
return;
case 8:
tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
return;
case 4:
tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
return;
}
}
i = __FDSET_LONGS;
while (i) {
i--;
*tmp = 0;
tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */

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/* $Id: processor.h,v 1.83 2001/10/08 09:32:13 davem Exp $
* include/asm-sparc/processor.h
*
* Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef __ASM_SPARC_PROCESSOR_H
#define __ASM_SPARC_PROCESSOR_H
/*
* Sparc32 implementation of macro that returns current
* instruction pointer ("program counter").
*/
#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
#include <linux/a.out.h>
#include <asm/psr.h>
#include <asm/ptrace.h>
#include <asm/head.h>
#include <asm/signal.h>
#include <asm/segment.h>
#include <asm/btfixup.h>
#include <asm/page.h>
/*
* The sparc has no problems with write protection
*/
#define wp_works_ok 1
#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
/* Whee, this is STACK_TOP + PAGE_SIZE and the lowest kernel address too...
* That one page is used to protect kernel from intruders, so that
* we can make our access_ok test faster
*/
#define TASK_SIZE PAGE_OFFSET
struct task_struct;
#ifdef __KERNEL__
struct fpq {
unsigned long *insn_addr;
unsigned long insn;
};
#endif
typedef struct {
int seg;
} mm_segment_t;
/* The Sparc processor specific thread struct. */
struct thread_struct {
struct pt_regs *kregs;
unsigned int _pad1;
/* Special child fork kpsr/kwim values. */
unsigned long fork_kpsr __attribute__ ((aligned (8)));
unsigned long fork_kwim;
/* Floating point regs */
unsigned long float_regs[32] __attribute__ ((aligned (8)));
unsigned long fsr;
unsigned long fpqdepth;
struct fpq fpqueue[16];
unsigned long flags;
mm_segment_t current_ds;
struct exec core_exec; /* just what it says. */
int new_signal;
};
#define SPARC_FLAG_KTHREAD 0x1 /* task is a kernel thread */
#define SPARC_FLAG_UNALIGNED 0x2 /* is allowed to do unaligned accesses */
#define INIT_THREAD { \
.flags = SPARC_FLAG_KTHREAD, \
.current_ds = KERNEL_DS, \
}
/* Return saved PC of a blocked thread. */
extern unsigned long thread_saved_pc(struct task_struct *t);
/* Do necessary setup to start up a newly executed thread. */
extern __inline__ void start_thread(struct pt_regs * regs, unsigned long pc,
unsigned long sp)
{
register unsigned long zero asm("g1");
regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;
regs->pc = ((pc & (~3)) - 4);
regs->npc = regs->pc + 4;
regs->y = 0;
zero = 0;
__asm__ __volatile__("std\t%%g0, [%0 + %3 + 0x00]\n\t"
"std\t%%g0, [%0 + %3 + 0x08]\n\t"
"std\t%%g0, [%0 + %3 + 0x10]\n\t"
"std\t%%g0, [%0 + %3 + 0x18]\n\t"
"std\t%%g0, [%0 + %3 + 0x20]\n\t"
"std\t%%g0, [%0 + %3 + 0x28]\n\t"
"std\t%%g0, [%0 + %3 + 0x30]\n\t"
"st\t%1, [%0 + %3 + 0x38]\n\t"
"st\t%%g0, [%0 + %3 + 0x3c]"
: /* no outputs */
: "r" (regs),
"r" (sp - sizeof(struct reg_window)),
"r" (zero),
"i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))
: "memory");
}
/* Free all resources held by a thread. */
#define release_thread(tsk) do { } while(0)
extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
/* Prepare to copy thread state - unlazy all lazy status */
#define prepare_to_copy(tsk) do { } while (0)
extern unsigned long get_wchan(struct task_struct *);
#define KSTK_EIP(tsk) ((tsk)->thread.kregs->pc)
#define KSTK_ESP(tsk) ((tsk)->thread.kregs->u_regs[UREG_FP])
#ifdef __KERNEL__
extern struct task_struct *last_task_used_math;
#define cpu_relax() barrier()
#endif
#endif /* __ASM_SPARC_PROCESSOR_H */

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/* $Id: psr.h,v 1.15 1997/10/04 08:54:22 ecd Exp $
* psr.h: This file holds the macros for masking off various parts of
* the processor status register on the Sparc. This is valid
* for Version 8. On the V9 this is renamed to the PSTATE
* register and its members are accessed as fields like
* PSTATE.PRIV for the current CPU privilege level.
*
* Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef __LINUX_SPARC_PSR_H
#define __LINUX_SPARC_PSR_H
/* The Sparc PSR fields are laid out as the following:
*
* ------------------------------------------------------------------------
* | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
* | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
* ------------------------------------------------------------------------
*/
#define PSR_CWP 0x0000001f /* current window pointer */
#define PSR_ET 0x00000020 /* enable traps field */
#define PSR_PS 0x00000040 /* previous privilege level */
#define PSR_S 0x00000080 /* current privilege level */
#define PSR_PIL 0x00000f00 /* processor interrupt level */
#define PSR_EF 0x00001000 /* enable floating point */
#define PSR_EC 0x00002000 /* enable co-processor */
#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_C 0x00100000 /* carry bit */
#define PSR_V 0x00200000 /* overflow bit */
#define PSR_Z 0x00400000 /* zero bit */
#define PSR_N 0x00800000 /* negative bit */
#define PSR_VERS 0x0f000000 /* cpu-version field */
#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
/* Get the %psr register. */
extern __inline__ unsigned int get_psr(void)
{
unsigned int psr;
__asm__ __volatile__(
"rd %%psr, %0\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
: "=r" (psr)
: /* no inputs */
: "memory");
return psr;
}
extern __inline__ void put_psr(unsigned int new_psr)
{
__asm__ __volatile__(
"wr %0, 0x0, %%psr\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
: /* no outputs */
: "r" (new_psr)
: "memory", "cc");
}
/* Get the %fsr register. Be careful, make sure the floating point
* enable bit is set in the %psr when you execute this or you will
* incur a trap.
*/
extern unsigned int fsr_storage;
extern __inline__ unsigned int get_fsr(void)
{
unsigned int fsr = 0;
__asm__ __volatile__(
"st %%fsr, %1\n\t"
"ld %1, %0\n\t"
: "=r" (fsr)
: "m" (fsr_storage));
return fsr;
}
#endif /* !(__ASSEMBLY__) */
#endif /* (__KERNEL__) */
#endif /* !(__LINUX_SPARC_PSR_H) */

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/* $Id: ptrace.h,v 1.25 1997/03/04 16:27:25 jj Exp $ */
#ifndef _SPARC_PTRACE_H
#define _SPARC_PTRACE_H
#include <asm/psr.h>
/* This struct defines the way the registers are stored on the
* stack during a system call and basically all traps.
*/
#ifndef __ASSEMBLY__
struct pt_regs {
unsigned long psr;
unsigned long pc;
unsigned long npc;
unsigned long y;
unsigned long u_regs[16]; /* globals and ins */
};
#define UREG_G0 0
#define UREG_G1 1
#define UREG_G2 2
#define UREG_G3 3
#define UREG_G4 4
#define UREG_G5 5
#define UREG_G6 6
#define UREG_G7 7
#define UREG_I0 8
#define UREG_I1 9
#define UREG_I2 10
#define UREG_I3 11
#define UREG_I4 12
#define UREG_I5 13
#define UREG_I6 14
#define UREG_I7 15
#define UREG_WIM UREG_G0
#define UREG_FADDR UREG_G0
#define UREG_FP UREG_I6
#define UREG_RETPC UREG_I7
/* A register window */
struct reg_window {
unsigned long locals[8];
unsigned long ins[8];
};
/* A Sparc stack frame */
struct sparc_stackf {
unsigned long locals[8];
unsigned long ins[6];
struct sparc_stackf *fp;
unsigned long callers_pc;
char *structptr;
unsigned long xargs[6];
unsigned long xxargs[1];
};
#define TRACEREG_SZ sizeof(struct pt_regs)
#define STACKFRAME_SZ sizeof(struct sparc_stackf)
#ifdef __KERNEL__
#define user_mode(regs) (!((regs)->psr & PSR_PS))
#define instruction_pointer(regs) ((regs)->pc)
unsigned long profile_pc(struct pt_regs *);
extern void show_regs(struct pt_regs *);
#endif
#else /* __ASSEMBLY__ */
/* For assembly code. */
#define TRACEREG_SZ 0x50
#define STACKFRAME_SZ 0x60
#endif
/*
* The asm_offsets.h is a generated file, so we cannot include it.
* It may be OK for glibc headers, but it's utterly pointless for C code.
* The assembly code using those offsets has to include it explicitly.
*/
/* #include <asm/asm_offsets.h> */
/* These are for pt_regs. */
#define PT_PSR 0x0
#define PT_PC 0x4
#define PT_NPC 0x8
#define PT_Y 0xc
#define PT_G0 0x10
#define PT_WIM PT_G0
#define PT_G1 0x14
#define PT_G2 0x18
#define PT_G3 0x1c
#define PT_G4 0x20
#define PT_G5 0x24
#define PT_G6 0x28
#define PT_G7 0x2c
#define PT_I0 0x30
#define PT_I1 0x34
#define PT_I2 0x38
#define PT_I3 0x3c
#define PT_I4 0x40
#define PT_I5 0x44
#define PT_I6 0x48
#define PT_FP PT_I6
#define PT_I7 0x4c
/* Reg_window offsets */
#define RW_L0 0x00
#define RW_L1 0x04
#define RW_L2 0x08
#define RW_L3 0x0c
#define RW_L4 0x10
#define RW_L5 0x14
#define RW_L6 0x18
#define RW_L7 0x1c
#define RW_I0 0x20
#define RW_I1 0x24
#define RW_I2 0x28
#define RW_I3 0x2c
#define RW_I4 0x30
#define RW_I5 0x34
#define RW_I6 0x38
#define RW_I7 0x3c
/* Stack_frame offsets */
#define SF_L0 0x00
#define SF_L1 0x04
#define SF_L2 0x08
#define SF_L3 0x0c
#define SF_L4 0x10
#define SF_L5 0x14
#define SF_L6 0x18
#define SF_L7 0x1c
#define SF_I0 0x20
#define SF_I1 0x24
#define SF_I2 0x28
#define SF_I3 0x2c
#define SF_I4 0x30
#define SF_I5 0x34
#define SF_FP 0x38
#define SF_PC 0x3c
#define SF_RETP 0x40
#define SF_XARG0 0x44
#define SF_XARG1 0x48
#define SF_XARG2 0x4c
#define SF_XARG3 0x50
#define SF_XARG4 0x54
#define SF_XARG5 0x58
#define SF_XXARG 0x5c
/* Stuff for the ptrace system call */
#define PTRACE_SUNATTACH 10
#define PTRACE_SUNDETACH 11
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
#define PTRACE_SETFPREGS 15
#define PTRACE_READDATA 16
#define PTRACE_WRITEDATA 17
#define PTRACE_READTEXT 18
#define PTRACE_WRITETEXT 19
#define PTRACE_GETFPAREGS 20
#define PTRACE_SETFPAREGS 21
#define PTRACE_GETUCODE 29 /* stupid bsd-ism */
#endif /* !(_SPARC_PTRACE_H) */

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include/asm-sparc/reg.h Normal file
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/*
* linux/asm-sparc/reg.h
* Layout of the registers as expected by gdb on the Sparc
* we should replace the user.h definitions with those in
* this file, we don't even use the other
* -miguel
*
* The names of the structures, constants and aliases in this file
* have the same names as the sunos ones, some programs rely on these
* names (gdb for example).
*
*/
#ifndef __SPARC_REG_H
#define __SPARC_REG_H
struct regs {
int r_psr;
#define r_ps r_psr
int r_pc;
int r_npc;
int r_y;
int r_g1;
int r_g2;
int r_g3;
int r_g4;
int r_g5;
int r_g6;
int r_g7;
int r_o0;
int r_o1;
int r_o2;
int r_o3;
int r_o4;
int r_o5;
int r_o6;
int r_o7;
};
struct fpq {
unsigned long *addr;
unsigned long instr;
};
struct fq {
union {
double whole;
struct fpq fpq;
} FQu;
};
#define FPU_REGS_TYPE unsigned int
#define FPU_FSR_TYPE unsigned
struct fp_status {
union {
FPU_REGS_TYPE Fpu_regs[32];
double Fpu_dregs[16];
} fpu_fr;
FPU_FSR_TYPE Fpu_fsr;
unsigned Fpu_flags;
unsigned Fpu_extra;
unsigned Fpu_qcnt;
struct fq Fpu_q[16];
};
#define fpu_regs f_fpstatus.fpu_fr.Fpu_regs
#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
#define fpu_fsr f_fpstatus.Fpu_fsr
#define fpu_flags f_fpstatus.Fpu_flags
#define fpu_extra f_fpstatus.Fpu_extra
#define fpu_q f_fpstatus.Fpu_q
#define fpu_qcnt f_fpstatus.Fpu_qcnt
struct fpu {
struct fp_status f_fpstatus;
};
#endif /* __SPARC_REG_H */

26
include/asm-sparc/resource.h Normal file
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/* $Id: resource.h,v 1.12 2000/09/23 02:09:21 davem Exp $
* resource.h: Resource definitions.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_RESOURCE_H
#define _SPARC_RESOURCE_H
/*
* These two resource limit IDs have a Sparc/Linux-specific ordering,
* the rest comes from the generic header:
*/
#define RLIMIT_NOFILE 6 /* max number of open files */
#define RLIMIT_NPROC 7 /* max number of processes */
/*
* SuS says limits have to be unsigned.
* We make this unsigned, but keep the
* old value for compatibility:
*/
#define RLIM_INFINITY 0x7fffffff
#include <asm-generic/resource.h>
#endif /* !(_SPARC_RESOURCE_H) */

191
include/asm-sparc/ross.h Normal file
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/* $Id: ross.h,v 1.13 1998/01/07 06:49:11 baccala Exp $
* ross.h: Ross module specific definitions and defines.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_ROSS_H
#define _SPARC_ROSS_H
#include <asm/asi.h>
#include <asm/page.h>
/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
* field has '1111'.
*/
/* The MMU control register fields on the HyperSparc.
*
* -----------------------------------------------------------------
* |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
* -----------------------------------------------------------------
* 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
*
* Phew, lots of fields there ;-)
*
* CWR: Cache Wrapping Enabled, if one cache wrapping is on.
* SE: Snoop Enable, turns on bus snooping for cache activity if one.
* WBE: Write Buffer Enable, one turns it on.
* MID: The ModuleID of the chip for MBus transactions.
* BM: Boot-Mode. One indicates the MMU is in boot mode.
* C: Indicates whether accesses are cachable while the MMU is
* disabled.
* CS: Cache Size -- 0 = 128k, 1 = 256k
* MR: Memory Reflection, one indicates that the memory bus connected
* to the MBus supports memory reflection.
* CM: Cache Mode -- 0 = write-through, 1 = copy-back
* CE: Cache Enable -- 0 = no caching, 1 = cache is on
* NF: No Fault -- 0 = faults trap the CPU from supervisor mode
* 1 = faults from supervisor mode do not generate traps
* ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
*/
#define HYPERSPARC_CWENABLE 0x00200000
#define HYPERSPARC_SBENABLE 0x00100000
#define HYPERSPARC_WBENABLE 0x00080000
#define HYPERSPARC_MIDMASK 0x00078000
#define HYPERSPARC_BMODE 0x00004000
#define HYPERSPARC_ACENABLE 0x00002000
#define HYPERSPARC_CSIZE 0x00001000
#define HYPERSPARC_MRFLCT 0x00000800
#define HYPERSPARC_CMODE 0x00000400
#define HYPERSPARC_CENABLE 0x00000100
#define HYPERSPARC_NFAULT 0x00000002
#define HYPERSPARC_MENABLE 0x00000001
/* The ICCR instruction cache register on the HyperSparc.
*
* -----------------------------------------------
* | | FTD | ICE |
* -----------------------------------------------
* 31 1 0
*
* This register is accessed using the V8 'wrasr' and 'rdasr'
* opcodes, since not all assemblers understand them and those
* that do use different semantics I will just hard code the
* instruction with a '.word' statement.
*
* FTD: If set to one flush instructions executed during an
* instruction cache hit occurs, the corresponding line
* for said cache-hit is invalidated. If FTD is zero,
* an unimplemented 'flush' trap will occur when any
* flush is executed by the processor.
*
* ICE: If set to one, the instruction cache is enabled. If
* zero, the cache will not be used for instruction fetches.
*
* All other bits are read as zeros, and writes to them have no
* effect.
*
* Wheee, not many assemblers understand the %iccr register nor
* the generic asr r/w instructions.
*
* 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
*
* 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
*
* 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
*
* 0x b f 8 0 6 0 0 0 ! 0xbf806000
*
*/
#define HYPERSPARC_ICCR_FTD 0x00000002
#define HYPERSPARC_ICCR_ICE 0x00000001
#ifndef __ASSEMBLY__
static inline unsigned int get_ross_icr(void)
{
unsigned int icreg;
__asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
"mov %%g1, %0\n\t"
: "=r" (icreg)
: /* no inputs */
: "g1", "memory");
return icreg;
}
static inline void put_ross_icr(unsigned int icreg)
{
__asm__ __volatile__("or %%g0, %0, %%g1\n\t"
".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
"nop\n\t"
"nop\n\t"
"nop\n\t"
: /* no outputs */
: "r" (icreg)
: "g1", "memory");
return;
}
/* HyperSparc specific cache flushing. */
/* This is for the on-chip instruction cache. */
static inline void hyper_flush_whole_icache(void)
{
__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
: /* no outputs */
: "i" (ASI_M_FLUSH_IWHOLE)
: "memory");
return;
}
extern int vac_cache_size;
extern int vac_line_size;
static inline void hyper_clear_all_tags(void)
{
unsigned long addr;
for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
: /* no outputs */
: "r" (addr), "i" (ASI_M_DATAC_TAG)
: "memory");
}
static inline void hyper_flush_unconditional_combined(void)
{
unsigned long addr;
for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
: /* no outputs */
: "r" (addr), "i" (ASI_M_FLUSH_CTX)
: "memory");
}
static inline void hyper_flush_cache_user(void)
{
unsigned long addr;
for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
: /* no outputs */
: "r" (addr), "i" (ASI_M_FLUSH_USER)
: "memory");
}
static inline void hyper_flush_cache_page(unsigned long page)
{
unsigned long end;
page &= PAGE_MASK;
end = page + PAGE_SIZE;
while (page < end) {
__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
: /* no outputs */
: "r" (page), "i" (ASI_M_FLUSH_PAGE)
: "memory");
page += vac_line_size;
}
}
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_ROSS_H) */

27
include/asm-sparc/rtc.h Normal file
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/* $Id: rtc.h,v 1.2 1996/08/21 23:17:39 ecd Exp $
*
* rtc.h: Definitions for access to the Mostek real time clock
*
* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
*/
#ifndef _RTC_H
#define _RTC_H
#include <linux/ioctl.h>
struct rtc_time
{
int sec; /* Seconds (0-59) */
int min; /* Minutes (0-59) */
int hour; /* Hour (0-23) */
int dow; /* Day of the week (1-7) */
int dom; /* Day of the month (1-31) */
int month; /* Month of year (1-12) */
int year; /* Year (0-99) */
};
#define RTCGET _IOR('p', 20, struct rtc_time)
#define RTCSET _IOW('p', 21, struct rtc_time)
#endif

115
include/asm-sparc/sbi.h Normal file
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/* $Id: sbi.h,v 1.2 1998/03/09 14:04:48 jj Exp $
* sbi.h: SBI (Sbus Interface on sun4d) definitions
*
* Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
*/
#ifndef _SPARC_SBI_H
#define _SPARC_SBI_H
#include <asm/obio.h>
/* SBI */
struct sbi_regs {
/* 0x0000 */ u32 cid; /* Component ID */
/* 0x0004 */ u32 ctl; /* Control */
/* 0x0008 */ u32 status; /* Status */
u32 _unused1;
/* 0x0010 */ u32 cfg0; /* Slot0 config reg */
/* 0x0014 */ u32 cfg1; /* Slot1 config reg */
/* 0x0018 */ u32 cfg2; /* Slot2 config reg */
/* 0x001c */ u32 cfg3; /* Slot3 config reg */
/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
/* 0x0030 */ u32 intr_state; /* Interrupt state */
/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
};
#define SBI_CID 0x02800000
#define SBI_CTL 0x02800004
#define SBI_STATUS 0x02800008
#define SBI_CFG0 0x02800010
#define SBI_CFG1 0x02800014
#define SBI_CFG2 0x02800018
#define SBI_CFG3 0x0280001c
#define SBI_STB0 0x02800020
#define SBI_STB1 0x02800024
#define SBI_STB2 0x02800028
#define SBI_STB3 0x0280002c
#define SBI_INTR_STATE 0x02800030
#define SBI_INTR_TID 0x02800034
#define SBI_INTR_DIAG 0x02800038
/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
#define SBI_CFG_BURST_MASK 0x0000001e
/* How to make devid from sbi no */
#define SBI2DEVID(sbino) ((sbino<<4)|2)
/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
*
* +-------+-------+-------+-------+-------+-------+-------+-------+
* SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
* SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
* Bits 31 27 23 19 15 11 7 3 0
*/
#ifndef __ASSEMBLY__
extern __inline__ int acquire_sbi(int devid, int mask)
{
__asm__ __volatile__ ("swapa [%2] %3, %0" :
"=r" (mask) :
"0" (mask),
"r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
"i" (ASI_M_CTL));
return mask;
}
extern __inline__ void release_sbi(int devid, int mask)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (mask),
"r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
"i" (ASI_M_CTL));
}
extern __inline__ void set_sbi_tid(int devid, int targetid)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (targetid),
"r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
"i" (ASI_M_CTL));
}
extern __inline__ int get_sbi_ctl(int devid, int cfgno)
{
int cfg;
__asm__ __volatile__ ("lda [%1] %2, %0" :
"=r" (cfg) :
"r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
"i" (ASI_M_CTL));
return cfg;
}
extern __inline__ void set_sbi_ctl(int devid, int cfgno, int cfg)
{
__asm__ __volatile__ ("sta %0, [%1] %2" : :
"r" (cfg),
"r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
"i" (ASI_M_CTL));
}
#endif /* !__ASSEMBLY__ */
#endif /* !(_SPARC_SBI_H) */

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