Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
此提交包含在：
Linus Torvalds
@@ -0,0 +1,26 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Kaz Kojima
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*
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* Defitions for the address spaces of the SH-4 CPUs.
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*/
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#ifndef __ASM_CPU_SH4_ADDRSPACE_H
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#define __ASM_CPU_SH4_ADDRSPACE_H
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/* Detailed P4SEG */
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#define P4SEG_STORE_QUE (P4SEG)
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#define P4SEG_IC_ADDR 0xf0000000
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#define P4SEG_IC_DATA 0xf1000000
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#define P4SEG_ITLB_ADDR 0xf2000000
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#define P4SEG_ITLB_DATA 0xf3000000
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#define P4SEG_OC_ADDR 0xf4000000
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#define P4SEG_OC_DATA 0xf5000000
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#define P4SEG_TLB_ADDR 0xf6000000
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#define P4SEG_TLB_DATA 0xf7000000
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#define P4SEG_REG_BASE 0xff000000
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#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
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35
include/asm-sh/cpu-sh4/cache.h
一般檔案
35
include/asm-sh/cpu-sh4/cache.h
一般檔案
@@ -0,0 +1,35 @@
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/*
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* include/asm-sh/cpu-sh4/cache.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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||||
* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_CACHE_H
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#define __ASM_CPU_SH4_CACHE_H
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#define L1_CACHE_SHIFT 5
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#define CCR 0xff00001c /* Address of Cache Control Register */
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#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
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#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
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#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
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#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
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#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
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#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
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#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
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#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
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#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
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#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
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/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
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#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
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#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
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#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
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#endif /* __ASM_CPU_SH4_CACHE_H */
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@@ -0,0 +1,64 @@
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/*
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* include/asm-sh/cpu-sh4/cacheflush.h
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*
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* Copyright (C) 1999 Niibe Yutaka
|
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* Copyright (C) 2003 Paul Mundt
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*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
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#define __ASM_CPU_SH4_CACHEFLUSH_H
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/*
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* Caches are broken on SH-4 (unless we use write-through
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* caching; in which case they're only semi-broken),
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* so we need them.
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*/
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/* Page is 4K, OC size is 16K, there are four lines. */
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#define CACHE_ALIAS 0x00003000
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struct page;
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struct mm_struct;
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struct vm_area_struct;
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extern void flush_cache_all(void);
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
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extern void flush_dcache_page(struct page *pg);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void flush_cache_sigtramp(unsigned long addr);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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#define flush_icache_page(vma,pg) do { } while (0)
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/* Initialization of P3 area for copy_user_page */
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extern void p3_cache_init(void);
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#define PG_mapped PG_arch_1
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/* We provide our own get_unmapped_area to avoid cache alias issue */
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#define HAVE_ARCH_UNMAPPED_AREA
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#ifdef CONFIG_MMU
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extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
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unsigned long size, unsigned long flags);
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#else /* CONFIG_MMU */
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static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
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unsigned long size, unsigned long flags)
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{
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return 0;
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}
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#endif /* CONFIG_MMU */
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#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
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17
include/asm-sh/cpu-sh4/dma.h
一般檔案
17
include/asm-sh/cpu-sh4/dma.h
一般檔案
@@ -0,0 +1,17 @@
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#ifndef __ASM_CPU_SH4_DMA_H
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#define __ASM_CPU_SH4_DMA_H
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#define SH_DMAC_BASE 0xffa00000
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#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
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SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30})
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#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
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SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34})
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#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
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SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38})
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#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
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SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
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#define DMAOR (SH_DMAC_BASE + 0x40)
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#endif /* __ASM_CPU_SH4_DMA_H */
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22
include/asm-sh/cpu-sh4/freq.h
一般檔案
22
include/asm-sh/cpu-sh4/freq.h
一般檔案
@@ -0,0 +1,22 @@
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/*
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* include/asm-sh/cpu-sh4/freq.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_FREQ_H
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#define __ASM_CPU_SH4_FREQ_H
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#if defined(CONFIG_CPU_SUBTYPE_SH73180)
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#define FRQCR 0xa4150000
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#else
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#define FRQCR 0xffc00000
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#endif
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#define MIN_DIVISOR_NR 0
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#define MAX_DIVISOR_NR 3
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#endif /* __ASM_CPU_SH4_FREQ_H */
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@@ -0,0 +1,39 @@
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/*
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* include/asm-sh/cpu-sh4/mmu_context.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
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#define __ASM_CPU_SH4_MMU_CONTEXT_H
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#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
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#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
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#define MMU_TTB 0xFF000008 /* Translation table base register */
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#define MMU_TEA 0xFF00000C /* TLB Exception Address */
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#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
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#define MMUCR 0xFF000010 /* MMU Control Register */
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#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
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#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
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#define MMU_PAGE_ASSOC_BIT 0x80
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#define MMU_NTLB_ENTRIES 64 /* for 7750 */
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#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
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#define MMU_ITLB_DATA_ARRAY 0xF3000000
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#define MMU_UTLB_DATA_ARRAY 0xF7000000
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#define MMU_UTLB_ENTRIES 64
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#define MMU_U_ENTRY_SHIFT 8
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#define MMU_UTLB_VALID 0x100
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#define MMU_ITLB_ENTRIES 4
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#define MMU_I_ENTRY_SHIFT 8
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#define MMU_ITLB_VALID 0x100
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#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
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25
include/asm-sh/cpu-sh4/rtc.h
一般檔案
25
include/asm-sh/cpu-sh4/rtc.h
一般檔案
@@ -0,0 +1,25 @@
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#ifndef __ASM_CPU_SH4_RTC_H
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#define __ASM_CPU_SH4_RTC_H
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/* SH-4 RTC */
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#define R64CNT 0xffc80000
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#define RSECCNT 0xffc80004
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#define RMINCNT 0xffc80008
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#define RHRCNT 0xffc8000c
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#define RWKCNT 0xffc80010
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#define RDAYCNT 0xffc80014
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#define RMONCNT 0xffc80018
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#define RYRCNT 0xffc8001c /* 16bit */
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#define RSECAR 0xffc80020
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#define RMINAR 0xffc80024
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#define RHRAR 0xffc80028
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#define RWKAR 0xffc8002c
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#define RDAYAR 0xffc80030
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#define RMONAR 0xffc80034
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#define RCR1 0xffc80038
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#define RCR2 0xffc8003c
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#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
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#endif /* __ASM_CPU_SH4_RTC_H */
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@@ -0,0 +1,19 @@
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/*
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* include/asm-sh/cpu-sh4/shmparam.h
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*
|
||||
* Copyright (C) 1999 Niibe Yutaka
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
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#ifndef __ASM_CPU_SH4_SHMPARAM_H
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#define __ASM_CPU_SH4_SHMPARAM_H
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/*
|
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* SH-4 has D-cache alias issue
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*/
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#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */
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#endif /* __ASM_CPU_SH4_SHMPARAM_H */
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@@ -0,0 +1,24 @@
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#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
|
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#define __ASM_CPU_SH4_SIGCONTEXT_H
|
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|
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struct sigcontext {
|
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unsigned long oldmask;
|
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|
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/* CPU registers */
|
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unsigned long sc_regs[16];
|
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unsigned long sc_pc;
|
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unsigned long sc_pr;
|
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unsigned long sc_sr;
|
||||
unsigned long sc_gbr;
|
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unsigned long sc_mach;
|
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unsigned long sc_macl;
|
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|
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/* FPU registers */
|
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unsigned long sc_fpregs[16];
|
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unsigned long sc_xfpregs[16];
|
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unsigned int sc_fpscr;
|
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unsigned int sc_fpul;
|
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unsigned int sc_ownedfp;
|
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};
|
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|
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#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
|
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48
include/asm-sh/cpu-sh4/sq.h
一般檔案
48
include/asm-sh/cpu-sh4/sq.h
一般檔案
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* include/asm-sh/cpu-sh4/sq.h
|
||||
*
|
||||
* Copyright (C) 2001, 2002, 2003 Paul Mundt
|
||||
* Copyright (C) 2001, 2002 M. R. Brown
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH4_SQ_H
|
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#define __ASM_CPU_SH4_SQ_H
|
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|
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#include <asm/addrspace.h>
|
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|
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/*
|
||||
* Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
|
||||
* mapped to any physical address space. Since data is written (and aligned)
|
||||
* to 32-byte boundaries, we need to be sure that all allocations are aligned.
|
||||
*/
|
||||
#define SQ_SIZE 32
|
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#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
|
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#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
|
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|
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#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
|
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#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
|
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#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
|
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|
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struct sq_mapping {
|
||||
const char *name;
|
||||
|
||||
unsigned long sq_addr;
|
||||
unsigned long addr;
|
||||
unsigned int size;
|
||||
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
/* arch/sh/kernel/cpu/sh4/sq.c */
|
||||
extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name);
|
||||
extern void sq_unmap(struct sq_mapping *map);
|
||||
|
||||
extern void sq_clear(unsigned long addr, unsigned int len);
|
||||
extern void sq_flush(void *addr);
|
||||
extern void sq_flush_range(unsigned long start, unsigned int len);
|
||||
|
||||
#endif /* __ASM_CPU_SH4_SQ_H */
|
||||
|
||||
51
include/asm-sh/cpu-sh4/timer.h
一般檔案
51
include/asm-sh/cpu-sh4/timer.h
一般檔案
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* include/asm-sh/cpu-sh4/timer.h
|
||||
*
|
||||
* Copyright (C) 2004 Lineo Solutions, Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH4_TIMER_H
|
||||
#define __ASM_CPU_SH4_TIMER_H
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* TMU Common definitions for SH4 processors
|
||||
* SH7750S/SH7750R
|
||||
* SH7751/SH7751R
|
||||
* SH7760
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#define TMU_TOCR 0xffd80000 /* Byte access */
|
||||
#endif
|
||||
#define TMU_TSTR 0xffd80004 /* Byte access */
|
||||
|
||||
#define TMU0_TCOR 0xffd80008 /* Long access */
|
||||
#define TMU0_TCNT 0xffd8000c /* Long access */
|
||||
#define TMU0_TCR 0xffd80010 /* Word access */
|
||||
|
||||
#define TMU1_TCOR 0xffd80014 /* Long access */
|
||||
#define TMU1_TCNT 0xffd80018 /* Long access */
|
||||
#define TMU1_TCR 0xffd8001c /* Word access */
|
||||
|
||||
#define TMU2_TCOR 0xffd80020 /* Long access */
|
||||
#define TMU2_TCNT 0xffd80024 /* Long access */
|
||||
#define TMU2_TCR 0xffd80028 /* Word access */
|
||||
#define TMU2_TCPR 0xffd8002c /* Long access */
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#define TMU3_TCOR 0xfe100008 /* Long access */
|
||||
#define TMU3_TCNT 0xfe10000c /* Long access */
|
||||
#define TMU3_TCR 0xfe100010 /* Word access */
|
||||
|
||||
#define TMU4_TCOR 0xfe100014 /* Long access */
|
||||
#define TMU4_TCNT 0xfe100018 /* Long access */
|
||||
#define TMU4_TCR 0xfe10001c /* Word access */
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH4_TIMER_H */
|
||||
|
||||
27
include/asm-sh/cpu-sh4/ubc.h
一般檔案
27
include/asm-sh/cpu-sh4/ubc.h
一般檔案
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* include/asm-sh/cpu-sh4/ubc.h
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH4_UBC_H
|
||||
#define __ASM_CPU_SH4_UBC_H
|
||||
|
||||
#define UBC_BARA 0xff200000
|
||||
#define UBC_BAMRA 0xff200004
|
||||
#define UBC_BBRA 0xff200008
|
||||
#define UBC_BASRA 0xff000014
|
||||
#define UBC_BARB 0xff20000c
|
||||
#define UBC_BAMRB 0xff200010
|
||||
#define UBC_BBRB 0xff200014
|
||||
#define UBC_BASRB 0xff000018
|
||||
#define UBC_BDRB 0xff200018
|
||||
#define UBC_BDMRB 0xff20001c
|
||||
#define UBC_BRCR 0xff200020
|
||||
|
||||
#endif /* __ASM_CPU_SH4_UBC_H */
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* include/asm-sh/cpu-sh4/watchdog.h
|
||||
*
|
||||
* Copyright (C) 2002, 2003 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH4_WATCHDOG_H
|
||||
#define __ASM_CPU_SH4_WATCHDOG_H
|
||||
|
||||
/* Register definitions */
|
||||
#define WTCNT 0xffc00008
|
||||
#define WTCSR 0xffc0000c
|
||||
|
||||
/* Bit definitions */
|
||||
#define WTCSR_TME 0x80
|
||||
#define WTCSR_WT 0x40
|
||||
#define WTCSR_RSTS 0x20
|
||||
#define WTCSR_WOVF 0x10
|
||||
#define WTCSR_IOVF 0x08
|
||||
|
||||
#endif /* __ASM_CPU_SH4_WATCHDOG_H */
|
||||
|
||||
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