Linux-2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
commit 1da177e4c3
17291 changed files with 6718755 additions and 0 deletions

26
include/asm-sh/a.out.h Normal file
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#ifndef __ASM_SH_A_OUT_H
#define __ASM_SH_A_OUT_H
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#ifdef __KERNEL__
#define STACK_TOP TASK_SIZE
#endif
#endif /* __ASM_SH_A_OUT_H */

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include/asm-sh/adc.h Normal file
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#ifndef __ASM_ADC_H
#define __ASM_ADC_H
#ifdef __KERNEL__
/*
* Copyright (C) 2004 Andriy Skulysh
*/
#include <asm/cpu/adc.h>
int adc_single(unsigned int channel);
#endif /* __KERNEL__ */
#endif /* __ASM_ADC_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH CPUs.
*/
#ifndef __ASM_SH_ADDRSPACE_H
#define __ASM_SH_ADDRSPACE_H
#ifdef __KERNEL__
#include <asm/cpu/addrspace.h>
/* Memory segments (32bit Priviledged mode addresses) */
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
/* Returns the privileged segment base of a given address */
#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
/* Returns the physical address of a PnSEG (n=1,2) address */
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
/*
* Map an address to a certain privileged segment
*/
#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
#endif /* __KERNEL__ */
#endif /* __ASM_SH_ADDRSPACE_H */

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include/asm-sh/adx/io.h Normal file
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/*
* include/asm-sh/io_adx.h
*
* Copyright (C) 2001 A&D Co., Ltd.
*
* This file may be copied or modified under the terms of the GNU
* General Public License. See linux/COPYING for more information.
*
* IO functions for an A&D ADX Board
*/
#ifndef _ASM_SH_IO_ADX_H
#define _ASM_SH_IO_ADX_H
#include <asm/io_generic.h>
extern unsigned char adx_inb(unsigned long port);
extern unsigned short adx_inw(unsigned long port);
extern unsigned int adx_inl(unsigned long port);
extern void adx_outb(unsigned char value, unsigned long port);
extern void adx_outw(unsigned short value, unsigned long port);
extern void adx_outl(unsigned int value, unsigned long port);
extern unsigned char adx_inb_p(unsigned long port);
extern void adx_outb_p(unsigned char value, unsigned long port);
extern void adx_insb(unsigned long port, void *addr, unsigned long count);
extern void adx_insw(unsigned long port, void *addr, unsigned long count);
extern void adx_insl(unsigned long port, void *addr, unsigned long count);
extern void adx_outsb(unsigned long port, const void *addr, unsigned long count);
extern void adx_outsw(unsigned long port, const void *addr, unsigned long count);
extern void adx_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned char adx_readb(unsigned long addr);
extern unsigned short adx_readw(unsigned long addr);
extern unsigned int adx_readl(unsigned long addr);
extern void adx_writeb(unsigned char b, unsigned long addr);
extern void adx_writew(unsigned short b, unsigned long addr);
extern void adx_writel(unsigned int b, unsigned long addr);
extern void * adx_ioremap(unsigned long offset, unsigned long size);
extern void adx_iounmap(void *addr);
extern unsigned long adx_isa_port2addr(unsigned long offset);
extern void setup_adx(void);
extern void init_adx_IRQ(void);
#ifdef __WANT_IO_DEF
#define __inb adx_inb
#define __inw adx_inw
#define __inl adx_inl
#define __outb adx_outb
#define __outw adx_outw
#define __outl adx_outl
#define __inb_p adx_inb_p
#define __inw_p adx_inw
#define __inl_p adx_inl
#define __outb_p adx_outb_p
#define __outw_p adx_outw
#define __outl_p adx_outl
#define __insb adx_insb
#define __insw adx_insw
#define __insl adx_insl
#define __outsb adx_outsb
#define __outsw adx_outsw
#define __outsl adx_outsl
#define __readb adx_readb
#define __readw adx_readw
#define __readl adx_readl
#define __writeb adx_writeb
#define __writew adx_writew
#define __writel adx_writel
#define __isa_port2addr adx_isa_port2addr
#define __ioremap adx_ioremap
#define __iounmap adx_iounmap
#endif
#endif /* _ASM_SH_IO_AANDD_H */

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include/asm-sh/atomic.h Normal file
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#ifndef __ASM_SH_ATOMIC_H
#define __ASM_SH_ATOMIC_H
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
*/
typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) ((v)->counter = (i))
#include <asm/system.h>
/*
* To get proper branch prediction for the main line, we must branch
* forward to code at the end of this object's .text section, then
* branch back to restart the operation.
*/
static __inline__ void atomic_add(int i, atomic_t * v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v += i;
local_irq_restore(flags);
}
static __inline__ void atomic_sub(int i, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v -= i;
local_irq_restore(flags);
}
static __inline__ int atomic_add_return(int i, atomic_t * v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp += i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
static __inline__ int atomic_sub_return(int i, atomic_t * v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp -= i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
#define atomic_dec_return(v) atomic_sub_return(1,(v))
#define atomic_inc_return(v) atomic_add_return(1,(v))
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
#define atomic_inc(v) atomic_add(1,(v))
#define atomic_dec(v) atomic_sub(1,(v))
static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v &= ~mask;
local_irq_restore(flags);
}
static __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v |= mask;
local_irq_restore(flags);
}
/* Atomic operations are already serializing on SH */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#endif /* __ASM_SH_ATOMIC_H */

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/*
*
* Hitachi Big Sur Eval Board support
*
* Dustin McIntire (dustin@sensoria.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Derived from Hitachi SH7751 reference manual
*
*/
#ifndef _ASM_BIGSUR_H_
#define _ASM_BIGSUR_H_
#include <asm/irq.h>
#include <asm/hd64465/hd64465.h>
/* 7751 Internal IRQ's used by external CPLD controller */
#define BIGSUR_IRQ_LOW 0
#define BIGSUR_IRQ_NUM 14 /* External CPLD level 1 IRQs */
#define BIGSUR_IRQ_HIGH (BIGSUR_IRQ_LOW + BIGSUR_IRQ_NUM)
#define BIGSUR_2NDLVL_IRQ_LOW (HD64465_IRQ_BASE+HD64465_IRQ_NUM)
#define BIGSUR_2NDLVL_IRQ_NUM 32 /* Level 2 IRQs = 4 regs * 8 bits */
#define BIGSUR_2NDLVL_IRQ_HIGH (BIGSUR_2NDLVL_IRQ_LOW + \
BIGSUR_2NDLVL_IRQ_NUM)
/* PCI interrupt base number (A_INTA-A_INTD) */
#define BIGSUR_SH7751_PCI_IRQ_BASE (BIGSUR_2NDLVL_IRQ_LOW+10)
/* CPLD registers and external chip addresses */
#define BIGSUR_HD64464_ADDR 0xB2000000
#define BIGSUR_DGDR 0xB1FFFE00
#define BIGSUR_BIDR 0xB1FFFD00
#define BIGSUR_CSLR 0xB1FFFC00
#define BIGSUR_SW1R 0xB1FFFB00
#define BIGSUR_DBGR 0xB1FFFA00
#define BIGSUR_BDTR 0xB1FFF900
#define BIGSUR_BDRR 0xB1FFF800
#define BIGSUR_PPR1 0xB1FFF700
#define BIGSUR_PPR2 0xB1FFF600
#define BIGSUR_IDE2 0xB1FFF500
#define BIGSUR_IDE3 0xB1FFF400
#define BIGSUR_SPCR 0xB1FFF300
#define BIGSUR_ETHR 0xB1FE0000
#define BIGSUR_PPDR 0xB1FDFF00
#define BIGSUR_ICTL 0xB1FDFE00
#define BIGSUR_ICMD 0xB1FDFD00
#define BIGSUR_DMA0 0xB1FDFC00
#define BIGSUR_DMA1 0xB1FDFB00
#define BIGSUR_IRQ0 0xB1FDFA00
#define BIGSUR_IRQ1 0xB1FDF900
#define BIGSUR_IRQ2 0xB1FDF800
#define BIGSUR_IRQ3 0xB1FDF700
#define BIGSUR_IMR0 0xB1FDF600
#define BIGSUR_IMR1 0xB1FDF500
#define BIGSUR_IMR2 0xB1FDF400
#define BIGSUR_IMR3 0xB1FDF300
#define BIGSUR_IRLMR0 0xB1FDF200
#define BIGSUR_IRLMR1 0xB1FDF100
#define BIGSUR_V320USC_ADDR 0xB1000000
#define BIGSUR_HD64465_ADDR 0xB0000000
#define BIGSUR_INTERNAL_BASE 0xB0000000
/* SMC ethernet card parameters */
#define BIGSUR_ETHER_IOPORT 0x220
/* IDE register paramters */
#define BIGSUR_IDECMD_IOPORT 0x1f0
#define BIGSUR_IDECTL_IOPORT 0x1f8
/* LED bit position in BIGSUR_CSLR */
#define BIGSUR_LED (1<<4)
/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
#define BIGSUR_LSR0_SIZE (64*(1<<20)) //64MB
#define BIGSUR_LSR1_SIZE (64*(1<<20)) //64MB
#endif /* _ASM_BIGSUR_H_ */

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/*
* include/asm-sh/io_bigsur.h
*
* By Dustin McIntire (dustin@sensoria.com) (c)2001
* Derived from io_hd64465.h, which bore the message:
* By Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc.
* and from io_hd64461.h, which bore the message:
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for a Hitachi Big Sur Evaluation Board.
*/
#ifndef _ASM_SH_IO_BIGSUR_H
#define _ASM_SH_IO_BIGSUR_H
#include <linux/types.h>
extern unsigned long bigsur_isa_port2addr(unsigned long offset);
extern int bigsur_irq_demux(int irq);
/* Provision for generic secondary demux step -- used by PCMCIA code */
extern void bigsur_register_irq_demux(int irq,
int (*demux)(int irq, void *dev), void *dev);
extern void bigsur_unregister_irq_demux(int irq);
/* Set this variable to 1 to see port traffic */
extern int bigsur_io_debug;
/* Map a range of ports to a range of kernel virtual memory. */
extern void bigsur_port_map(u32 baseport, u32 nports, u32 addr, u8 shift);
extern void bigsur_port_unmap(u32 baseport, u32 nports);
#endif /* _ASM_SH_IO_BIGSUR_H */

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/*
* include/asm-sh/serial-bigsur.h
*
* Configuration details for Big Sur 16550 based serial ports
* i.e. HD64465, PCMCIA, etc.
*/
#ifndef _ASM_SERIAL_BIGSUR_H
#define _ASM_SERIAL_BIGSUR_H
#include <asm/hd64465.h>
#define BASE_BAUD (3379200 / 16)
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
/* XXX: This should be moved ino irq.h */
#define irq_cannonicalize(x) (x)
#endif /* _ASM_SERIAL_BIGSUR_H */

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include/asm-sh/bitops.h Normal file
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#ifndef __ASM_SH_BITOPS_H
#define __ASM_SH_BITOPS_H
#ifdef __KERNEL__
#include <asm/system.h>
/* For __swab32 */
#include <asm/byteorder.h>
static __inline__ void set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a |= mask;
local_irq_restore(flags);
}
static __inline__ void __set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a |= mask;
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
static __inline__ void clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
static __inline__ void __clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a &= ~mask;
}
static __inline__ void change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a ^= mask;
local_irq_restore(flags);
}
static __inline__ void __change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a ^= mask;
}
static __inline__ int test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
local_irq_restore(flags);
return retval;
}
static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a |= mask;
return retval;
}
static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
local_irq_restore(flags);
return retval;
}
static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a &= ~mask;
return retval;
}
static __inline__ int test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
local_irq_restore(flags);
return retval;
}
static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a ^= mask;
return retval;
}
static __inline__ int test_bit(int nr, const volatile void *addr)
{
return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
}
static __inline__ unsigned long ffz(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bt/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* __ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static __inline__ unsigned long __ffs(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bf/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* find_next_bit - find the next set bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*/
static __inline__ unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *p++;
tmp &= ~0UL << offset;
if (size < 32)
goto found_first;
if (tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = *p++) != 0)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp &= ~0UL >> (32 - size);
if (tmp == 0UL) /* Are any bits set? */
return result + size; /* Nope. */
found_middle:
return result + __ffs(tmp);
}
/**
* find_first_bit - find the first set bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first set bit, not the number of the byte
* containing a bit.
*/
#define find_first_bit(addr, size) \
find_next_bit((addr), (size), 0)
static __inline__ int find_next_zero_bit(const unsigned long *addr, int size, int offset)
{
const unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
if (~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL << size;
found_middle:
return result + ffz(tmp);
}
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
#define ffs(x) generic_ffs(x)
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
/*
* Every architecture must define this function. It's the fastest
* way of searching a 140-bit bitmap where the first 100 bits are
* unlikely to be set. It's guaranteed that at least one of the 140
* bits is cleared.
*/
static inline int sched_find_first_bit(const unsigned long *b)
{
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 32;
if (unlikely(b[2]))
return __ffs(b[2]) + 64;
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
}
#ifdef __LITTLE_ENDIAN__
#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
#define ext2_find_next_zero_bit(addr, size, offset) \
find_next_zero_bit((unsigned long *)(addr), (size), (offset))
#else
static __inline__ int ext2_set_bit(int nr, volatile void * addr)
{
int mask, retval;
unsigned long flags;
volatile unsigned char *ADDR = (unsigned char *) addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
local_irq_save(flags);
retval = (mask & *ADDR) != 0;
*ADDR |= mask;
local_irq_restore(flags);
return retval;
}
static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
unsigned long flags;
volatile unsigned char *ADDR = (unsigned char *) addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
local_irq_save(flags);
retval = (mask & *ADDR) != 0;
*ADDR &= ~mask;
local_irq_restore(flags);
return retval;
}
static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
{
int mask;
const volatile unsigned char *ADDR = (const unsigned char *) addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
return ((mask & *ADDR) != 0);
}
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if(offset) {
/* We hold the little endian value in tmp, but then the
* shift is illegal. So we could keep a big endian value
* in tmp, like this:
*
* tmp = __swab32(*(p++));
* tmp |= ~0UL >> (32-offset);
*
* but this would decrease preformance, so we change the
* shift:
*/
tmp = *(p++);
tmp |= __swab32(~0UL >> (32-offset));
if(size < 32)
goto found_first;
if(~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while(size & ~31UL) {
if(~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if(!size)
return result;
tmp = *p;
found_first:
/* tmp is little endian, so we would have to swab the shift,
* see above. But then we have to swab tmp below for ffz, so
* we might as well do this here.
*/
return result + ffz(__swab32(tmp) | (~0UL << size));
found_middle:
return result + ffz(__swab32(tmp));
}
#endif
#define ext2_set_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_set_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_clear_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_clear_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
#define minix_set_bit(nr,addr) set_bit(nr,addr)
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
/*
* fls: find last bit set.
*/
#define fls(x) generic_fls(x)
#endif /* __KERNEL__ */
#endif /* __ASM_SH_BITOPS_H */

17
include/asm-sh/bug.h Normal file
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#ifndef __ASM_SH_BUG_H
#define __ASM_SH_BUG_H
#include <linux/config.h>
/*
* Tell the user there is some problem.
*/
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
*(volatile int *)0 = 0; \
} while (0)
#define HAVE_ARCH_BUG
#include <asm-generic/bug.h>
#endif

50
include/asm-sh/bugs.h Normal file
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@@ -0,0 +1,50 @@
#ifndef __ASM_SH_BUGS_H
#define __ASM_SH_BUGS_H
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
/*
* I don't know of any Super-H bugs yet.
*/
#include <asm/processor.h>
static void __init check_bugs(void)
{
extern char *get_cpu_subtype(void);
extern unsigned long loops_per_jiffy;
char *p= &system_utsname.machine[2]; /* "sh" */
cpu_data->loops_per_jiffy = loops_per_jiffy;
switch (cpu_data->type) {
case CPU_SH7604:
*p++ = '2';
break;
case CPU_SH7705 ... CPU_SH7300:
*p++ = '3';
break;
case CPU_SH7750 ... CPU_SH4_501:
*p++ = '4';
break;
default:
*p++ = '?';
*p++ = '!';
break;
}
printk("CPU: %s\n", get_cpu_subtype());
#ifndef __LITTLE_ENDIAN__
/* 'eb' means 'Endian Big' */
*p++ = 'e';
*p++ = 'b';
#endif
*p = '\0';
}
#endif /* __ASM_SH_BUGS_H */

65
include/asm-sh/bus-sh.h Normal file
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/*
* include/asm-sh/bus-sh.h
*
* Copyright (C) 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_BUS_SH_H
#define __ASM_SH_BUS_SH_H
extern struct bus_type sh_bus_types[];
struct sh_dev {
struct device dev;
char *name;
unsigned int dev_id;
unsigned int bus_id;
struct resource res;
void *mapbase;
unsigned int irq[6];
u64 *dma_mask;
};
#define to_sh_dev(d) container_of((d), struct sh_dev, dev)
#define sh_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define sh_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, (p))
struct sh_driver {
struct device_driver drv;
unsigned int dev_id;
unsigned int bus_id;
int (*probe)(struct sh_dev *);
int (*remove)(struct sh_dev *);
int (*suspend)(struct sh_dev *, u32);
int (*resume)(struct sh_dev *);
};
#define to_sh_driver(d) container_of((d), struct sh_driver, drv)
#define sh_name(d) ((d)->dev.driver->name)
/*
* Device ID numbers for bus types
*/
enum {
SH_DEV_ID_USB_OHCI,
};
#define SH_NR_BUSES 1
#define SH_BUS_NAME_VIRT "shbus"
enum {
SH_BUS_VIRT,
};
/* arch/sh/kernel/cpu/bus.c */
extern int sh_device_register(struct sh_dev *dev);
extern void sh_device_unregister(struct sh_dev *dev);
extern int sh_driver_register(struct sh_driver *drv);
extern void sh_driver_unregister(struct sh_driver *drv);
#endif /* __ASM_SH_BUS_SH_H */

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#ifndef __ASM_SH_BYTEORDER_H
#define __ASM_SH_BYTEORDER_H
/*
* Copyright (C) 1999 Niibe Yutaka
*/
#include <asm/types.h>
#include <linux/compiler.h>
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
{
__asm__("swap.b %0, %0\n\t"
"swap.w %0, %0\n\t"
"swap.b %0, %0"
: "=r" (x)
: "0" (x));
return x;
}
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
{
__asm__("swap.b %0, %0"
: "=r" (x)
: "0" (x));
return x;
}
static inline __u64 ___arch__swab64(__u64 val)
{
union {
struct { __u32 a,b; } s;
__u64 u;
} v, w;
v.u = val;
w.s.b = ___arch__swab32(v.s.a);
w.s.a = ___arch__swab32(v.s.b);
return w.u;
}
#define __arch__swab64(x) ___arch__swab64(x)
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#ifdef __LITTLE_ENDIAN__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif /* __ASM_SH_BYTEORDER_H */

48
include/asm-sh/cache.h Normal file
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/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
*
* include/asm-sh/cache.h
*
* Copyright 1999 (C) Niibe Yutaka
* Copyright 2002, 2003 (C) Paul Mundt
*/
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#ifdef __KERNEL__
#include <asm/cpu/cache.h>
#include <asm/cpu/cacheflush.h>
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
struct cache_info {
unsigned int ways;
unsigned int sets;
unsigned int linesz;
unsigned int way_incr;
unsigned int entry_shift;
unsigned int entry_mask;
unsigned long flags;
};
/* Flush (write-back only) a region (smaller than a page) */
extern void __flush_wback_region(void *start, int size);
/* Flush (write-back & invalidate) a region (smaller than a page) */
extern void __flush_purge_region(void *start, int size);
/* Flush (invalidate only) a region (smaller than a page) */
extern void __flush_invalidate_region(void *start, int size);
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHE_H */

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#ifndef __ASM_SH_CACHEFLUSH_H
#define __ASM_SH_CACHEFLUSH_H
#ifdef __KERNEL__
#include <asm/cpu/cacheflush.h>
/* Flush (write-back only) a region (smaller than a page) */
extern void __flush_wback_region(void *start, int size);
/* Flush (write-back & invalidate) a region (smaller than a page) */
extern void __flush_purge_region(void *start, int size);
/* Flush (invalidate only) a region (smaller than a page) */
extern void __flush_invalidate_region(void *start, int size);
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
} while (0)
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHEFLUSH_H */

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/*
* include/asm-sh/io_cat68701.h
*
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
* 2001 Yutarou Ebihar (ebihara@si-linux.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an AONE Corp. CAT-68701 SH7708 Borad
*/
#ifndef _ASM_SH_IO_CAT68701_H
#define _ASM_SH_IO_CAT68701_H
extern unsigned long cat68701_isa_port2addr(unsigned long offset);
extern int cat68701_irq_demux(int irq);
extern void init_cat68701_IRQ(void);
extern void heartbeat_cat68701(void);
#endif /* _ASM_SH_IO_CAT68701_H */

216
include/asm-sh/checksum.h Normal file
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#ifndef __ASM_SH_CHECKSUM_H
#define __ASM_SH_CHECKSUM_H
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
*/
#include <linux/config.h>
#include <linux/in6.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
asmlinkage unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
/*
* the same as csum_partial, but copies from src while it
* checksums, and handles user-space pointer exceptions correctly, when needed.
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsigned char *dst,
int len, int sum, int *src_err_ptr, int *dst_err_ptr);
/*
* Note: when you get a NULL pointer exception here this means someone
* passed in an incorrect kernel address to one of these functions.
*
* If you use these functions directly please don't forget the
* verify_area().
*/
static __inline__
unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst,
int len, int sum)
{
return csum_partial_copy_generic ( src, dst, len, sum, NULL, NULL);
}
static __inline__
unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst,
int len, int sum, int *err_ptr)
{
return csum_partial_copy_generic ( src, dst, len, sum, err_ptr, NULL);
}
/*
* Fold a partial checksum
*/
static __inline__ unsigned int csum_fold(unsigned int sum)
{
unsigned int __dummy;
__asm__("swap.w %0, %1\n\t"
"extu.w %0, %0\n\t"
"extu.w %1, %1\n\t"
"add %1, %0\n\t"
"swap.w %0, %1\n\t"
"add %1, %0\n\t"
"not %0, %0\n\t"
: "=r" (sum), "=&r" (__dummy)
: "0" (sum)
: "t");
return sum;
}
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
* i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
* for linux by * Arnt Gulbrandsen.
*/
static __inline__ unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl)
{
unsigned int sum, __dummy0, __dummy1;
__asm__ __volatile__(
"mov.l @%1+, %0\n\t"
"mov.l @%1+, %3\n\t"
"add #-2, %2\n\t"
"clrt\n\t"
"1:\t"
"addc %3, %0\n\t"
"movt %4\n\t"
"mov.l @%1+, %3\n\t"
"dt %2\n\t"
"bf/s 1b\n\t"
" cmp/eq #1, %4\n\t"
"addc %3, %0\n\t"
"addc %2, %0" /* Here %2 is 0, add carry-bit */
/* Since the input registers which are loaded with iph and ihl
are modified, we must also specify them as outputs, or gcc
will assume they contain their original values. */
: "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
: "1" (iph), "2" (ihl)
: "t");
return csum_fold(sum);
}
static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
#ifdef __LITTLE_ENDIAN__
unsigned long len_proto = (ntohs(len)<<16)+proto*256;
#else
unsigned long len_proto = (proto<<16)+len;
#endif
__asm__("clrt\n\t"
"addc %0, %1\n\t"
"addc %2, %1\n\t"
"addc %3, %1\n\t"
"movt %0\n\t"
"add %1, %0"
: "=r" (sum), "=r" (len_proto)
: "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
: "t");
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static __inline__ unsigned short int csum_tcpudp_magic(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len)
{
return csum_fold (csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
struct in6_addr *daddr,
__u32 len,
unsigned short proto,
unsigned int sum)
{
unsigned int __dummy;
__asm__("clrt\n\t"
"mov.l @(0,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(4,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(8,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(12,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(0,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(4,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(8,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(12,%3), %1\n\t"
"addc %1, %0\n\t"
"addc %4, %0\n\t"
"addc %5, %0\n\t"
"movt %1\n\t"
"add %1, %0\n"
: "=r" (sum), "=&r" (__dummy)
: "r" (saddr), "r" (daddr),
"r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
: "t");
return csum_fold(sum);
}
/*
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
static __inline__ unsigned int csum_and_copy_to_user (const unsigned char *src,
unsigned char __user *dst,
int len, int sum,
int *err_ptr)
{
if (access_ok(VERIFY_WRITE, dst, len))
return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr);
if (len)
*err_ptr = -EFAULT;
return -1; /* invalid checksum */
}
#endif /* __ASM_SH_CHECKSUM_H */

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@@ -0,0 +1,16 @@
/*
* Definitions for the address spaces of the SH-2 CPUs.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_ADDRSPACE_H
#define __ASM_CPU_SH2_ADDRSPACE_H
/* Should fill here */
#endif /* __ASM_CPU_SH2_ADDRSPACE_H */

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@@ -0,0 +1,31 @@
/*
* include/asm-sh/cpu-sh2/cache.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHE_H
#define __ASM_CPU_SH2_CACHE_H
#define L1_CACHE_SHIFT 4
#define CCR 0xfffffe92 /* Address of Cache Control Register */
#define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */
#define CCR_CACHE_OD 0x04 /* Data Replacement disable */
#define CCR_CACHE_TW 0x08 /* Two-way mode */
#define CCR_CACHE_CP 0x10 /* Cache purge */
#define CACHE_OC_ADDRESS_ARRAY 0x60000000
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CP
#define CCR_CACHE_ORA CCR_CACHE_TW
#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
#endif /* __ASM_CPU_SH2_CACHE_H */

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@@ -0,0 +1,42 @@
/*
* include/asm-sh/cpu-sh2/cacheflush.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
#define __ASM_CPU_SH2_CACHEFLUSH_H
/*
* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
*
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_range(start, end) flushes(invalidates) a range for icache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* Caches are indexed (effectively) by physical address on SH-2, so
* we don't need them.
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define p3_cache_init() do { } while (0)
#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */

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@@ -0,0 +1,23 @@
/*
* Definitions for the SH-2 DMAC.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_DMA_H
#define __ASM_CPU_SH2_DMA_H
#define SH_MAX_DMA_CHANNELS 2
#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
#define DMAOR 0xffffffb0
#endif /* __ASM_CPU_SH2_DMA_H */

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@@ -0,0 +1,16 @@
/*
* include/asm-sh/cpu-sh2/shmparam.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_SHMPARAM_H
#define __ASM_CPU_SH2_SHMPARAM_H
#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
#endif /* __ASM_CPU_SH2_SHMPARAM_H */

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@@ -0,0 +1,17 @@
#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
#define __ASM_CPU_SH2_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
};
#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */

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@@ -0,0 +1,32 @@
/*
* include/asm-sh/cpu-sh2/ubc.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_UBC_H
#define __ASM_CPU_SH2_UBC_H
#define UBC_BARA 0xffffff40
#define UBC_BAMRA 0xffffff44
#define UBC_BBRA 0xffffff48
#define UBC_BARB 0xffffff60
#define UBC_BAMRB 0xffffff64
#define UBC_BBRB 0xffffff68
#define UBC_BDRB 0xffffff70
#define UBC_BDMRB 0xffffff74
#define UBC_BRCR 0xffffff78
/*
* We don't have any ASID changes to make in the UBC on the SH-2.
*
* Make these purposely invalid to track misuse.
*/
#define UBC_BASRA 0x00000000
#define UBC_BASRB 0x00000000
#endif /* __ASM_CPU_SH2_UBC_H */

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/*
* include/asm-sh/cpu-sh2/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_WATCHDOG_H
#define __ASM_CPU_SH2_WATCHDOG_H
/*
* More SH-2 brilliance .. its not good enough that we can't read
* and write the same sizes to WTCNT, now we have to read and write
* with different sizes at different addresses for WTCNT _and_ RSTCSR.
*
* At least on the bright side no one has managed to screw over WTCSR
* in this fashion .. yet.
*/
/* Register definitions */
#define WTCNT 0xfffffe80
#define WTCSR 0xfffffe80
#define RSTCSR 0xfffffe82
#define WTCNT_R (WTCNT + 1)
#define RSTCSR_R (RSTCSR + 1)
/* Bit definitions */
#define WTCSR_IOVF 0x80
#define WTCSR_WT 0x40
#define WTCSR_TME 0x20
#define WTCSR_RSTS 0x00
#define RSTCSR_RSTS 0x20
/**
* sh_wdt_read_rstcsr - Read from Reset Control/Status Register
*
* Reads back the RSTCSR value.
*/
static inline __u8 sh_wdt_read_rstcsr(void)
{
/*
* Same read/write brain-damage as for WTCNT here..
*/
return ctrl_inb(RSTCSR_R);
}
/**
* sh_wdt_write_csr - Write to Reset Control/Status Register
*
* @val: Value to write
*
* Writes the given value @val to the lower byte of the control/status
* register. The upper byte is set manually on each write.
*/
static inline void sh_wdt_write_rstcsr(__u8 val)
{
/*
* Note: Due to the brain-damaged nature of this register,
* we can't presently touch the WOVF bit, since the upper byte
* has to be swapped for this. So just leave it alone..
*/
ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
}
#endif /* __ASM_CPU_SH2_WATCHDOG_H */

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#ifndef __ASM_CPU_SH3_ADC_H
#define __ASM_CPU_SH3_ADC_H
/*
* Copyright (C) 2004 Andriy Skulysh
*/
#define ADDRAH 0xa4000080
#define ADDRAL 0xa4000082
#define ADDRBH 0xa4000084
#define ADDRBL 0xa4000086
#define ADDRCH 0xa4000088
#define ADDRCL 0xa400008a
#define ADDRDH 0xa400008c
#define ADDRDL 0xa400008e
#define ADCSR 0xa4000090
#define ADCSR_ADF 0x80
#define ADCSR_ADIE 0x40
#define ADCSR_ADST 0x20
#define ADCSR_MULTI 0x10
#define ADCSR_CKS 0x08
#define ADCSR_CH_MASK 0x07
#define ADCR 0xa4000092
#endif /* __ASM_CPU_SH3_ADC_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH-3 CPUs.
*/
#ifndef __ASM_CPU_SH3_ADDRSPACE_H
#define __ASM_CPU_SH3_ADDRSPACE_H
/* Should fill here */
#endif /* __ASM_CPU_SH3_ADDRSPACE_H */

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/*
* include/asm-sh/cpu-sh3/cache.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_CACHE_H
#define __ASM_CPU_SH3_CACHE_H
#define L1_CACHE_SHIFT 4
#define CCR 0xffffffec /* Address of Cache Control Register */
#define CCR_CACHE_CE 0x01 /* Cache Enable */
#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
#define CCR_CACHE_CF 0x08 /* Cache Flush */
#define CCR_CACHE_ORA 0x20 /* RAM mode */
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_PHYSADDR_MASK 0x1ffffc00
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
#define CCR3 0xa40000b4
#define CCR_CACHE_16KB 0x00010000
#define CCR_CACHE_32KB 0x00020000
#endif
#endif /* __ASM_CPU_SH3_CACHE_H */

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/*
* include/asm-sh/cpu-sh3/cacheflush.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
#define __ASM_CPU_SH3_CACHEFLUSH_H
/*
* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
*
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_range(start, end) flushes(invalidates) a range for icache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* Caches are indexed (effectively) by physical address on SH-3, so
* we don't need them.
*/
#if defined(CONFIG_SH7705_CACHE_32KB)
/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
* SH4. Unlike the SH4 this is a unified cache so we need to do some work
* in mmap when 'exec'ing a new binary
*/
/* 32KB cache, 4kb PAGE sizes need to check bit 12 */
#define CACHE_ALIAS 0x00001000
struct page;
struct mm_struct;
struct vm_area_struct;
extern void flush_cache_all(void);
extern void flush_cache_mm(struct mm_struct *mm);
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
extern void flush_dcache_page(struct page *pg);
extern void flush_icache_range(unsigned long start, unsigned long end);
extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
/* SH3 has unified cache so no special action needed here */
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define flush_page_to_ram(page) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define p3_cache_init() do { } while (0)
#define PG_mapped PG_arch_1
/* We provide our own get_unmapped_area to avoid cache alias issue */
#define HAVE_ARCH_UNMAPPED_AREA
#else
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define p3_cache_init() do { } while (0)
#define HAVE_ARCH_UNMAPPED_AREA
#endif
#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */

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#ifndef __ASM_CPU_SH3_DAC_H
#define __ASM_CPU_SH3_DAC_H
/*
* Copyright (C) 2003 Andriy Skulysh
*/
#define DADR0 0xa40000a0
#define DADR1 0xa40000a2
#define DACR 0xa40000a4
#define DACR_DAOE1 0x80
#define DACR_DAOE0 0x40
#define DACR_DAE 0x20
static __inline__ void sh_dac_enable(int channel)
{
unsigned char v;
v = ctrl_inb(DACR);
if(channel) v |= DACR_DAOE1;
else v |= DACR_DAOE0;
ctrl_outb(v,DACR);
}
static __inline__ void sh_dac_disable(int channel)
{
unsigned char v;
v = ctrl_inb(DACR);
if(channel) v &= ~DACR_DAOE1;
else v &= ~DACR_DAOE0;
ctrl_outb(v,DACR);
}
static __inline__ void sh_dac_output(u8 value, int channel)
{
if(channel) ctrl_outb(value,DADR1);
else ctrl_outb(value,DADR0);
}
#endif /* __ASM_CPU_SH3_DAC_H */

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#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
#define SH_DMAC_BASE 0xa4000020
#endif /* __ASM_CPU_SH3_DMA_H */

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/*
* include/asm-sh/cpu-sh3/freq.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_FREQ_H
#define __ASM_CPU_SH3_FREQ_H
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#define FRQCR 0xa415ff80
#else
#define FRQCR 0xffffff80
#endif
#define MIN_DIVISOR_NR 0
#define MAX_DIVISOR_NR 4
#endif /* __ASM_CPU_SH3_FREQ_H */

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/*
* include/asm-sh/cpu-sh3/mmu_context.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
#define __ASM_CPU_SH3_MMU_CONTEXT_H
#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
#define MMU_PAGE_ASSOC_BIT 0x80
#define MMU_NTLB_ENTRIES 128 /* for 7708 */
#define MMU_NTLB_WAYS 4
#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */

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#ifndef __ASM_CPU_SH3_RTC_H
#define __ASM_CPU_SH3_RTC_H
/* SH-3 RTC */
#define R64CNT 0xfffffec0
#define RSECCNT 0xfffffec2
#define RMINCNT 0xfffffec4
#define RHRCNT 0xfffffec6
#define RWKCNT 0xfffffec8
#define RDAYCNT 0xfffffeca
#define RMONCNT 0xfffffecc
#define RYRCNT 0xfffffece
#define RSECAR 0xfffffed0
#define RMINAR 0xfffffed2
#define RHRAR 0xfffffed4
#define RWKAR 0xfffffed6
#define RDAYAR 0xfffffed8
#define RMONAR 0xfffffeda
#define RCR1 0xfffffedc
#define RCR2 0xfffffede
#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
#endif /* __ASM_CPU_SH3_RTC_H */

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/*
* include/asm-sh/cpu-sh3/shmparam.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_SHMPARAM_H
#define __ASM_CPU_SH3_SHMPARAM_H
#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
#endif /* __ASM_CPU_SH3_SHMPARAM_H */

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#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
#define __ASM_CPU_SH3_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
};
#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */

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/*
* include/asm-sh/cpu-sh3/timer.h
*
* Copyright (C) 2004 Lineo Solutions, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_TIMER_H
#define __ASM_CPU_SH3_TIMER_H
/*
* ---------------------------------------------------------------------------
* TMU Common definitions for SH3 processors
* SH7706
* SH7709S
* SH7727
* SH7729R
* SH7710
* SH7720
* SH7300
* ---------------------------------------------------------------------------
*/
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
#define TMU_TSTR 0xa412fe92 /* Byte access */
#define TMU0_TCOR 0xa412fe94 /* Long access */
#define TMU0_TCNT 0xa412fe98 /* Long access */
#define TMU0_TCR 0xa412fe9c /* Word access */
#define TMU1_TCOR 0xa412fea0 /* Long access */
#define TMU1_TCNT 0xa412fea4 /* Long access */
#define TMU1_TCR 0xa412fea8 /* Word access */
#define TMU2_TCOR 0xa412feac /* Long access */
#define TMU2_TCNT 0xa412feb0 /* Long access */
#define TMU2_TCR 0xa412feb4 /* Word access */
#else
#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU_TOCR 0xfffffe90 /* Byte access */
#endif
#define TMU_TSTR 0xfffffe92 /* Byte access */
#define TMU0_TCOR 0xfffffe94 /* Long access */
#define TMU0_TCNT 0xfffffe98 /* Long access */
#define TMU0_TCR 0xfffffe9c /* Word access */
#define TMU1_TCOR 0xfffffea0 /* Long access */
#define TMU1_TCNT 0xfffffea4 /* Long access */
#define TMU1_TCR 0xfffffea8 /* Word access */
#define TMU2_TCOR 0xfffffeac /* Long access */
#define TMU2_TCNT 0xfffffeb0 /* Long access */
#define TMU2_TCR 0xfffffeb4 /* Word access */
#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
#endif
#endif
#endif /* __ASM_CPU_SH3_TIMER_H */

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/*
* include/asm-sh/cpu-sh3/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_UBC_H
#define __ASM_CPU_SH3_UBC_H
#define UBC_BARA 0xffffffb0
#define UBC_BAMRA 0xffffffb4
#define UBC_BBRA 0xffffffb8
#define UBC_BASRA 0xffffffe4
#define UBC_BARB 0xffffffa0
#define UBC_BAMRB 0xffffffa4
#define UBC_BBRB 0xffffffa8
#define UBC_BASRB 0xffffffe8
#define UBC_BDRB 0xffffff90
#define UBC_BDMRB 0xffffff94
#define UBC_BRCR 0xffffff98
#endif /* __ASM_CPU_SH3_UBC_H */

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/*
* include/asm-sh/cpu-sh3/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_WATCHDOG_H
#define __ASM_CPU_SH3_WATCHDOG_H
/* Register definitions */
#define WTCNT 0xffffff84
#define WTCSR 0xffffff86
/* Bit definitions */
#define WTCSR_TME 0x80
#define WTCSR_WT 0x40
#define WTCSR_RSTS 0x20
#define WTCSR_WOVF 0x10
#define WTCSR_IOVF 0x08
#endif /* __ASM_CPU_SH3_WATCHDOG_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH-4 CPUs.
*/
#ifndef __ASM_CPU_SH4_ADDRSPACE_H
#define __ASM_CPU_SH4_ADDRSPACE_H
/* Detailed P4SEG */
#define P4SEG_STORE_QUE (P4SEG)
#define P4SEG_IC_ADDR 0xf0000000
#define P4SEG_IC_DATA 0xf1000000
#define P4SEG_ITLB_ADDR 0xf2000000
#define P4SEG_ITLB_DATA 0xf3000000
#define P4SEG_OC_ADDR 0xf4000000
#define P4SEG_OC_DATA 0xf5000000
#define P4SEG_TLB_ADDR 0xf6000000
#define P4SEG_TLB_DATA 0xf7000000
#define P4SEG_REG_BASE 0xff000000
#endif /* __ASM_CPU_SH4_ADDRSPACE_H */

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/*
* include/asm-sh/cpu-sh4/cache.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_CACHE_H
#define __ASM_CPU_SH4_CACHE_H
#define L1_CACHE_SHIFT 5
#define CCR 0xff00001c /* Address of Cache Control Register */
#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
#endif /* __ASM_CPU_SH4_CACHE_H */

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/*
* include/asm-sh/cpu-sh4/cacheflush.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
#define __ASM_CPU_SH4_CACHEFLUSH_H
/*
* Caches are broken on SH-4 (unless we use write-through
* caching; in which case they're only semi-broken),
* so we need them.
*/
/* Page is 4K, OC size is 16K, there are four lines. */
#define CACHE_ALIAS 0x00003000
struct page;
struct mm_struct;
struct vm_area_struct;
extern void flush_cache_all(void);
extern void flush_cache_mm(struct mm_struct *mm);
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
extern void flush_dcache_page(struct page *pg);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void flush_icache_range(unsigned long start, unsigned long end);
extern void flush_cache_sigtramp(unsigned long addr);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
#define flush_icache_page(vma,pg) do { } while (0)
/* Initialization of P3 area for copy_user_page */
extern void p3_cache_init(void);
#define PG_mapped PG_arch_1
/* We provide our own get_unmapped_area to avoid cache alias issue */
#define HAVE_ARCH_UNMAPPED_AREA
#ifdef CONFIG_MMU
extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
unsigned long size, unsigned long flags);
#else /* CONFIG_MMU */
static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
unsigned long size, unsigned long flags)
{
return 0;
}
#endif /* CONFIG_MMU */
#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */

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#ifndef __ASM_CPU_SH4_DMA_H
#define __ASM_CPU_SH4_DMA_H
#define SH_DMAC_BASE 0xffa00000
#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30})
#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34})
#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38})
#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
#define DMAOR (SH_DMAC_BASE + 0x40)
#endif /* __ASM_CPU_SH4_DMA_H */

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/*
* include/asm-sh/cpu-sh4/freq.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_FREQ_H
#define __ASM_CPU_SH4_FREQ_H
#if defined(CONFIG_CPU_SUBTYPE_SH73180)
#define FRQCR 0xa4150000
#else
#define FRQCR 0xffc00000
#endif
#define MIN_DIVISOR_NR 0
#define MAX_DIVISOR_NR 3
#endif /* __ASM_CPU_SH4_FREQ_H */

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/*
* include/asm-sh/cpu-sh4/mmu_context.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
#define __ASM_CPU_SH4_MMU_CONTEXT_H
#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
#define MMU_TTB 0xFF000008 /* Translation table base register */
#define MMU_TEA 0xFF00000C /* TLB Exception Address */
#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
#define MMUCR 0xFF000010 /* MMU Control Register */
#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
#define MMU_PAGE_ASSOC_BIT 0x80
#define MMU_NTLB_ENTRIES 64 /* for 7750 */
#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
#define MMU_ITLB_DATA_ARRAY 0xF3000000
#define MMU_UTLB_DATA_ARRAY 0xF7000000
#define MMU_UTLB_ENTRIES 64
#define MMU_U_ENTRY_SHIFT 8
#define MMU_UTLB_VALID 0x100
#define MMU_ITLB_ENTRIES 4
#define MMU_I_ENTRY_SHIFT 8
#define MMU_ITLB_VALID 0x100
#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */

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#ifndef __ASM_CPU_SH4_RTC_H
#define __ASM_CPU_SH4_RTC_H
/* SH-4 RTC */
#define R64CNT 0xffc80000
#define RSECCNT 0xffc80004
#define RMINCNT 0xffc80008
#define RHRCNT 0xffc8000c
#define RWKCNT 0xffc80010
#define RDAYCNT 0xffc80014
#define RMONCNT 0xffc80018
#define RYRCNT 0xffc8001c /* 16bit */
#define RSECAR 0xffc80020
#define RMINAR 0xffc80024
#define RHRAR 0xffc80028
#define RWKAR 0xffc8002c
#define RDAYAR 0xffc80030
#define RMONAR 0xffc80034
#define RCR1 0xffc80038
#define RCR2 0xffc8003c
#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
#endif /* __ASM_CPU_SH4_RTC_H */

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/*
* include/asm-sh/cpu-sh4/shmparam.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_SHMPARAM_H
#define __ASM_CPU_SH4_SHMPARAM_H
/*
* SH-4 has D-cache alias issue
*/
#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */
#endif /* __ASM_CPU_SH4_SHMPARAM_H */

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#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
#define __ASM_CPU_SH4_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
/* FPU registers */
unsigned long sc_fpregs[16];
unsigned long sc_xfpregs[16];
unsigned int sc_fpscr;
unsigned int sc_fpul;
unsigned int sc_ownedfp;
};
#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */

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/*
* include/asm-sh/cpu-sh4/sq.h
*
* Copyright (C) 2001, 2002, 2003 Paul Mundt
* Copyright (C) 2001, 2002 M. R. Brown
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_SQ_H
#define __ASM_CPU_SH4_SQ_H
#include <asm/addrspace.h>
/*
* Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
* mapped to any physical address space. Since data is written (and aligned)
* to 32-byte boundaries, we need to be sure that all allocations are aligned.
*/
#define SQ_SIZE 32
#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
struct sq_mapping {
const char *name;
unsigned long sq_addr;
unsigned long addr;
unsigned int size;
struct list_head list;
};
/* arch/sh/kernel/cpu/sh4/sq.c */
extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name);
extern void sq_unmap(struct sq_mapping *map);
extern void sq_clear(unsigned long addr, unsigned int len);
extern void sq_flush(void *addr);
extern void sq_flush_range(unsigned long start, unsigned int len);
#endif /* __ASM_CPU_SH4_SQ_H */

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/*
* include/asm-sh/cpu-sh4/timer.h
*
* Copyright (C) 2004 Lineo Solutions, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_TIMER_H
#define __ASM_CPU_SH4_TIMER_H
/*
* ---------------------------------------------------------------------------
* TMU Common definitions for SH4 processors
* SH7750S/SH7750R
* SH7751/SH7751R
* SH7760
* ---------------------------------------------------------------------------
*/
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
#define TMU_TOCR 0xffd80000 /* Byte access */
#endif
#define TMU_TSTR 0xffd80004 /* Byte access */
#define TMU0_TCOR 0xffd80008 /* Long access */
#define TMU0_TCNT 0xffd8000c /* Long access */
#define TMU0_TCR 0xffd80010 /* Word access */
#define TMU1_TCOR 0xffd80014 /* Long access */
#define TMU1_TCNT 0xffd80018 /* Long access */
#define TMU1_TCR 0xffd8001c /* Word access */
#define TMU2_TCOR 0xffd80020 /* Long access */
#define TMU2_TCNT 0xffd80024 /* Long access */
#define TMU2_TCR 0xffd80028 /* Word access */
#define TMU2_TCPR 0xffd8002c /* Long access */
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
#define TMU3_TCOR 0xfe100008 /* Long access */
#define TMU3_TCNT 0xfe10000c /* Long access */
#define TMU3_TCR 0xfe100010 /* Word access */
#define TMU4_TCOR 0xfe100014 /* Long access */
#define TMU4_TCNT 0xfe100018 /* Long access */
#define TMU4_TCR 0xfe10001c /* Word access */
#endif
#endif /* __ASM_CPU_SH4_TIMER_H */

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/*
* include/asm-sh/cpu-sh4/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_UBC_H
#define __ASM_CPU_SH4_UBC_H
#define UBC_BARA 0xff200000
#define UBC_BAMRA 0xff200004
#define UBC_BBRA 0xff200008
#define UBC_BASRA 0xff000014
#define UBC_BARB 0xff20000c
#define UBC_BAMRB 0xff200010
#define UBC_BBRB 0xff200014
#define UBC_BASRB 0xff000018
#define UBC_BDRB 0xff200018
#define UBC_BDMRB 0xff20001c
#define UBC_BRCR 0xff200020
#endif /* __ASM_CPU_SH4_UBC_H */

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/*
* include/asm-sh/cpu-sh4/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_WATCHDOG_H
#define __ASM_CPU_SH4_WATCHDOG_H
/* Register definitions */
#define WTCNT 0xffc00008
#define WTCSR 0xffc0000c
/* Bit definitions */
#define WTCSR_TME 0x80
#define WTCSR_WT 0x40
#define WTCSR_RSTS 0x20
#define WTCSR_WOVF 0x10
#define WTCSR_IOVF 0x08
#endif /* __ASM_CPU_SH4_WATCHDOG_H */

6
include/asm-sh/cputime.h Normal file
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#ifndef __SH_CPUTIME_H
#define __SH_CPUTIME_H
#include <asm-generic/cputime.h>
#endif /* __SH_CPUTIME_H */

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#ifndef __ASM_SH_CQREEK_CQREEK_H
#define __ASM_SH_CQREEK_CQREEK_H
#define BRIDGE_FEATURE 0x0002
#define BRIDGE_IDE_CTRL 0x0018
#define BRIDGE_IDE_INTR_LVL 0x001A
#define BRIDGE_IDE_INTR_MASK 0x001C
#define BRIDGE_IDE_INTR_STAT 0x001E
#define BRIDGE_ISA_CTRL 0x0028
#define BRIDGE_ISA_INTR_LVL 0x002A
#define BRIDGE_ISA_INTR_MASK 0x002C
#define BRIDGE_ISA_INTR_STAT 0x002E
/* arch/sh/boards/cqreek/setup.c */
extern void setup_cqreek(void);
/* arch/sh/boards/cqreek/irq.c */
extern int cqreek_has_ide, cqreek_has_isa;
extern void init_cqreek_IRQ(void);
/* arch/sh/boards/cqreek/io.c */
extern unsigned long cqreek_port2addr(unsigned long port);
#endif /* __ASM_SH_CQREEK_CQREEK_H */

20
include/asm-sh/current.h Normal file
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#ifndef __ASM_SH_CURRENT_H
#define __ASM_SH_CURRENT_H
/*
* Copyright (C) 1999 Niibe Yutaka
*
*/
#include <linux/thread_info.h>
struct task_struct;
static __inline__ struct task_struct * get_current(void)
{
return current_thread_info()->task;
}
#define current get_current()
#endif /* __ASM_SH_CURRENT_H */

27
include/asm-sh/delay.h Normal file
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#ifndef __ASM_SH_DELAY_H
#define __ASM_SH_DELAY_H
/*
* Copyright (C) 1993 Linus Torvalds
*
* Delay routines calling functions in arch/sh/lib/delay.c
*/
extern void __bad_udelay(void);
extern void __bad_ndelay(void);
extern void __udelay(unsigned long usecs);
extern void __ndelay(unsigned long nsecs);
extern void __const_udelay(unsigned long usecs);
extern void __delay(unsigned long loops);
#define udelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
__udelay(n))
#define ndelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
__ndelay(n))
#endif /* __ASM_SH_DELAY_H */

1
include/asm-sh/div64.h Normal file
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#include <asm-generic/div64.h>

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@@ -0,0 +1,179 @@
#ifndef __ASM_SH_DMA_MAPPING_H
#define __ASM_SH_DMA_MAPPING_H
#include <linux/config.h>
#include <linux/mm.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
extern struct bus_type pci_bus_type;
/* arch/sh/mm/consistent.c */
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size);
extern void consistent_sync(void *vaddr, size_t size, int direction);
#define dma_supported(dev, mask) (1)
static inline int dma_set_mask(struct device *dev, u64 mask)
{
if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = mask;
return 0;
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
{
if (sh_mv.mv_consistent_alloc) {
void *ret;
ret = sh_mv.mv_consistent_alloc(dev, size, dma_handle, flag);
if (ret != NULL)
return ret;
}
return consistent_alloc(flag, size, dma_handle);
}
static inline void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
if (sh_mv.mv_consistent_free) {
int ret;
ret = sh_mv.mv_consistent_free(dev, size, vaddr, dma_handle);
if (ret == 0)
return;
}
consistent_free(vaddr, size);
}
static inline void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction dir)
{
consistent_sync(vaddr, size, (int)dir);
}
static inline dma_addr_t dma_map_single(struct device *dev,
void *ptr, size_t size,
enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return virt_to_bus(ptr);
#endif
dma_cache_sync(ptr, size, dir);
return virt_to_bus(ptr);
}
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
int i;
for (i = 0; i < nents; i++) {
#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
sg[i].length, dir);
#endif
sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
}
return nents;
}
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction dir)
{
return dma_map_single(dev, page_address(page) + offset, size, dir);
}
static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
size_t size, enum dma_data_direction dir)
{
dma_unmap_single(dev, dma_address, size, dir);
}
static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
size_t size, enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return;
#endif
dma_cache_sync(bus_to_virt(dma_handle), size, dir);
}
static inline void dma_sync_single_range(struct device *dev,
dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return;
#endif
dma_cache_sync(bus_to_virt(dma_handle) + offset, size, dir);
}
static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction dir)
{
int i;
for (i = 0; i < nelems; i++) {
#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
sg[i].length, dir);
#endif
sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
}
}
static inline void dma_sync_single_for_cpu(struct device *dev,
dma_addr_t dma_handle, size_t size,
enum dma_data_direction dir)
__attribute__ ((alias("dma_sync_single")));
static inline void dma_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle, size_t size,
enum dma_data_direction dir)
__attribute__ ((alias("dma_sync_single")));
static inline void dma_sync_sg_for_cpu(struct device *dev,
struct scatterlist *sg, int nelems,
enum dma_data_direction dir)
__attribute__ ((alias("dma_sync_sg")));
static inline void dma_sync_sg_for_device(struct device *dev,
struct scatterlist *sg, int nelems,
enum dma_data_direction dir)
__attribute__ ((alias("dma_sync_sg")));
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline int dma_mapping_error(dma_addr_t dma_addr)
{
return dma_addr == 0;
}
#endif /* __ASM_SH_DMA_MAPPING_H */

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include/asm-sh/dma.h Normal file
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/*
* include/asm-sh/dma.h
*
* Copyright (C) 2003, 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DMA_H
#define __ASM_SH_DMA_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sysdev.h>
#include <asm/cpu/dma.h>
#include <asm/semaphore.h>
/* The maximum address that we can perform a DMA transfer to on this platform */
/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
occurrence should be flagged as an error. */
/* But... */
/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
#ifdef CONFIG_NR_DMA_CHANNELS
# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
#else
# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
#endif
/*
* Read and write modes can mean drastically different things depending on the
* channel configuration. Consult your DMAC documentation and module
* implementation for further clues.
*/
#define DMA_MODE_READ 0x00
#define DMA_MODE_WRITE 0x01
#define DMA_MODE_MASK 0x01
#define DMA_AUTOINIT 0x10
/*
* DMAC (dma_info) flags
*/
enum {
DMAC_CHANNELS_CONFIGURED = 0x00,
DMAC_CHANNELS_TEI_CAPABLE = 0x01,
};
/*
* DMA channel capabilities / flags
*/
enum {
DMA_CONFIGURED = 0x00,
DMA_TEI_CAPABLE = 0x01,
};
extern spinlock_t dma_spin_lock;
struct dma_channel;
struct dma_ops {
int (*request)(struct dma_channel *chan);
void (*free)(struct dma_channel *chan);
int (*get_residue)(struct dma_channel *chan);
int (*xfer)(struct dma_channel *chan);
void (*configure)(struct dma_channel *chan, unsigned long flags);
};
struct dma_channel {
char dev_id[16];
unsigned int chan;
unsigned int mode;
unsigned int count;
unsigned long sar;
unsigned long dar;
unsigned long flags;
atomic_t busy;
struct semaphore sem;
wait_queue_head_t wait_queue;
struct sys_device dev;
};
struct dma_info {
const char *name;
unsigned int nr_channels;
unsigned long flags;
struct dma_ops *ops;
struct dma_channel *channels;
struct list_head list;
};
#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
/* arch/sh/drivers/dma/dma-api.c */
extern int dma_xfer(unsigned int chan, unsigned long from,
unsigned long to, size_t size, unsigned int mode);
#define dma_write(chan, from, to, size) \
dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
#define dma_write_page(chan, from, to) \
dma_write(chan, from, to, PAGE_SIZE)
#define dma_read(chan, from, to, size) \
dma_xfer(chan, from, to, size, DMA_MODE_READ)
#define dma_read_page(chan, from, to) \
dma_read(chan, from, to, PAGE_SIZE)
extern int request_dma(unsigned int chan, const char *dev_id);
extern void free_dma(unsigned int chan);
extern int get_dma_residue(unsigned int chan);
extern struct dma_info *get_dma_info(unsigned int chan);
extern struct dma_channel *get_dma_channel(unsigned int chan);
extern void dma_wait_for_completion(unsigned int chan);
extern void dma_configure_channel(unsigned int chan, unsigned long flags);
extern int register_dmac(struct dma_info *info);
extern void unregister_dmac(struct dma_info *info);
#ifdef CONFIG_SYSFS
/* arch/sh/drivers/dma/dma-sysfs.c */
extern int dma_create_sysfs_files(struct dma_channel *);
#endif
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* __KERNEL__ */
#endif /* __ASM_SH_DMA_H */

10
include/asm-sh/dmida/io.h Normal file
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#ifndef __ASM_SH_DMIDA_IO_H
#define __ASM_SH_DMIDA_IO_H
/*
* Nothing special here.. just use the generic cchip io routines.
*/
#include <asm/hd64465/io.h>
#endif /* __ASM_SH_DMIDA_IO_H */

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@@ -0,0 +1,34 @@
/*
* include/asm-sh/dreamcast/dma.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DREAMCAST_DMA_H
#define __ASM_SH_DREAMCAST_DMA_H
/* Number of DMA channels */
#define ONCHIP_NR_DMA_CHANNELS 4
#define G2_NR_DMA_CHANNELS 4
#define PVR2_NR_DMA_CHANNELS 1
/* Channels for cascading */
#define PVR2_CASCADE_CHAN 2
#define G2_CASCADE_CHAN 3
/* PVR2 DMA Registers */
#define PVR2_DMA_BASE 0xa05f6800
#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
/* G2 DMA Register */
#define G2_DMA_BASE 0xa05f7800
#endif /* __ASM_SH_DREAMCAST_DMA_H */

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/*
* include/asm-sh/dreamcast/pci.h
*
* Copyright (C) 2001, 2002 M. R. Brown
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DREAMCAST_PCI_H
#define __ASM_SH_DREAMCAST_PCI_H
#include <asm/mach/sysasic.h>
#define GAPSPCI_REGS 0x01001400
#define GAPSPCI_DMA_BASE 0x01840000
#define GAPSPCI_DMA_SIZE 32768
#define GAPSPCI_BBA_CONFIG 0x01001600
#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
#endif /* __ASM_SH_DREAMCAST_PCI_H */

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/* include/asm-sh/dc_sysasic.h
*
* Definitions for the Dreamcast System ASIC and related peripherals.
*
* Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
* Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
*
* This file is part of the LinuxDC project (www.linuxdc.org)
*
* Released under the terms of the GNU GPL v2.0.
*
*/
#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
#define __ASM_SH_DREAMCAST_SYSASIC_H
#include <asm/irq.h>
/* Hardware events -
Each of these events correspond to a bit within the Event Mask Registers/
Event Status Registers. Because of the virtual IRQ numbering scheme, a
base offset must be used when calculating the virtual IRQ that each event
takes.
*/
#define HW_EVENT_IRQ_BASE OFFCHIP_IRQ_BASE /* 48 */
/* IRQ 13 */
#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
/* IRQ 11 */
#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */

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#ifndef __ASM_EC3104_H
#define __ASM_EC3104_H
/*
* Most of the register set is at 0xb0ec0000 - 0xb0ecffff.
*
* as far as I've figured it out the register map is:
* 0xb0ec0000 - id string
* 0xb0ec0XXX - power management
* 0xb0ec1XXX - interrupt control
* 0xb0ec3XXX - ps2 port (touch pad on aero 8000)
* 0xb0ec6XXX - i2c
* 0xb0ec7000 - first serial port (proprietary connector on aero 8000)
* 0xb0ec8000 - second serial port
* 0xb0ec9000 - third serial port
* 0xb0eca000 - fourth serial port (keyboard controller on aero 8000)
* 0xb0eccXXX - GPIO
* 0xb0ecdXXX - GPIO
*/
#define EC3104_BASE 0xb0ec0000
#define EC3104_SER4_DATA (EC3104_BASE+0xa000)
#define EC3104_SER4_IIR (EC3104_BASE+0xa008)
#define EC3104_SER4_MCR (EC3104_BASE+0xa010)
#define EC3104_SER4_LSR (EC3104_BASE+0xa014)
#define EC3104_SER4_MSR (EC3104_BASE+0xa018)
/*
* our ISA bus. this seems to be real ISA.
*/
#define EC3104_ISA_BASE 0xa5000000
#define EC3104_IRQ 11
#define EC3104_IRQBASE 64
#define EC3104_IRQ_SER1 EC3104_IRQBASE + 7
#define EC3104_IRQ_SER2 EC3104_IRQBASE + 8
#define EC3104_IRQ_SER3 EC3104_IRQBASE + 9
#define EC3104_IRQ_SER4 EC3104_IRQBASE + 10
#endif /* __ASM_EC3104_H */

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#ifndef _ASM_SH_IO_EC3104_H
#define _ASM_SH_IO_EC3104_H
#include <linux/types.h>
extern unsigned char ec3104_inb(unsigned long port);
extern unsigned short ec3104_inw(unsigned long port);
extern unsigned long ec3104_inl(unsigned long port);
extern void ec3104_outb(unsigned char value, unsigned long port);
extern void ec3104_outw(unsigned short value, unsigned long port);
extern void ec3104_outl(unsigned long value, unsigned long port);
extern int ec3104_irq_demux(int irq);
#endif /* _ASM_SH_IO_EC3104_H */

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extern unsigned char ec3104_kbd_sysrq_xlate[];
extern int ec3104_kbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int ec3104_kbd_getkeycode(unsigned int scancode);
extern int ec3104_kbd_translate(unsigned char, unsigned char *, char);
extern char ec3104_kbd_unexpected_up(unsigned char);
extern void ec3104_kbd_leds(unsigned char);
extern void ec3104_kbd_init_hw(void);
#define SYSRQ_KEY 0x54
#define kbd_sysrq_xlate ec3104_kbd_sysrq_xlate
#define kbd_setkeycode ec3104_kbd_setkeycode
#define kbd_getkeycode ec3104_kbd_getkeycode
#define kbd_translate ec3104_kbd_translate
#define kbd_unexpected_up ec3104_kbd_unexpected_up
#define kbd_leds ec3104_kbd_leds
#define kbd_init_hw ec3104_kbd_init_hw

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#include <asm/ec3104.h>
/* Naturally we don't know the exact value but 115200 baud has a divisor
* of 9 and 19200 baud has a divisor of 52, so this seems like a good
* guess. */
#define BASE_BAUD (16800000 / 16)
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
/* there is a fourth serial port with the expected values as well, but
* it's got the keyboard controller behind it so we can't really use it
* (without moving the keyboard driver to userspace, which doesn't sound
* like a very good idea) */
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
{ 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
/* XXX: This should be moved ino irq.h */
#define irq_cannonicalize(x) (x)

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/*
* include/asm-sh/edosk7705/io.h
*
* Modified version of io_se.h for the EDOSK7705 specific functions.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an Hitachi EDOSK7705 development board
*/
#ifndef __ASM_SH_EDOSK7705_IO_H
#define __ASM_SH_EDOSK7705_IO_H
#include <asm/io_generic.h>
extern unsigned char sh_edosk7705_inb(unsigned long port);
extern unsigned int sh_edosk7705_inl(unsigned long port);
extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
#endif /* __ASM_SH_EDOSK7705_IO_H */

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#ifndef __ASM_SH_ELF_H
#define __ASM_SH_ELF_H
/* SH relocation types */
#define R_SH_NONE 0
#define R_SH_DIR32 1
#define R_SH_REL32 2
#define R_SH_DIR8WPN 3
#define R_SH_IND12W 4
#define R_SH_DIR8WPL 5
#define R_SH_DIR8WPZ 6
#define R_SH_DIR8BP 7
#define R_SH_DIR8W 8
#define R_SH_DIR8L 9
#define R_SH_SWITCH16 25
#define R_SH_SWITCH32 26
#define R_SH_USES 27
#define R_SH_COUNT 28
#define R_SH_ALIGN 29
#define R_SH_CODE 30
#define R_SH_DATA 31
#define R_SH_LABEL 32
#define R_SH_SWITCH8 33
#define R_SH_GNU_VTINHERIT 34
#define R_SH_GNU_VTENTRY 35
#define R_SH_TLS_GD_32 144
#define R_SH_TLS_LD_32 145
#define R_SH_TLS_LDO_32 146
#define R_SH_TLS_IE_32 147
#define R_SH_TLS_LE_32 148
#define R_SH_TLS_DTPMOD32 149
#define R_SH_TLS_DTPOFF32 150
#define R_SH_TLS_TPOFF32 151
#define R_SH_GOT32 160
#define R_SH_PLT32 161
#define R_SH_COPY 162
#define R_SH_GLOB_DAT 163
#define R_SH_JMP_SLOT 164
#define R_SH_RELATIVE 165
#define R_SH_GOTOFF 166
#define R_SH_GOTPC 167
/* Keep this the last entry. */
#define R_SH_NUM 256
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fpu_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ( (x)->e_machine == EM_SH )
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#ifdef __LITTLE_ENDIAN__
#define ELF_DATA ELFDATA2LSB
#else
#define ELF_DATA ELFDATA2MSB
#endif
#define ELF_ARCH EM_SH
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
#define ELF_CORE_COPY_REGS(_dest,_regs) \
memcpy((char *) &_dest, (char *) _regs, \
sizeof(struct pt_regs));
/* This yields a mask that user programs can use to figure out what
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
For the moment, we have only optimizations for the Intel generations,
but that could change... */
#define ELF_PLATFORM (NULL)
#define ELF_PLAT_INIT(_r, load_addr) \
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
_r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
_r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
_r->sr = SR_FD; } while (0)
#ifdef __KERNEL__
#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
#endif
#endif /* __ASM_SH_ELF_H */

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include/asm-sh/errno.h Normal file
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#ifndef __ASM_SH_ERRNO_H
#define __ASM_SH_ERRNO_H
#include <asm-generic/errno.h>
#endif /* __ASM_SH_ERRNO_H */

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include/asm-sh/fcntl.h Normal file
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#ifndef __ASM_SH_FCNTL_H
#define __ASM_SH_FCNTL_H
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
#define O_ACCMODE 0003
#define O_RDONLY 00
#define O_WRONLY 01
#define O_RDWR 02
#define O_CREAT 0100 /* not fcntl */
#define O_EXCL 0200 /* not fcntl */
#define O_NOCTTY 0400 /* not fcntl */
#define O_TRUNC 01000 /* not fcntl */
#define O_APPEND 02000
#define O_NONBLOCK 04000
#define O_NDELAY O_NONBLOCK
#define O_SYNC 010000
#define FASYNC 020000 /* fcntl, for BSD compatibility */
#define O_DIRECT 040000 /* direct disk access hint - currently ignored */
#define O_LARGEFILE 0100000
#define O_DIRECTORY 0200000 /* must be a directory */
#define O_NOFOLLOW 0400000 /* don't follow links */
#define O_NOATIME 01000000
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get close_on_exec */
#define F_SETFD 2 /* set/clear close_on_exec */
#define F_GETFL 3 /* get file->f_flags */
#define F_SETFL 4 /* set file->f_flags */
#define F_GETLK 5
#define F_SETLK 6
#define F_SETLKW 7
#define F_SETOWN 8 /* for sockets. */
#define F_GETOWN 9 /* for sockets. */
#define F_SETSIG 10 /* for sockets. */
#define F_GETSIG 11 /* for sockets. */
#define F_GETLK64 12 /* using 'struct flock64' */
#define F_SETLK64 13
#define F_SETLKW64 14
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
/* for posix fcntl() and lockf() */
#define F_RDLCK 0
#define F_WRLCK 1
#define F_UNLCK 2
/* for old implementation of bsd flock () */
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
/* for leases */
#define F_INPROGRESS 16
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
#define LOCK_MAND 32 /* This is a mandatory flock */
#define LOCK_READ 64 /* ... Which allows concurrent read operations */
#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
struct flock {
short l_type;
short l_whence;
off_t l_start;
off_t l_len;
pid_t l_pid;
};
struct flock64 {
short l_type;
short l_whence;
loff_t l_start;
loff_t l_len;
pid_t l_pid;
};
#define F_LINUX_SPECIFIC_BASE 1024
#endif /* __ASM_SH_FCNTL_H */

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/*
* fixmap.h: compile-time virtual memory allocation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Ingo Molnar
*
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
*/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/page.h>
#ifdef CONFIG_HIGHMEM
#include <linux/threads.h>
#include <asm/kmap_types.h>
#endif
/*
* Here we define all the compile-time 'special' virtual
* addresses. The point is to have a constant address at
* compile time, but to set the physical address only
* in the boot process. We allocate these special addresses
* from the end of virtual memory (0xfffff000) backwards.
* Also this lets us do fail-safe vmalloc(), we
* can guarantee that these special addresses and
* vmalloc()-ed addresses never overlap.
*
* these 'compile-time allocated' memory buffers are
* fixed-size 4k pages. (or larger if used with an increment
* highger than 1) use fixmap_set(idx,phys) to associate
* physical memory with fixmap indices.
*
* TLB entries of such buffers will not be flushed across
* task switches.
*/
/*
* on UP currently we will have no trace of the fixmap mechanizm,
* no page table allocations, etc. This might change in the
* future, say framebuffers for the console driver(s) could be
* fix-mapped?
*/
enum fixed_addresses {
#ifdef CONFIG_HIGHMEM
FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
#endif
__end_of_fixed_addresses
};
extern void __set_fixmap (enum fixed_addresses idx,
unsigned long phys, pgprot_t flags);
#define set_fixmap(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL)
/*
* Some hardware wants to get fixmapped without caching.
*/
#define set_fixmap_nocache(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
/*
* used by vmalloc.c.
*
* Leave one empty page between vmalloc'ed areas and
* the start of the fixmap, and leave one page empty
* at the top of mem..
*/
#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
extern void __this_fixmap_does_not_exist(void);
/*
* 'index to address' translation. If anyone tries to use the idx
* directly without tranlation, we catch the bug with a NULL-deference
* kernel oops. Illegal ranges of incoming indices are caught too.
*/
static inline unsigned long fix_to_virt(const unsigned int idx)
{
/*
* this branch gets completely eliminated after inlining,
* except when someone tries to use fixaddr indices in an
* illegal way. (such as mixing up address types or using
* out-of-range indices).
*
* If it doesn't get removed, the linker will complain
* loudly with a reasonably clear error message..
*/
if (idx >= __end_of_fixed_addresses)
__this_fixmap_does_not_exist();
return __fix_to_virt(idx);
}
static inline unsigned long virt_to_fix(const unsigned long vaddr)
{
BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
return __virt_to_fix(vaddr);
}
#endif

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/*
* include/asm-sh/flat.h
*
* uClinux flat-format executables
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive for
* more details.
*/
#ifndef __ASM_SH_FLAT_H
#define __ASM_SH_FLAT_H
#define flat_stack_align(sp) /* nothing needed */
#define flat_argvp_envp_on_stack() 1
#define flat_old_ram_flag(flags) (flags)
#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
#define flat_get_relocate_addr(rel) (rel)
#endif /* __ASM_SH_FLAT_H */

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/*
* Architecture specific parts of the Floppy driver
* include/asm-i386/floppy.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995
*/
#ifndef __ASM_SH_FLOPPY_H
#define __ASM_SH_FLOPPY_H
#include <linux/vmalloc.h>
/*
* The DMA channel used by the floppy controller cannot access data at
* addresses >= 16MB
*
* Went back to the 1MB limit, as some people had problems with the floppy
* driver otherwise. It doesn't matter much for performance anyway, as most
* floppy accesses go through the track buffer.
*/
#define _CROSS_64KB(a,s,vdma) \
(!vdma && ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64))
#define CROSS_64KB(a,s) _CROSS_64KB(a,s,use_virtual_dma & 1)
#define SW fd_routine[use_virtual_dma&1]
#define CSW fd_routine[can_use_virtual_dma & 1]
#define fd_inb(port) inb_p(port)
#define fd_outb(value,port) outb_p(value,port)
#define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy")
#define fd_free_dma() CSW._free_dma(FLOPPY_DMA)
#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL)
#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
#define FLOPPY_CAN_FALLBACK_ON_NODMA
static int virtual_dma_count;
static int virtual_dma_residue;
static char *virtual_dma_addr;
static int virtual_dma_mode;
static int doing_pdma;
static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs)
{
register unsigned char st;
#undef TRACE_FLPY_INT
#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
#endif
if(!doing_pdma) {
floppy_interrupt(irq, dev_id, regs);
return;
}
#ifdef TRACE_FLPY_INT
if(!calls)
bytes = virtual_dma_count;
#endif
{
register int lcount;
register char *lptr;
st = 1;
for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
st=inb(virtual_dma_port+4) & 0xa0 ;
if(st != 0xa0)
break;
if(virtual_dma_mode)
outb_p(*lptr, virtual_dma_port+5);
else
*lptr = inb_p(virtual_dma_port+5);
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
st = inb(virtual_dma_port+4);
}
#ifdef TRACE_FLPY_INT
calls++;
#endif
if(st == 0x20)
return;
if(!(st & 0x20)) {
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
#ifdef TRACE_FLPY_INT
printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
dma_wait=0;
#endif
doing_pdma = 0;
floppy_interrupt(irq, dev_id, regs);
return;
}
#ifdef TRACE_FLPY_INT
if(!virtual_dma_count)
dma_wait++;
#endif
}
static void fd_disable_dma(void)
{
if(! (can_use_virtual_dma & 1))
disable_dma(FLOPPY_DMA);
doing_pdma = 0;
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
}
static int vdma_request_dma(unsigned int dmanr, const char * device_id)
{
return 0;
}
static void vdma_nop(unsigned int dummy)
{
}
static int vdma_get_dma_residue(unsigned int dummy)
{
return virtual_dma_count + virtual_dma_residue;
}
static int fd_request_irq(void)
{
if(can_use_virtual_dma)
return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT,
"floppy", NULL);
else
return request_irq(FLOPPY_IRQ, floppy_interrupt,
SA_INTERRUPT|SA_SAMPLE_RANDOM,
"floppy", NULL);
}
static unsigned long dma_mem_alloc(unsigned long size)
{
return __get_dma_pages(GFP_KERNEL,get_order(size));
}
static unsigned long vdma_mem_alloc(unsigned long size)
{
return (unsigned long) vmalloc(size);
}
#define nodma_mem_alloc(size) vdma_mem_alloc(size)
static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
{
if((unsigned int) addr >= (unsigned int) high_memory)
return vfree((void *)addr);
else
free_pages(addr, get_order(size));
}
#define fd_dma_mem_free(addr, size) _fd_dma_mem_free(addr, size)
static void _fd_chose_dma_mode(char *addr, unsigned long size)
{
if(can_use_virtual_dma == 2) {
if((unsigned int) addr >= (unsigned int) high_memory ||
virt_to_bus(addr) >= 0x10000000)
use_virtual_dma = 1;
else
use_virtual_dma = 0;
} else {
use_virtual_dma = can_use_virtual_dma & 1;
}
}
#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size)
static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
{
doing_pdma = 1;
virtual_dma_port = io;
virtual_dma_mode = (mode == DMA_MODE_WRITE);
virtual_dma_addr = addr;
virtual_dma_count = size;
virtual_dma_residue = 0;
return 0;
}
static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
{
#ifdef FLOPPY_SANITY_CHECK
if (CROSS_64KB(addr, size)) {
printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size);
return -1;
}
#endif
dma_cache_wback_inv(addr, size);
/* actual, physical DMA */
doing_pdma = 0;
clear_dma_ff(FLOPPY_DMA);
set_dma_mode(FLOPPY_DMA,mode);
set_dma_addr(FLOPPY_DMA,virt_to_bus(addr));
set_dma_count(FLOPPY_DMA,size);
enable_dma(FLOPPY_DMA);
return 0;
}
struct fd_routine_l {
int (*_request_dma)(unsigned int dmanr, const char * device_id);
void (*_free_dma)(unsigned int dmanr);
int (*_get_dma_residue)(unsigned int dummy);
unsigned long (*_dma_mem_alloc) (unsigned long size);
int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
} fd_routine[] = {
{
request_dma,
free_dma,
get_dma_residue,
dma_mem_alloc,
hard_dma_setup
},
{
vdma_request_dma,
vdma_nop,
vdma_get_dma_residue,
vdma_mem_alloc,
vdma_dma_setup
}
};
static int FDC1 = 0x3f0;
static int FDC2 = -1;
/*
* Floppy types are stored in the rtc's CMOS RAM and so rtc_lock
* is needed to prevent corrupted CMOS RAM in case "insmod floppy"
* coincides with another rtc CMOS user. Paul G.
*/
#define FLOPPY0_TYPE (4)
#define FLOPPY1_TYPE (0)
#define N_FDC 2
#define N_DRIVE 8
#define FLOPPY_MOTOR_MASK 0xf0
#define AUTO_DMA
#define EXTRA_FLOPPY_PARAMS
#endif /* __ASM_SH_FLOPPY_H */

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/*
* include/asm-sh/freq.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASM_SH_FREQ_H
#define __ASM_SH_FREQ_H
#ifdef __KERNEL__
#include <asm/cpu/freq.h>
/* arch/sh/kernel/time.c */
extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc);
extern unsigned int get_ifc_divisor(unsigned int value);
extern unsigned int get_ifc_divisor(unsigned int value);
extern unsigned int get_ifc_divisor(unsigned int value);
extern unsigned int get_ifc_value(unsigned int divisor);
extern unsigned int get_pfc_value(unsigned int divisor);
extern unsigned int get_bfc_value(unsigned int divisor);
#endif /* __KERNEL__ */
#endif /* __ASM_SH_FREQ_H */

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#ifndef __ASM_SH_HARDIRQ_H
#define __ASM_SH_HARDIRQ_H
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/irq.h>
/* entry.S is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
extern void ack_bad_irq(unsigned int irq);
#endif /* __ASM_SH_HARDIRQ_H */

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/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Defintions applicable to the STMicroelectronics ST40STB1 HARP and
* compatible boards.
*/
#if defined(CONFIG_SH_STB1_HARP)
#define EPLD_BASE 0xa0800000
#define EPLD_LED (EPLD_BASE+0x000c0000)
#define EPLD_INTSTAT0 (EPLD_BASE+0x00200000)
#define EPLD_INTSTAT1 (EPLD_BASE+0x00240000)
#define EPLD_INTMASK0 (EPLD_BASE+0x00280000)
#define EPLD_INTMASK1 (EPLD_BASE+0x002c0000)
#define EPLD_PAGEADDR (EPLD_BASE+0x00300000)
#define EPLD_REVID1 (EPLD_BASE+0x00380000)
#define EPLD_REVID2 (EPLD_BASE+0x003c0000)
#define EPLD_LED_ON 1
#define EPLD_LED_OFF 0
#elif defined(CONFIG_SH_STB1_OVERDRIVE)
#define EPLD_BASE 0xa7000000
#define EPLD_REVID (EPLD_BASE+0x00000000)
#define EPLD_LED (EPLD_BASE+0x00040000)
#define EPLD_INTMASK0 (EPLD_BASE+0x001c0000)
#define EPLD_INTMASK1 (EPLD_BASE+0x00200000)
#define EPLD_INTSTAT0 (EPLD_BASE+0x00240000)
#define EPLD_INTSTAT1 (EPLD_BASE+0x00280000)
#define EPLD_LED_ON 0
#define EPLD_LED_OFF 1
#else
#error Unknown board
#endif

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#ifndef __ASM_SH_HARP_IO_H
#define __ASM_SH_HARP_IO_H
/*
* Nothing special here.. just use the generic cchip io routines.
*/
#include <asm/hd64465/io.h>
#endif /* __ASM_SH_HARP_IO_H */

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#ifndef __ASM_SH_HD64461
#define __ASM_SH_HD64461
/*
* $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
* Copyright (C) 2000 YAEGASHI Takeshi
* Hitachi HD64461 companion chip support
*/
#include <linux/config.h>
/* Constants for PCMCIA mappings */
#define HD64461_PCC_WINDOW 0x01000000
#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */
#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE)
#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */
#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE)
#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
#define HD64461_STBCR 0x10000
#define HD64461_STBCR_CKIO_STBY 0x2000
#define HD64461_STBCR_SAFECKE_IST 0x1000
#define HD64461_STBCR_SLCKE_IST 0x0800
#define HD64461_STBCR_SAFECKE_OST 0x0400
#define HD64461_STBCR_SLCKE_OST 0x0200
#define HD64461_STBCR_SMIAST 0x0100
#define HD64461_STBCR_SLCDST 0x0080
#define HD64461_STBCR_SPC0ST 0x0040
#define HD64461_STBCR_SPC1ST 0x0020
#define HD64461_STBCR_SAFEST 0x0010
#define HD64461_STBCR_STM0ST 0x0008
#define HD64461_STBCR_STM1ST 0x0004
#define HD64461_STBCR_SIRST 0x0002
#define HD64461_STBCR_SURTST 0x0001
#define HD64461_SYSCR 0x10002
#define HD64461_SCPUCR 0x10004
#define HD64461_LCDCBAR 0x11000
#define HD64461_LCDCLOR 0x11002
#define HD64461_LCDCCR 0x11004
#define HD64461_LCDCCR_MOFF 0x80
#define HD64461_LDR1 0x11010
#define HD64461_LDR1_DON 0x01
#define HD64461_LDR1_DINV 0x80
#define HD64461_LDR2 0x11012
#define HD64461_LDHNCR 0x11014
#define HD64461_LDHNSR 0x11016
#define HD64461_LDVNTR 0x11018
#define HD64461_LDVNDR 0x1101a
#define HD64461_LDVSPR 0x1101c
#define HD64461_LDR3 0x1101e
#define HD64461_CPTWAR 0x11030
#define HD64461_CPTWDR 0x11032
#define HD64461_CPTRAR 0x11034
#define HD64461_CPTRDR 0x11036
#define HD64461_GRDOR 0x11040
#define HD64461_GRSCR 0x11042
#define HD64461_GRCFGR 0x11044
#define HD64461_GRCFGR_ACCSTATUS 0x10
#define HD64461_GRCFGR_ACCRESET 0x08
#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06
#define HD64461_GRCFGR_ACCSTART_LINE 0x04
#define HD64461_GRCFGR_COLORDEPTH16 0x01
#define HD64461_LNSARH 0x11046
#define HD64461_LNSARL 0x11048
#define HD64461_LNAXLR 0x1104a
#define HD64461_LNDGR 0x1104c
#define HD64461_LNAXR 0x1104e
#define HD64461_LNERTR 0x11050
#define HD64461_LNMDR 0x11052
#define HD64461_BBTSSARH 0x11054
#define HD64461_BBTSSARL 0x11056
#define HD64461_BBTDSARH 0x11058
#define HD64461_BBTDSARL 0x1105a
#define HD64461_BBTDWR 0x1105c
#define HD64461_BBTDHR 0x1105e
#define HD64461_BBTPARH 0x11060
#define HD64461_BBTPARL 0x11062
#define HD64461_BBTMARH 0x11064
#define HD64461_BBTMARL 0x11066
#define HD64461_BBTROPR 0x11068
#define HD64461_BBTMDR 0x1106a
/* PC Card Controller Registers */
#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */
#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */
#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */
#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */
#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */
#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */
#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */
#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */
/* PCC Interface Status Register */
#define HD64461_PCCISR_READY 0x80 /* card ready */
#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
/* PCC General Control Register */
#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
/* PCC Card Status Change Register */
#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
#define HD64461_PCCCSCR_RC 0x04 /* READY change */
#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
/* PCC Card Status Change Interrupt Enable Register */
#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
/* PCC Software Control Register */
#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
#define HD64461_PCCSCR_SWP 0x01 /* write protect */
#define HD64461_P0OCR 0x1202a
#define HD64461_P1OCR 0x1202c
#define HD64461_PGCR 0x1202e
#define HD64461_GPACR 0x14000
#define HD64461_GPBCR 0x14002
#define HD64461_GPCCR 0x14004
#define HD64461_GPDCR 0x14006
#define HD64461_GPADR 0x14010
#define HD64461_GPBDR 0x14012
#define HD64461_GPCDR 0x14014
#define HD64461_GPDDR 0x14016
#define HD64461_GPAICR 0x14020
#define HD64461_GPBICR 0x14022
#define HD64461_GPCICR 0x14024
#define HD64461_GPDICR 0x14026
#define HD64461_GPAISR 0x14040
#define HD64461_GPBISR 0x14042
#define HD64461_GPCISR 0x14044
#define HD64461_GPDISR 0x14046
#define HD64461_NIRR 0x15000
#define HD64461_NIMR 0x15002
#ifndef CONFIG_HD64461_IOBASE
#define CONFIG_HD64461_IOBASE 0xb0000000
#endif
#ifndef CONFIG_HD64461_IRQ
#define CONFIG_HD64461_IRQ 36
#endif
#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
#define HD64461_IRQ_NUM 16
#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
#endif

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/*
* include/asm-sh/io_hd64461.h
*
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an HD64461
*/
#ifndef _ASM_SH_IO_HD64461_H
#define _ASM_SH_IO_HD64461_H
extern unsigned char hd64461_inb(unsigned long port);
extern unsigned short hd64461_inw(unsigned long port);
extern unsigned int hd64461_inl(unsigned long port);
extern void hd64461_outb(unsigned char value, unsigned long port);
extern void hd64461_outw(unsigned short value, unsigned long port);
extern void hd64461_outl(unsigned int value, unsigned long port);
extern unsigned char hd64461_inb_p(unsigned long port);
extern void hd64461_outb_p(unsigned char value, unsigned long port);
extern void hd64461_insb(unsigned long port, void *addr, unsigned long count);
extern void hd64461_insw(unsigned long port, void *addr, unsigned long count);
extern void hd64461_insl(unsigned long port, void *addr, unsigned long count);
extern void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count);
extern void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count);
extern void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count);
extern unsigned short hd64461_readw(unsigned long addr);
extern void hd64461_writew(unsigned short b, unsigned long addr);
extern int hd64461_irq_demux(int irq);
extern void hd64461_register_irq_demux(int irq,
int (*demux)(int irq, void *dev), void *dev);
extern void hd64461_unregister_irq_demux(int irq);
#endif /* _ASM_SH_IO_HD64461_H */

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#ifndef _ASM_SH_HD64465_GPIO_
#define _ASM_SH_HD64465_GPIO_ 1
/*
* $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
*
* Hitachi HD64465 companion chip: General Purpose IO pins support.
* This layer enables other device drivers to configure GPIO
* pins, get and set their values, and register an interrupt
* routine for when input pins change in hardware.
*
* by Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc.
*/
#include <asm/hd64465.h>
/* Macro to construct a portpin number (used in all
* subsequent functions) from a port letter and a pin
* number, e.g. HD64465_GPIO_PORTPIN('A', 5).
*/
#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
/* Pin configuration constants for _configure() */
#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
#define HD64465_GPIO_OUT 1 /* output */
#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
#define HD64465_GPIO_IN 3 /* input */
/* Configure a pin's direction */
extern void hd64465_gpio_configure(int portpin, int direction);
/* Get, set value */
extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
extern unsigned int hd64465_gpio_get_pin(int portpin);
extern void hd64465_gpio_set_port(int port, unsigned int value);
extern unsigned int hd64465_gpio_get_port(int port);
/* mode constants for _register_irq() */
#define HD64465_GPIO_FALLING 0
#define HD64465_GPIO_RISING 1
/* Interrupt on external value change */
extern void hd64465_gpio_register_irq(int portpin, int mode,
void (*handler)(int portpin, void *dev), void *dev);
extern void hd64465_gpio_unregister_irq(int portpin);
#endif /* _ASM_SH_HD64465_GPIO_ */

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#ifndef _ASM_SH_HD64465_
#define _ASM_SH_HD64465_ 1
/*
* $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
*
* Hitachi HD64465 companion chip support
*
* by Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc.
*
* Derived from <asm/hd64461.h> which bore the message:
* Copyright (C) 2000 YAEGASHI Takeshi
*/
#include <linux/config.h>
#include <asm/io.h>
#include <asm/irq.h>
/*
* Note that registers are defined here as virtual port numbers,
* which have no meaning except to get translated by hd64465_isa_port2addr()
* to an address in the range 0xb0000000-0xb3ffffff. Note that
* this translation happens to consist of adding the lower 16 bits
* of the virtual port number to 0xb0000000. Note also that the manual
* shows addresses as absolute physical addresses starting at 0x10000000,
* so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
* manual, and accessed using address 0xb0005000 - Greg.
*/
/* System registers */
#define HD64465_REG_SRR 0x1000c /* System Revision Register */
#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
#define HD64465_SDID 0x8122 /* 64465 device ID */
/* Power Management registers */
#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
/* Interrupt Controller registers */
#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
/* Timer registers */
#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
#define HD64465_TCR_PST_1 0x06 /* 1:1 */
#define HD64465_TCR_PST_4 0x04 /* 1:4 */
#define HD64465_TCR_PST_8 0x02 /* 1:8 */
#define HD64465_TCR_PST_16 0x00 /* 1:16 */
#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
/* Analog/Digital Converter registers */
#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
/* General Purpose I/O ports registers */
#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
/* PCMCIA bridge interface */
#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
#define HD64465_PCCISR_PIREQ 0x80
#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
#define HD64465_PCCSCR_SWP 0x01 /* write protect */
#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
/* PS/2 Keyboard and mouse controller -- *not* register compatible */
#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
/*
* Logical address at which the HD64465 is mapped. Note that this
* should always be in the P2 segment (uncached and untranslated).
*/
#ifndef CONFIG_HD64465_IOBASE
#define CONFIG_HD64465_IOBASE 0xb0000000
#endif
/*
* The HD64465 multiplexes all its modules' interrupts onto
* this single interrupt.
*/
#ifndef CONFIG_HD64465_IRQ
#define CONFIG_HD64465_IRQ 5
#endif
#define _HD64465_IO_MASK 0xf8000000
#define is_hd64465_addr(addr) \
((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
/*
* A range of 16 virtual interrupts generated by
* demuxing the HD64465 muxed interrupt.
*/
#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
#define HD64465_IRQ_NUM 16
#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
/* bit 4 is reserved */
#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
/* Constants for PCMCIA mappings */
#define HD64465_PCC_WINDOW 0x01000000
#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
/*
* Base of USB controller interface (as memory)
*/
#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
#define HD64465_USB_LEN 0x1000
/*
* Base of embedded SRAM, used for USB controller.
*/
#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
#define HD64465_SRAM_LEN 0x1000
#endif /* _ASM_SH_HD64465_ */

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/*
* include/asm-sh/io_hd64465.h
*
* By Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc.
*
* Derived from io_hd64461.h, which bore the message:
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
*/
#ifndef _ASM_SH_IO_HD64465_H
#define _ASM_SH_IO_HD64465_H
extern unsigned char hd64465_inb(unsigned long port);
extern unsigned short hd64465_inw(unsigned long port);
extern unsigned int hd64465_inl(unsigned long port);
extern void hd64465_outb(unsigned char value, unsigned long port);
extern void hd64465_outw(unsigned short value, unsigned long port);
extern void hd64465_outl(unsigned int value, unsigned long port);
extern unsigned char hd64465_inb_p(unsigned long port);
extern void hd64465_outb_p(unsigned char value, unsigned long port);
extern unsigned long hd64465_isa_port2addr(unsigned long offset);
extern int hd64465_irq_demux(int irq);
/* Provision for generic secondary demux step -- used by PCMCIA code */
extern void hd64465_register_irq_demux(int irq,
int (*demux)(int irq, void *dev), void *dev);
extern void hd64465_unregister_irq_demux(int irq);
/* Set this variable to 1 to see port traffic */
extern int hd64465_io_debug;
/* Map a range of ports to a range of kernel virtual memory.
*/
extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
unsigned long addr, unsigned char shift);
extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
#endif /* _ASM_SH_IO_HD64465_H */

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include/asm-sh/hdreg.h Normal file
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#include <asm-generic/hdreg.h>

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#ifndef __ASM_SH_HP6XX_H
#define __ASM_SH_HP6XX_H
/*
* Copyright (C) 2003 Andriy Skulysh
*/
#define HP680_TS_IRQ IRQ3_IRQ
#define DAC_LCD_BRIGHTNESS 0
#define DAC_SPEAKER_VOLUME 1
#define PHDR_TS_PEN_DOWN 0x08
#define SCPDR_TS_SCAN_ENABLE 0x20
#define SCPDR_TS_SCAN_Y 0x02
#define SCPDR_TS_SCAN_X 0x01
#define SCPCR_TS_ENABLE 0x405
#define SCPCR_TS_MASK 0xc0f
#define ADC_CHANNEL_TS_Y 1
#define ADC_CHANNEL_TS_X 2
#define HD64461_GPADR_SPEAKER 0x01
#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
#define HD64461_GPBDR_LCDOFF 0x01
#define HD64461_GPBDR_LED_RED 0x80
#endif /* __ASM_SH_HP6XX_H */

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#ifndef __ASM_SH_HP6XX_IDE_H
#define __ASM_SH_HP6XX_IDE_H
#define IRQ_CFCARD 93
#define IRQ_PCMCIA 94
#endif /* __ASM_SH_HP6XX_IDE_H */

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#ifndef __ASM_SH_HP6XX_IO_H
#define __ASM_SH_HP6XX_IO_H
/*
* Nothing special here.. just use the generic cchip io routines.
*/
#include <asm/hd64461/io.h>
#endif /* __ASM_SH_HP6XX_IO_H */

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#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H
#define __ASM_SH_RENESAS_HS7751RVOIP_H
/*
* linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h
*
* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
*
* Renesas Technology Sales HS7751RVoIP support
*/
/* Box specific addresses. */
#define PA_BCR 0xa4000000 /* FPGA */
#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */
#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */
#define PA_DMACNTR 0xa400000a /* USB DMA Control */
#define PA_INPORTR 0xa400000c /* Input Port Register */
#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
#define PA_VERREG 0xa4000014 /* FPGA Version Register */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */
#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */
#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */
#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */
#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */
#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */
#define IRQ_USBCOM 8 /* USB Comunication IRQ */
#define IRQ_USBCON 9 /* USB Connect IRQ */
#define IRQ_USBDMA 10 /* USB DMA IRQ */
#define IRQ_CFCARD 11 /* CF Card IRQ */
#define IRQ_PCMCIA 12 /* PCMCIA IRQ */
#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */
#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */
#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */
#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */
#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */
#define IRQ_RINGING 4 /* Ringing IRQ */
#define IRQ_CODEC 5 /* CODEC IRQ */
#endif /* __ASM_SH_RENESAS_HS7751RVOIP */

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#ifndef __ASM_SH_HS7751RVOIP_IDE_H
#define __ASM_SH_HS7751RVOIP_IDE_H
/* Nothing to see here.. */
#include <asm/hs7751rvoip/hs7751rvoip.h>
#endif /* __ASM_SH_HS7751RVOIP_IDE_H */

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/*
* include/asm-sh/hs7751rvoip/hs7751rvoip.h
*
* Modified version of io_se.h for the hs7751rvoip-specific functions.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an Renesas Technology sales HS7751RVOIP
*/
#ifndef _ASM_SH_IO_HS7751RVOIP_H
#define _ASM_SH_IO_HS7751RVOIP_H
#include <asm/io_generic.h>
extern unsigned char hs7751rvoip_inb(unsigned long port);
extern unsigned short hs7751rvoip_inw(unsigned long port);
extern unsigned int hs7751rvoip_inl(unsigned long port);
extern void hs7751rvoip_outb(unsigned char value, unsigned long port);
extern void hs7751rvoip_outw(unsigned short value, unsigned long port);
extern void hs7751rvoip_outl(unsigned int value, unsigned long port);
extern unsigned char hs7751rvoip_inb_p(unsigned long port);
extern void hs7751rvoip_outb_p(unsigned char value, unsigned long port);
extern void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count);
extern void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count);
extern void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count);
extern void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count);
extern void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count);
extern void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count);
extern void *hs7751rvoip_ioremap(unsigned long offset, unsigned long size);
extern unsigned long hs7751rvoip_isa_port2addr(unsigned long offset);
#endif /* _ASM_SH_IO_HS7751RVOIP_H */

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include/asm-sh/hw_irq.h Normal file
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#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H
static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
{
/* Nothing to do */
}
#endif /* __ASM_SH_HW_IRQ_H */

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/*
* linux/include/asm-sh/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
/*
* This file contains the i386 architecture specific IDE code.
* In future, SuperH code.
*/
#ifndef __ASM_SH_IDE_H
#define __ASM_SH_IDE_H
#ifdef __KERNEL__
#include <linux/config.h>
#ifndef MAX_HWIFS
#define MAX_HWIFS CONFIG_IDE_MAX_HWIFS
#endif
#define ide_default_io_ctl(base) (0)
#include <asm-generic/ide_iops.h>
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IDE_H */

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#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H
/*
* Convention:
* read{b,w,l}/write{b,w,l} are for PCI,
* while in{b,w,l}/out{b,w,l} are for ISA
* These may (will) be platform specific function.
* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
* and 'string' versions: ins{b,w,l}/outs{b,w,l}
* For read{b,w,l} and write{b,w,l} there are also __raw versions, which
* do not have a memory barrier after them.
*
* In addition, we have
* ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
* which are processor specific.
*/
/*
* We follow the Alpha convention here:
* __inb expands to an inline function call (which calls via the mv)
* _inb is a real function call (note ___raw fns are _ version of __raw)
* inb by default expands to _inb, but the machine specific code may
* define it to __inb if it chooses.
*/
#include <asm/cache.h>
#include <asm/system.h>
#include <asm/addrspace.h>
#include <asm/machvec.h>
#include <linux/config.h>
/*
* Depending on which platform we are running on, we need different
* I/O functions.
*/
#ifdef __KERNEL__
/*
* Since boards are able to define their own set of I/O routines through
* their respective machine vector, we always wrap through the mv.
*
* Also, in the event that a board hasn't provided its own definition for
* a given routine, it will be wrapped to generic code at run-time.
*/
# define __inb(p) sh_mv.mv_inb((p))
# define __inw(p) sh_mv.mv_inw((p))
# define __inl(p) sh_mv.mv_inl((p))
# define __outb(x,p) sh_mv.mv_outb((x),(p))
# define __outw(x,p) sh_mv.mv_outw((x),(p))
# define __outl(x,p) sh_mv.mv_outl((x),(p))
# define __inb_p(p) sh_mv.mv_inb_p((p))
# define __inw_p(p) sh_mv.mv_inw_p((p))
# define __inl_p(p) sh_mv.mv_inl_p((p))
# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
# define __readb(a) sh_mv.mv_readb((a))
# define __readw(a) sh_mv.mv_readw((a))
# define __readl(a) sh_mv.mv_readl((a))
# define __writeb(v,a) sh_mv.mv_writeb((v),(a))
# define __writew(v,a) sh_mv.mv_writew((v),(a))
# define __writel(v,a) sh_mv.mv_writel((v),(a))
# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s))
# define __iounmap(a) sh_mv.mv_iounmap((a))
# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a)
# define inb __inb
# define inw __inw
# define inl __inl
# define outb __outb
# define outw __outw
# define outl __outl
# define inb_p __inb_p
# define inw_p __inw_p
# define inl_p __inl_p
# define outb_p __outb_p
# define outw_p __outw_p
# define outl_p __outl_p
# define insb __insb
# define insw __insw
# define insl __insl
# define outsb __outsb
# define outsw __outsw
# define outsl __outsl
# define __raw_readb __readb
# define __raw_readw __readw
# define __raw_readl __readl
# define __raw_writeb __writeb
# define __raw_writew __writew
# define __raw_writel __writel
/*
* The platform header files may define some of these macros to use
* the inlined versions where appropriate. These macros may also be
* redefined by userlevel programs.
*/
#ifdef __raw_readb
# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; })
#endif
#ifdef __raw_readw
# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; })
#endif
#ifdef __raw_readl
# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; })
#endif
#ifdef __raw_writeb
# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); })
#endif
#ifdef __raw_writew
# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); })
#endif
#ifdef __raw_writel
# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); })
#endif
#define readb_relaxed(a) readb(a)
#define readw_relaxed(a) readw(a)
#define readl_relaxed(a) readl(a)
#define mmiowb()
/*
* If the platform has PC-like I/O, this function converts the offset into
* an address.
*/
static __inline__ unsigned long isa_port2addr(unsigned long offset)
{
return __isa_port2addr(offset);
}
/*
* This function provides a method for the generic case where a board-specific
* isa_port2addr simply needs to return the port + some arbitrary port base.
*
* We use this at board setup time to implicitly set the port base, and
* as a result, we can use the generic isa_port2addr.
*/
static inline void __set_io_port_base(unsigned long pbase)
{
extern unsigned long generic_io_base;
generic_io_base = pbase;
}
#define isa_readb(a) readb(isa_port2addr(a))
#define isa_readw(a) readw(isa_port2addr(a))
#define isa_readl(a) readl(isa_port2addr(a))
#define isa_writeb(b,a) writeb(b,isa_port2addr(a))
#define isa_writew(w,a) writew(w,isa_port2addr(a))
#define isa_writel(l,a) writel(l,isa_port2addr(a))
#define isa_memset_io(a,b,c) \
memset((void *)(isa_port2addr((unsigned long)a)),(b),(c))
#define isa_memcpy_fromio(a,b,c) \
memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c))
#define isa_memcpy_toio(a,b,c) \
memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c))
/* We really want to try and get these to memcpy etc */
extern void memcpy_fromio(void *, unsigned long, unsigned long);
extern void memcpy_toio(unsigned long, const void *, unsigned long);
extern void memset_io(unsigned long, int, unsigned long);
/* SuperH on-chip I/O functions */
static __inline__ unsigned char ctrl_inb(unsigned long addr)
{
return *(volatile unsigned char*)addr;
}
static __inline__ unsigned short ctrl_inw(unsigned long addr)
{
return *(volatile unsigned short*)addr;
}
static __inline__ unsigned int ctrl_inl(unsigned long addr)
{
return *(volatile unsigned long*)addr;
}
static __inline__ void ctrl_outb(unsigned char b, unsigned long addr)
{
*(volatile unsigned char*)addr = b;
}
static __inline__ void ctrl_outw(unsigned short b, unsigned long addr)
{
*(volatile unsigned short*)addr = b;
}
static __inline__ void ctrl_outl(unsigned int b, unsigned long addr)
{
*(volatile unsigned long*)addr = b;
}
#define IO_SPACE_LIMIT 0xffffffff
/*
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/SuperH mapping
*/
static __inline__ unsigned long virt_to_phys(volatile void * address)
{
return PHYSADDR(address);
}
static __inline__ void * phys_to_virt(unsigned long address)
{
return (void *)P1SEGADDR(address);
}
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
#define page_to_bus page_to_phys
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the x86 architecture, we just read/write the
* memory location directly.
*
* On SH, we have the whole physical address space mapped at all times
* (as MIPS does), so "ioremap()" and "iounmap()" do not need to do
* anything. (This isn't true for all machines but we still handle
* these cases with wired TLB entries anyway ...)
*
* We cheat a bit and always return uncachable areas until we've fixed
* the drivers to handle caching properly.
*/
static __inline__ void * ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size);
}
static __inline__ void iounmap(void *addr)
{
return __iounmap(addr);
}
#define ioremap_nocache(off,size) ioremap(off,size)
static __inline__ int check_signature(unsigned long io_addr,
const unsigned char *signature, int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
/*
* The caches on some architectures aren't dma-coherent and have need to
* handle this in software. There are three types of operations that
* can be applied to dma buffers.
*
* - dma_cache_wback_inv(start, size) makes caches and RAM coherent by
* writing the content of the caches back to memory, if necessary.
* The function also invalidates the affected part of the caches as
* necessary before DMA transfers from outside to memory.
* - dma_cache_inv(start, size) invalidates the affected parts of the
* caches. Dirty lines of the caches may be written back or simply
* be discarded. This operation is necessary before dma operations
* to the memory.
* - dma_cache_wback(start, size) writes back any dirty lines but does
* not invalidate the cache. This can be used before DMA reads from
* memory,
*/
#define dma_cache_wback_inv(_start,_size) \
__flush_purge_region(_start,_size)
#define dma_cache_inv(_start,_size) \
__flush_invalidate_region(_start,_size)
#define dma_cache_wback(_start,_size) \
__flush_wback_region(_start,_size)
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */

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/*
* include/asm-sh/io_generic.h
*
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Generic IO functions
*/
#ifndef _ASM_SH_IO_GENERIC_H
#define _ASM_SH_IO_GENERIC_H
extern unsigned long generic_io_base;
extern unsigned char generic_inb(unsigned long port);
extern unsigned short generic_inw(unsigned long port);
extern unsigned int generic_inl(unsigned long port);
extern void generic_outb(unsigned char value, unsigned long port);
extern void generic_outw(unsigned short value, unsigned long port);
extern void generic_outl(unsigned int value, unsigned long port);
extern unsigned char generic_inb_p(unsigned long port);
extern unsigned short generic_inw_p(unsigned long port);
extern unsigned int generic_inl_p(unsigned long port);
extern void generic_outb_p(unsigned char value, unsigned long port);
extern void generic_outw_p(unsigned short value, unsigned long port);
extern void generic_outl_p(unsigned int value, unsigned long port);
extern void generic_insb(unsigned long port, void *addr, unsigned long count);
extern void generic_insw(unsigned long port, void *addr, unsigned long count);
extern void generic_insl(unsigned long port, void *addr, unsigned long count);
extern void generic_outsb(unsigned long port, const void *addr, unsigned long count);
extern void generic_outsw(unsigned long port, const void *addr, unsigned long count);
extern void generic_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned char generic_readb(unsigned long addr);
extern unsigned short generic_readw(unsigned long addr);
extern unsigned int generic_readl(unsigned long addr);
extern void generic_writeb(unsigned char b, unsigned long addr);
extern void generic_writew(unsigned short b, unsigned long addr);
extern void generic_writel(unsigned int b, unsigned long addr);
extern void *generic_ioremap(unsigned long offset, unsigned long size);
extern void generic_iounmap(void *addr);
extern unsigned long generic_isa_port2addr(unsigned long offset);
#endif /* _ASM_SH_IO_GENERIC_H */

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/* $Id: ioctl.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
*
* linux/ioctl.h for Linux by H.H. Bergman.
*/
#ifndef __ASM_SH_IOCTL_H
#define __ASM_SH_IOCTL_H
/* ioctl command encoding: 32 bits total, command in lower 16 bits,
* size of the parameter structure in the lower 14 bits of the
* upper 16 bits.
* Encoding the size of the parameter structure in the ioctl request
* is useful for catching programs compiled with old versions
* and to avoid overwriting user space outside the user buffer area.
* The highest 2 bits are reserved for indicating the ``access mode''.
* NOTE: This limits the max parameter size to 16kB -1 !
*/
/*
* The following is for compatibility across the various Linux
* platforms. The i386 ioctl numbering scheme doesn't really enforce
* a type field. De facto, however, the top 8 bits of the lower 16
* bits are indeed used as a type field, so we might just as well make
* this explicit here. Please be sure to use the decoding macros
* below from now on.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 14
#define _IOC_DIRBITS 2
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/*
* Direction bits.
*/
#define _IOC_NONE 0U
#define _IOC_WRITE 1U
#define _IOC_READ 2U
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* used to decode ioctl numbers.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* ...and for the drivers/sound files... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif /* __ASM_SH_IOCTL_H */

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#ifndef __ASM_SH_IOCTLS_H
#define __ASM_SH_IOCTLS_H
#include <asm/ioctl.h>
#define FIOCLEX _IO('f', 1)
#define FIONCLEX _IO('f', 2)
#define FIOASYNC _IOW('f', 125, int)
#define FIONBIO _IOW('f', 126, int)
#define FIONREAD _IOR('f', 127, int)
#define TIOCINQ FIONREAD
#define FIOQSIZE _IOR('f', 128, loff_t)
#define TCGETS 0x5401
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA _IOR('t', 23, struct termio)
#define TCSETA _IOW('t', 24, struct termio)
#define TCSETAW _IOW('t', 25, struct termio)
#define TCSETAF _IOW('t', 28, struct termio)
#define TCSBRK _IO('t', 29)
#define TCXONC _IO('t', 30)
#define TCFLSH _IO('t', 31)
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
#define TIOCSPGRP _IOW('t', 118, int)
#define TIOCGPGRP _IOR('t', 119, int)
#define TIOCEXCL _IO('T', 12) /* 0x540C */
#define TIOCNXCL _IO('T', 13) /* 0x540D */
#define TIOCSCTTY _IO('T', 14) /* 0x540E */
#define TIOCSTI _IOW('T', 18, char) /* 0x5412 */
#define TIOCMGET _IOR('T', 21, unsigned int) /* 0x5415 */
#define TIOCMBIS _IOW('T', 22, unsigned int) /* 0x5416 */
#define TIOCMBIC _IOW('T', 23, unsigned int) /* 0x5417 */
#define TIOCMSET _IOW('T', 24, unsigned int) /* 0x5418 */
# define TIOCM_LE 0x001
# define TIOCM_DTR 0x002
# define TIOCM_RTS 0x004
# define TIOCM_ST 0x008
# define TIOCM_SR 0x010
# define TIOCM_CTS 0x020
# define TIOCM_CAR 0x040
# define TIOCM_RNG 0x080
# define TIOCM_DSR 0x100
# define TIOCM_CD TIOCM_CAR
# define TIOCM_RI TIOCM_RNG
#define TIOCGSOFTCAR _IOR('T', 25, unsigned int) /* 0x5419 */
#define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */
#define TIOCLINUX _IOW('T', 28, char) /* 0x541C */
#define TIOCCONS _IO('T', 29) /* 0x541D */
#define TIOCGSERIAL _IOR('T', 30, struct serial_struct) /* 0x541E */
#define TIOCSSERIAL _IOW('T', 31, struct serial_struct) /* 0x541F */
#define TIOCPKT _IOW('T', 32, int) /* 0x5420 */
# define TIOCPKT_DATA 0
# define TIOCPKT_FLUSHREAD 1
# define TIOCPKT_FLUSHWRITE 2
# define TIOCPKT_STOP 4
# define TIOCPKT_START 8
# define TIOCPKT_NOSTOP 16
# define TIOCPKT_DOSTOP 32
#define TIOCNOTTY _IO('T', 34) /* 0x5422 */
#define TIOCSETD _IOW('T', 35, int) /* 0x5423 */
#define TIOCGETD _IOR('T', 36, int) /* 0x5424 */
#define TCSBRKP _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
#define TIOCSBRK _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
#define TIOCCBRK _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
#define TIOCGSID _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
#define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */
#define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */
#define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT _IOR('T', 88, struct async_struct) /* 0x5458 */ /* For debugging only */
#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* 0x545A */ /* Get multiport config */
#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* 0x545B */ /* Set multiport config */
#define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */
#define TIOCGICOUNT _IOR('T', 93, struct async_icount) /* 0x545D */ /* read serial port inline interrupt counts */
#endif /* __ASM_SH_IOCTLS_H */

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include/asm-sh/ipc.h Normal file
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#include <asm-generic/ipc.h>

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include/asm-sh/ipcbuf.h Normal file
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#ifndef __ASM_SH_IPCBUF_H__
#define __ASM_SH_IPCBUF_H__
/*
* The ipc64_perm structure for i386 architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 32-bit mode_t and seq
* - 2 miscellaneous 32-bit values
*/
struct ipc64_perm
{
__kernel_key_t key;
__kernel_uid32_t uid;
__kernel_gid32_t gid;
__kernel_uid32_t cuid;
__kernel_gid32_t cgid;
__kernel_mode_t mode;
unsigned short __pad1;
unsigned short seq;
unsigned short __pad2;
unsigned long __unused1;
unsigned long __unused2;
};
#endif /* __ASM_SH_IPCBUF_H__ */

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#ifndef __ASM_SH_IRQ_SH73180_H
#define __ASM_SH_IRQ_SH73180_H
/*
* linux/include/asm-sh/irq-sh73180.h
*
* Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
*/
#undef INTC_IPRA
#undef INTC_IPRB
#undef INTC_IPRC
#undef INTC_IPRD
#undef DMTE0_IRQ
#undef DMTE1_IRQ
#undef DMTE2_IRQ
#undef DMTE3_IRQ
#undef DMTE4_IRQ
#undef DMTE5_IRQ
#undef DMTE6_IRQ
#undef DMTE7_IRQ
#undef DMAE_IRQ
#undef DMA_IPR_ADDR
#undef DMA_IPR_POS
#undef DMA_PRIORITY
#undef NR_IRQS
#undef __irq_demux
#undef irq_demux
#undef INTC_IMCR0
#undef INTC_IMCR1
#undef INTC_IMCR2
#undef INTC_IMCR3
#undef INTC_IMCR4
#undef INTC_IMCR5
#undef INTC_IMCR6
#undef INTC_IMCR7
#undef INTC_IMCR8
#undef INTC_IMCR9
#undef INTC_IMCR10
#define INTC_IPRA 0xA4080000UL
#define INTC_IPRB 0xA4080004UL
#define INTC_IPRC 0xA4080008UL
#define INTC_IPRD 0xA408000CUL
#define INTC_IPRE 0xA4080010UL
#define INTC_IPRF 0xA4080014UL
#define INTC_IPRG 0xA4080018UL
#define INTC_IPRH 0xA408001CUL
#define INTC_IPRI 0xA4080020UL
#define INTC_IPRJ 0xA4080024UL
#define INTC_IPRK 0xA4080028UL
#define INTC_IMR0 0xA4080080UL
#define INTC_IMR1 0xA4080084UL
#define INTC_IMR2 0xA4080088UL
#define INTC_IMR3 0xA408008CUL
#define INTC_IMR4 0xA4080090UL
#define INTC_IMR5 0xA4080094UL
#define INTC_IMR6 0xA4080098UL
#define INTC_IMR7 0xA408009CUL
#define INTC_IMR8 0xA40800A0UL
#define INTC_IMR9 0xA40800A4UL
#define INTC_IMR10 0xA40800A8UL
#define INTC_IMR11 0xA40800ACUL
#define INTC_IMCR0 0xA40800C0UL
#define INTC_IMCR1 0xA40800C4UL
#define INTC_IMCR2 0xA40800C8UL
#define INTC_IMCR3 0xA40800CCUL
#define INTC_IMCR4 0xA40800D0UL
#define INTC_IMCR5 0xA40800D4UL
#define INTC_IMCR6 0xA40800D8UL
#define INTC_IMCR7 0xA40800DCUL
#define INTC_IMCR8 0xA40800E0UL
#define INTC_IMCR9 0xA40800E4UL
#define INTC_IMCR10 0xA40800E8UL
#define INTC_IMCR11 0xA40800ECUL
#define INTC_ICR0 0xA4140000UL
#define INTC_ICR1 0xA414001CUL
#define INTMSK0 0xa4140044
#define INTMSKCLR0 0xa4140064
#define INTC_INTPRI0 0xa4140010
/*
NOTE:
*_IRQ = (INTEVT2 - 0x200)/0x20
*/
/* TMU0 */
#define TMU0_IRQ 16
#define TMU0_IPR_ADDR INTC_IPRA
#define TMU0_IPR_POS 3
#define TMU0_PRIORITY 2
#define TIMER_IRQ 16
#define TIMER_IPR_ADDR INTC_IPRA
#define TIMER_IPR_POS 3
#define TIMER_PRIORITY 2
/* TMU1 */
#define TMU1_IRQ 17
#define TMU1_IPR_ADDR INTC_IPRA
#define TMU1_IPR_POS 2
#define TMU1_PRIORITY 2
/* TMU2 */
#define TMU2_IRQ 18
#define TMU2_IPR_ADDR INTC_IPRA
#define TMU2_IPR_POS 1
#define TMU2_PRIORITY 2
/* LCDC */
#define LCDC_IRQ 28
#define LCDC_IPR_ADDR INTC_IPRB
#define LCDC_IPR_POS 2
#define LCDC_PRIORITY 2
/* VIO (Video I/O) */
#define CEU_IRQ 52
#define BEU_IRQ 53
#define VEU_IRQ 54
#define VOU_IRQ 55
#define VIO_IPR_ADDR INTC_IPRE
#define VIO_IPR_POS 2
#define VIO_PRIORITY 2
/* MFI (Multi Functional Interface) */
#define MFI_IRQ 56
#define MFI_IPR_ADDR INTC_IPRE
#define MFI_IPR_POS 1
#define MFI_PRIORITY 2
/* VPU (Video Processing Unit) */
#define VPU_IRQ 60
#define VPU_IPR_ADDR INTC_IPRE
#define VPU_IPR_POS 0
#define VPU_PRIORITY 2
/* 3DG */
#define TDG_IRQ 63
#define TDG_IPR_ADDR INTC_IPRJ
#define TDG_IPR_POS 2
#define TDG_PRIORITY 2
/* DMAC(1) */
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMA1_IPR_ADDR INTC_IPRE
#define DMA1_IPR_POS 3
#define DMA1_PRIORITY 7
/* DMAC(2) */
#define DMTE4_IRQ 76
#define DMTE5_IRQ 77
#define DMA2_IPR_ADDR INTC_IPRF
#define DMA2_IPR_POS 2
#define DMA2_PRIORITY 7
/* SCIF0 */
#define SCIF_ERI_IRQ 80
#define SCIF_RXI_IRQ 81
#define SCIF_BRI_IRQ 82
#define SCIF_TXI_IRQ 83
#define SCIF_IPR_ADDR INTC_IPRG
#define SCIF_IPR_POS 3
#define SCIF_PRIORITY 3
/* SIOF0 */
#define SIOF0_IRQ 84
#define SIOF0_IPR_ADDR INTC_IPRH
#define SIOF0_IPR_POS 3
#define SIOF0_PRIORITY 3
/* FLCTL (Flash Memory Controller) */
#define FLSTE_IRQ 92
#define FLTEND_IRQ 93
#define FLTRQ0_IRQ 94
#define FLTRQ1_IRQ 95
#define FLCTL_IPR_ADDR INTC_IPRH
#define FLCTL_IPR_POS 1
#define FLCTL_PRIORITY 3
/* IIC(0) (IIC Bus Interface) */
#define IIC0_ALI_IRQ 96
#define IIC0_TACKI_IRQ 97
#define IIC0_WAITI_IRQ 98
#define IIC0_DTEI_IRQ 99
#define IIC0_IPR_ADDR INTC_IPRH
#define IIC0_IPR_POS 0
#define IIC0_PRIORITY 3
/* IIC(1) (IIC Bus Interface) */
#define IIC1_ALI_IRQ 44
#define IIC1_TACKI_IRQ 45
#define IIC1_WAITI_IRQ 46
#define IIC1_DTEI_IRQ 47
#define IIC1_IPR_ADDR INTC_IPRG
#define IIC1_IPR_POS 0
#define IIC1_PRIORITY 3
/* SIO0 */
#define SIO0_IRQ 88
#define SIO0_IPR_ADDR INTC_IPRI
#define SIO0_IPR_POS 3
#define SIO0_PRIORITY 3
/* SDHI */
#define SDHI_SDHII0_IRQ 100
#define SDHI_SDHII1_IRQ 101
#define SDHI_SDHII2_IRQ 102
#define SDHI_SDHII3_IRQ 103
#define SDHI_IPR_ADDR INTC_IPRK
#define SDHI_IPR_POS 0
#define SDHI_PRIORITY 3
/* SIU (Sound Interface Unit) */
#define SIU_IRQ 108
#define SIU_IPR_ADDR INTC_IPRJ
#define SIU_IPR_POS 1
#define SIU_PRIORITY 3
/* ONCHIP_NR_IRQS */
#define NR_IRQS 109
/* In a generic kernel, NR_IRQS is an upper bound, and we should use
* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
*/
#define ACTUAL_NR_IRQS NR_IRQS
extern void disable_irq(unsigned int);
extern void disable_irq_nosync(unsigned int);
extern void enable_irq(unsigned int);
/*
* Simple Mask Register Support
*/
extern void make_maskreg_irq(unsigned int irq);
extern unsigned short *irq_mask_register;
/*
* Function for "on chip support modules".
*/
extern void make_ipr_irq(unsigned int irq, unsigned int addr,
int pos, int priority);
extern void make_imask_irq(unsigned int irq);
#define PORT_PACR 0xA4050100UL
#define PORT_PBCR 0xA4050102UL
#define PORT_PCCR 0xA4050104UL
#define PORT_PDCR 0xA4050106UL
#define PORT_PECR 0xA4050108UL
#define PORT_PFCR 0xA405010AUL
#define PORT_PGCR 0xA405010CUL
#define PORT_PHCR 0xA405010EUL
#define PORT_PJCR 0xA4050110UL
#define PORT_PKCR 0xA4050112UL
#define PORT_PLCR 0xA4050114UL
#define PORT_SCPCR 0xA4050116UL
#define PORT_PMCR 0xA4050118UL
#define PORT_PNCR 0xA405011AUL
#define PORT_PQCR 0xA405011CUL
#define PORT_PRCR 0xA405011EUL
#define PORT_PTCR 0xA405014CUL
#define PORT_PUCR 0xA405014EUL
#define PORT_PVCR 0xA4050150UL
#define PORT_PSELA 0xA4050140UL
#define PORT_PSELB 0xA4050142UL
#define PORT_PSELC 0xA4050144UL
#define PORT_PSELE 0xA4050158UL
#define PORT_HIZCRA 0xA4050146UL
#define PORT_HIZCRB 0xA4050148UL
#define PORT_DRVCR 0xA405014AUL
#define PORT_PADR 0xA4050120UL
#define PORT_PBDR 0xA4050122UL
#define PORT_PCDR 0xA4050124UL
#define PORT_PDDR 0xA4050126UL
#define PORT_PEDR 0xA4050128UL
#define PORT_PFDR 0xA405012AUL
#define PORT_PGDR 0xA405012CUL
#define PORT_PHDR 0xA405012EUL
#define PORT_PJDR 0xA4050130UL
#define PORT_PKDR 0xA4050132UL
#define PORT_PLDR 0xA4050134UL
#define PORT_SCPDR 0xA4050136UL
#define PORT_PMDR 0xA4050138UL
#define PORT_PNDR 0xA405013AUL
#define PORT_PQDR 0xA405013CUL
#define PORT_PRDR 0xA405013EUL
#define PORT_PTDR 0xA405016CUL
#define PORT_PUDR 0xA405016EUL
#define PORT_PVDR 0xA4050170UL
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ2_IRQ 34
#define IRQ3_IRQ 35
#define IRQ4_IRQ 36
#define IRQ5_IRQ 37
#define IRQ6_IRQ 38
#define IRQ7_IRQ 39
#define INTPRI00 0xA4140010UL
#define IRQ0_IPR_ADDR INTPRI00
#define IRQ1_IPR_ADDR INTPRI00
#define IRQ2_IPR_ADDR INTPRI00
#define IRQ3_IPR_ADDR INTPRI00
#define IRQ4_IPR_ADDR INTPRI00
#define IRQ5_IPR_ADDR INTPRI00
#define IRQ6_IPR_ADDR INTPRI00
#define IRQ7_IPR_ADDR INTPRI00
#define IRQ0_IPR_POS 7
#define IRQ1_IPR_POS 6
#define IRQ2_IPR_POS 5
#define IRQ3_IPR_POS 4
#define IRQ4_IPR_POS 3
#define IRQ5_IPR_POS 2
#define IRQ6_IPR_POS 1
#define IRQ7_IPR_POS 0
#define IRQ0_PRIORITY 1
#define IRQ1_PRIORITY 1
#define IRQ2_PRIORITY 1
#define IRQ3_PRIORITY 1
#define IRQ4_PRIORITY 1
#define IRQ5_PRIORITY 1
#define IRQ6_PRIORITY 1
#define IRQ7_PRIORITY 1
extern int shmse_irq_demux(int irq);
#define __irq_demux(irq) shmse_irq_demux(irq)
#define irq_demux(irq) __irq_demux(irq)
#endif /* __ASM_SH_IRQ_SH73180_H */

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include/asm-sh/irq.h Normal file
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#ifndef __ASM_SH_IRQ_H
#define __ASM_SH_IRQ_H
/*
*
* linux/include/asm-sh/irq.h
*
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2003 Paul Mundt
*
*/
#include <linux/config.h>
#include <asm/machvec.h>
#include <asm/ptrace.h> /* for pt_regs */
#if defined(CONFIG_SH_HP600) || \
defined(CONFIG_SH_RTS7751R2D) || \
defined(CONFIG_SH_HS7751RVOIP) || \
defined(CONFIG_SH_SH03)
#include <asm/mach/ide.h>
#endif
#if defined(CONFIG_CPU_SH3)
#define INTC_IPRA 0xfffffee2UL
#define INTC_IPRB 0xfffffee4UL
#elif defined(CONFIG_CPU_SH4)
#define INTC_IPRA 0xffd00004UL
#define INTC_IPRB 0xffd00008UL
#define INTC_IPRC 0xffd0000cUL
#define INTC_IPRD 0xffd00010UL
#endif
#ifdef CONFIG_IDE
# ifndef IRQ_CFCARD
# define IRQ_CFCARD 14
# endif
# ifndef IRQ_PCMCIA
# define IRQ_PCMCIA 15
# endif
#endif
#define TIMER_IRQ 16
#define TIMER_IPR_ADDR INTC_IPRA
#define TIMER_IPR_POS 3
#define TIMER_PRIORITY 2
#define TIMER1_IRQ 17
#define TIMER1_IPR_ADDR INTC_IPRA
#define TIMER1_IPR_POS 2
#define TIMER1_PRIORITY 4
#define RTC_IRQ 22
#define RTC_IPR_ADDR INTC_IPRA
#define RTC_IPR_POS 0
#define RTC_PRIORITY TIMER_PRIORITY
#if defined(CONFIG_CPU_SH3)
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMA_IPR_ADDR INTC_IPRE
#define DMA_IPR_POS 3
#define DMA_PRIORITY 7
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
/* TMU2 */
#define TIMER2_IRQ 18
#define TIMER2_IPR_ADDR INTC_IPRA
#define TIMER2_IPR_POS 1
#define TIMER2_PRIORITY 2
/* WDT */
#define WDT_IRQ 27
#define WDT_IPR_ADDR INTC_IPRB
#define WDT_IPR_POS 3
#define WDT_PRIORITY 2
/* SIM (SIM Card Module) */
#define SIM_ERI_IRQ 23
#define SIM_RXI_IRQ 24
#define SIM_TXI_IRQ 25
#define SIM_TEND_IRQ 26
#define SIM_IPR_ADDR INTC_IPRB
#define SIM_IPR_POS 1
#define SIM_PRIORITY 2
/* VIO (Video I/O) */
#define VIO_IRQ 52
#define VIO_IPR_ADDR INTC_IPRE
#define VIO_IPR_POS 2
#define VIO_PRIORITY 2
/* MFI (Multi Functional Interface) */
#define MFI_IRQ 56
#define MFI_IPR_ADDR INTC_IPRE
#define MFI_IPR_POS 1
#define MFI_PRIORITY 2
/* VPU (Video Processing Unit) */
#define VPU_IRQ 60
#define VPU_IPR_ADDR INTC_IPRE
#define VPU_IPR_POS 0
#define VPU_PRIORITY 2
/* KEY (Key Scan Interface) */
#define KEY_IRQ 79
#define KEY_IPR_ADDR INTC_IPRF
#define KEY_IPR_POS 3
#define KEY_PRIORITY 2
/* CMT (Compare Match Timer) */
#define CMT_IRQ 104
#define CMT_IPR_ADDR INTC_IPRF
#define CMT_IPR_POS 0
#define CMT_PRIORITY 2
/* DMAC(1) */
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMA1_IPR_ADDR INTC_IPRE
#define DMA1_IPR_POS 3
#define DMA1_PRIORITY 7
/* DMAC(2) */
#define DMTE4_IRQ 76
#define DMTE5_IRQ 77
#define DMA2_IPR_ADDR INTC_IPRF
#define DMA2_IPR_POS 2
#define DMA2_PRIORITY 7
/* SIOF0 */
#define SIOF0_IRQ 84
#define SIOF0_IPR_ADDR INTC_IPRH
#define SIOF0_IPR_POS 3
#define SIOF0_PRIORITY 3
/* FLCTL (Flash Memory Controller) */
#define FLSTE_IRQ 92
#define FLTEND_IRQ 93
#define FLTRQ0_IRQ 94
#define FLTRQ1_IRQ 95
#define FLCTL_IPR_ADDR INTC_IPRH
#define FLCTL_IPR_POS 1
#define FLCTL_PRIORITY 3
/* IIC (IIC Bus Interface) */
#define IIC_ALI_IRQ 96
#define IIC_TACKI_IRQ 97
#define IIC_WAITI_IRQ 98
#define IIC_DTEI_IRQ 99
#define IIC_IPR_ADDR INTC_IPRH
#define IIC_IPR_POS 0
#define IIC_PRIORITY 3
/* SIO0 */
#define SIO0_IRQ 88
#define SIO0_IPR_ADDR INTC_IPRI
#define SIO0_IPR_POS 3
#define SIO0_PRIORITY 3
/* SIU (Sound Interface Unit) */
#define SIU_IRQ 108
#define SIU_IPR_ADDR INTC_IPRJ
#define SIU_IPR_POS 1
#define SIU_PRIORITY 3
#endif
#elif defined(CONFIG_CPU_SH4)
#define DMTE0_IRQ 34
#define DMTE1_IRQ 35
#define DMTE2_IRQ 36
#define DMTE3_IRQ 37
#define DMTE4_IRQ 44 /* 7751R only */
#define DMTE5_IRQ 45 /* 7751R only */
#define DMTE6_IRQ 46 /* 7751R only */
#define DMTE7_IRQ 47 /* 7751R only */
#define DMAE_IRQ 38
#define DMA_IPR_ADDR INTC_IPRC
#define DMA_IPR_POS 2
#define DMA_PRIORITY 7
#endif
#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
defined (CONFIG_CPU_SUBTYPE_SH7751)
#define SCI_ERI_IRQ 23
#define SCI_RXI_IRQ 24
#define SCI_TXI_IRQ 25
#define SCI_IPR_ADDR INTC_IPRB
#define SCI_IPR_POS 1
#define SCI_PRIORITY 3
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#define SCIF0_IRQ 80
#define SCIF0_IPR_ADDR INTC_IPRG
#define SCIF0_IPR_POS 3
#define SCIF0_PRIORITY 3
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
#define SCIF_ERI_IRQ 56
#define SCIF_RXI_IRQ 57
#define SCIF_BRI_IRQ 58
#define SCIF_TXI_IRQ 59
#define SCIF_IPR_ADDR INTC_IPRE
#define SCIF_IPR_POS 1
#define SCIF_PRIORITY 3
#define IRDA_ERI_IRQ 52
#define IRDA_RXI_IRQ 53
#define IRDA_BRI_IRQ 54
#define IRDA_TXI_IRQ 55
#define IRDA_IPR_ADDR INTC_IPRE
#define IRDA_IPR_POS 2
#define IRDA_PRIORITY 3
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
#define SCIF_ERI_IRQ 40
#define SCIF_RXI_IRQ 41
#define SCIF_BRI_IRQ 42
#define SCIF_TXI_IRQ 43
#define SCIF_IPR_ADDR INTC_IPRC
#define SCIF_IPR_POS 1
#define SCIF_PRIORITY 3
#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
#define SCIF1_ERI_IRQ 23
#define SCIF1_RXI_IRQ 24
#define SCIF1_BRI_IRQ 25
#define SCIF1_TXI_IRQ 26
#define SCIF1_IPR_ADDR INTC_IPRB
#define SCIF1_IPR_POS 1
#define SCIF1_PRIORITY 3
#endif
#endif
/* NR_IRQS is made from three components:
* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
* 2. PINT_NR_IRQS - number of PINT interrupts
* 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
*/
/* 1. ONCHIP_NR_IRQS */
#ifdef CONFIG_SH_GENERIC
# define ONCHIP_NR_IRQS 144
#else
# if defined(CONFIG_CPU_SUBTYPE_SH7604)
# define ONCHIP_NR_IRQS 24 // Actually 21
# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
# define ONCHIP_NR_IRQS 64
# define PINT_NR_IRQS 16
# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
# define ONCHIP_NR_IRQS 32
# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7705)
# define ONCHIP_NR_IRQS 64 // Actually 61
# define PINT_NR_IRQS 16
# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
# define ONCHIP_NR_IRQS 48 // Actually 44
# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
# define ONCHIP_NR_IRQS 72
# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
# define ONCHIP_NR_IRQS 110
# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
# define ONCHIP_NR_IRQS 72
# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
# define ONCHIP_NR_IRQS 144
# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
# define ONCHIP_NR_IRQS 109
# endif
#endif
/* 2. PINT_NR_IRQS */
#ifdef CONFIG_SH_GENERIC
# define PINT_NR_IRQS 16
#else
# ifndef PINT_NR_IRQS
# define PINT_NR_IRQS 0
# endif
#endif
#if PINT_NR_IRQS > 0
# define PINT_IRQ_BASE ONCHIP_NR_IRQS
#endif
/* 3. OFFCHIP_NR_IRQS */
#ifdef CONFIG_SH_GENERIC
# define OFFCHIP_NR_IRQS 16
#else
# if defined(CONFIG_HD64461)
# define OFFCHIP_NR_IRQS 18
# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
# define OFFCHIP_NR_IRQS 48
# elif defined(CONFIG_HD64465)
# define OFFCHIP_NR_IRQS 16
# elif defined (CONFIG_SH_EC3104)
# define OFFCHIP_NR_IRQS 16
# elif defined (CONFIG_SH_DREAMCAST)
# define OFFCHIP_NR_IRQS 96
# else
# define OFFCHIP_NR_IRQS 0
# endif
#endif
#if OFFCHIP_NR_IRQS > 0
# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
#endif
/* NR_IRQS. 1+2+3 */
#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
/* In a generic kernel, NR_IRQS is an upper bound, and we should use
* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
*/
#ifdef CONFIG_SH_GENERIC
# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
#else
# define ACTUAL_NR_IRQS NR_IRQS
#endif
extern void disable_irq(unsigned int);
extern void disable_irq_nosync(unsigned int);
extern void enable_irq(unsigned int);
/*
* Simple Mask Register Support
*/
extern void make_maskreg_irq(unsigned int irq);
extern unsigned short *irq_mask_register;
/*
* Function for "on chip support modules".
*/
extern void make_ipr_irq(unsigned int irq, unsigned int addr,
int pos, int priority);
extern void make_imask_irq(unsigned int irq);
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#undef INTC_IPRA
#undef INTC_IPRB
#define INTC_IPRA 0xA414FEE2UL
#define INTC_IPRB 0xA414FEE4UL
#define INTC_IPRC 0xA4140016UL
#define INTC_IPRD 0xA4140018UL
#define INTC_IPRE 0xA414001AUL
#define INTC_IPRF 0xA4080000UL
#define INTC_IPRG 0xA4080002UL
#define INTC_IPRH 0xA4080004UL
#define INTC_IPRI 0xA4080006UL
#define INTC_IPRJ 0xA4080008UL
#define INTC_IMR0 0xA4080040UL
#define INTC_IMR1 0xA4080042UL
#define INTC_IMR2 0xA4080044UL
#define INTC_IMR3 0xA4080046UL
#define INTC_IMR4 0xA4080048UL
#define INTC_IMR5 0xA408004AUL
#define INTC_IMR6 0xA408004CUL
#define INTC_IMR7 0xA408004EUL
#define INTC_IMR8 0xA4080050UL
#define INTC_IMR9 0xA4080052UL
#define INTC_IMR10 0xA4080054UL
#define INTC_IMCR0 0xA4080060UL
#define INTC_IMCR1 0xA4080062UL
#define INTC_IMCR2 0xA4080064UL
#define INTC_IMCR3 0xA4080066UL
#define INTC_IMCR4 0xA4080068UL
#define INTC_IMCR5 0xA408006AUL
#define INTC_IMCR6 0xA408006CUL
#define INTC_IMCR7 0xA408006EUL
#define INTC_IMCR8 0xA4080070UL
#define INTC_IMCR9 0xA4080072UL
#define INTC_IMCR10 0xA4080074UL
#define INTC_ICR0 0xA414FEE0UL
#define INTC_ICR1 0xA4140010UL
#define INTC_IRR0 0xA4140004UL
#define PORT_PACR 0xA4050100UL
#define PORT_PBCR 0xA4050102UL
#define PORT_PCCR 0xA4050104UL
#define PORT_PDCR 0xA4050106UL
#define PORT_PECR 0xA4050108UL
#define PORT_PFCR 0xA405010AUL
#define PORT_PGCR 0xA405010CUL
#define PORT_PHCR 0xA405010EUL
#define PORT_PJCR 0xA4050110UL
#define PORT_PKCR 0xA4050112UL
#define PORT_PLCR 0xA4050114UL
#define PORT_SCPCR 0xA4050116UL
#define PORT_PMCR 0xA4050118UL
#define PORT_PNCR 0xA405011AUL
#define PORT_PQCR 0xA405011CUL
#define PORT_PSELA 0xA4050140UL
#define PORT_PSELB 0xA4050142UL
#define PORT_PSELC 0xA4050144UL
#define PORT_HIZCRA 0xA4050146UL
#define PORT_HIZCRB 0xA4050148UL
#define PORT_DRVCR 0xA4050150UL
#define PORT_PADR 0xA4050120UL
#define PORT_PBDR 0xA4050122UL
#define PORT_PCDR 0xA4050124UL
#define PORT_PDDR 0xA4050126UL
#define PORT_PEDR 0xA4050128UL
#define PORT_PFDR 0xA405012AUL
#define PORT_PGDR 0xA405012CUL
#define PORT_PHDR 0xA405012EUL
#define PORT_PJDR 0xA4050130UL
#define PORT_PKDR 0xA4050132UL
#define PORT_PLDR 0xA4050134UL
#define PORT_SCPDR 0xA4050136UL
#define PORT_PMDR 0xA4050138UL
#define PORT_PNDR 0xA405013AUL
#define PORT_PQDR 0xA405013CUL
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ2_IRQ 34
#define IRQ3_IRQ 35
#define IRQ4_IRQ 36
#define IRQ5_IRQ 37
#define IRQ0_IPR_ADDR INTC_IPRC
#define IRQ1_IPR_ADDR INTC_IPRC
#define IRQ2_IPR_ADDR INTC_IPRC
#define IRQ3_IPR_ADDR INTC_IPRC
#define IRQ4_IPR_ADDR INTC_IPRD
#define IRQ5_IPR_ADDR INTC_IPRD
#define IRQ0_IPR_POS 0
#define IRQ1_IPR_POS 1
#define IRQ2_IPR_POS 2
#define IRQ3_IPR_POS 3
#define IRQ4_IPR_POS 0
#define IRQ5_IPR_POS 1
#define IRQ0_PRIORITY 1
#define IRQ1_PRIORITY 1
#define IRQ2_PRIORITY 1
#define IRQ3_PRIORITY 1
#define IRQ4_PRIORITY 1
#define IRQ5_PRIORITY 1
extern int ipr_irq_demux(int irq);
#define __irq_demux(irq) ipr_irq_demux(irq)
#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
#define INTC_IPRA 0xfffffee2UL
#define INTC_IPRB 0xfffffe60UL
#define INTC_VCRA 0xfffffe62UL
#define INTC_VCRB 0xfffffe64UL
#define INTC_VCRC 0xfffffe66UL
#define INTC_VCRD 0xfffffe68UL
#define INTC_VCRWDT 0xfffffee4UL
#define INTC_VCRDIV 0xffffff0cUL
#define INTC_VCRDMA0 0xffffffa0UL
#define INTC_VCRDMA1 0xffffffa8UL
#define INTC_ICR 0xfffffee0UL
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
#define INTC_IRR0 0xa4000004UL
#define INTC_IRR1 0xa4000006UL
#define INTC_IRR2 0xa4000008UL
#define INTC_ICR0 0xfffffee0UL
#define INTC_ICR1 0xa4000010UL
#define INTC_ICR2 0xa4000012UL
#define INTC_INTER 0xa4000014UL
#define INTC_IPRC 0xa4000016UL
#define INTC_IPRD 0xa4000018UL
#define INTC_IPRE 0xa400001aUL
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
#define INTC_IPRF 0xa400001cUL
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
#define INTC_IPRF 0xa4080000UL
#define INTC_IPRG 0xa4080002UL
#define INTC_IPRH 0xa4080004UL
#endif
#define PORT_PACR 0xa4000100UL
#define PORT_PBCR 0xa4000102UL
#define PORT_PCCR 0xa4000104UL
#define PORT_PFCR 0xa400010aUL
#define PORT_PADR 0xa4000120UL
#define PORT_PBDR 0xa4000122UL
#define PORT_PCDR 0xa4000124UL
#define PORT_PFDR 0xa400012aUL
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ2_IRQ 34
#define IRQ3_IRQ 35
#define IRQ4_IRQ 36
#define IRQ5_IRQ 37
#define IRQ0_IPR_ADDR INTC_IPRC
#define IRQ1_IPR_ADDR INTC_IPRC
#define IRQ2_IPR_ADDR INTC_IPRC
#define IRQ3_IPR_ADDR INTC_IPRC
#define IRQ4_IPR_ADDR INTC_IPRD
#define IRQ5_IPR_ADDR INTC_IPRD
#define IRQ0_IPR_POS 0
#define IRQ1_IPR_POS 1
#define IRQ2_IPR_POS 2
#define IRQ3_IPR_POS 3
#define IRQ4_IPR_POS 0
#define IRQ5_IPR_POS 1
#define IRQ0_PRIORITY 1
#define IRQ1_PRIORITY 1
#define IRQ2_PRIORITY 1
#define IRQ3_PRIORITY 1
#define IRQ4_PRIORITY 1
#define IRQ5_PRIORITY 1
#define PINT0_IRQ 40
#define PINT8_IRQ 41
#define PINT0_IPR_ADDR INTC_IPRD
#define PINT8_IPR_ADDR INTC_IPRD
#define PINT0_IPR_POS 3
#define PINT8_IPR_POS 2
#define PINT0_PRIORITY 2
#define PINT8_PRIORITY 2
extern int ipr_irq_demux(int irq);
#define __irq_demux(irq) ipr_irq_demux(irq)
#else
#define __irq_demux(irq) irq
#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
#define INTC_ICR 0xffd00000
#define INTC_ICR_NMIL (1<<15)
#define INTC_ICR_MAI (1<<14)
#define INTC_ICR_NMIB (1<<9)
#define INTC_ICR_NMIE (1<<8)
#define INTC_ICR_IRLM (1<<7)
#endif
#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
#define INTC2_FIRST_IRQ 64
#define NR_INTC2_IRQS 25
#define INTC2_BASE 0xfe080000
#define INTC2_INTC2MODE (INTC2_BASE+0x80)
#define INTC2_INTPRI_OFFSET 0x00
#define INTC2_INTREQ_OFFSET 0x20
#define INTC2_INTMSK_OFFSET 0x40
#define INTC2_INTMSKCLR_OFFSET 0x60
void make_intc2_irq(unsigned int irq,
unsigned int ipr_offset, unsigned int ipr_shift,
unsigned int msk_offset, unsigned int msk_shift,
unsigned int priority);
void init_IRQ_intc2(void);
void intc2_add_clear_irq(int irq, int (*fn)(int));
#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
static inline int generic_irq_demux(int irq)
{
return irq;
}
#define irq_canonicalize(irq) (irq)
#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
#if defined(CONFIG_CPU_SUBTYPE_SH73180)
#include <asm/irq-sh73180.h>
#endif
#endif /* __ASM_SH_IRQ_H */

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