Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
217
include/asm-mips/hazards.h
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217
include/asm-mips/hazards.h
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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*/
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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#include <linux/config.h>
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#ifdef __ASSEMBLY__
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.macro _ssnop
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sll $0, $0, 1
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.endm
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.macro _ehb
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sll $0, $0, 3
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.endm
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/*
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* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
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* use of the JTLB for instructions should not occur for 4 cpu cycles and use
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* for data translations should not occur for 3 cpu cycles.
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*/
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#ifdef CONFIG_CPU_RM9000
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.macro mtc0_tlbw_hazard
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.set push
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.set mips32
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_ssnop; _ssnop; _ssnop; _ssnop
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.set pop
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.endm
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.macro tlbw_eret_hazard
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.set push
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.set mips32
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_ssnop; _ssnop; _ssnop; _ssnop
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.set pop
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.endm
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#else
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/*
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* The taken branch will result in a two cycle penalty for the two killed
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* instructions on R4000 / R4400. Other processors only have a single cycle
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* hazard so this is nice trick to have an optimal code for a range of
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* processors.
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*/
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.macro mtc0_tlbw_hazard
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b . + 8
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.endm
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.macro tlbw_eret_hazard
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.endm
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#endif
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/*
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* mtc0->mfc0 hazard
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* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
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* It is a MIPS32R2 processor so ehb will clear the hazard.
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*/
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#ifdef CONFIG_CPU_MIPSR2
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/*
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* Use a macro for ehb unless explicit support for MIPSR2 is enabled
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*/
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#define irq_enable_hazard
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_ehb
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#define irq_disable_hazard
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_ehb
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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#define irq_enable_hazard
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#define irq_disable_hazard
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#else
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/*
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* Classic MIPS needs 1 - 3 nops or ssnops
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*/
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#define irq_enable_hazard
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#define irq_disable_hazard \
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_ssnop; _ssnop; _ssnop
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#endif
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#else /* __ASSEMBLY__ */
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__asm__(
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" .macro _ssnop \n\t"
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" sll $0, $2, 1 \n\t"
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" .endm \n\t"
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" \n\t"
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" .macro _ehb \n\t"
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" sll $0, $0, 3 \n\t"
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" .endm \n\t");
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#ifdef CONFIG_CPU_RM9000
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/*
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* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
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* use of the JTLB for instructions should not occur for 4 cpu cycles and use
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* for data translations should not occur for 3 cpu cycles.
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*/
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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".set\tmips0")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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".set\tmips0")
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#else
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/*
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* Overkill warning ...
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*/
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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".set reorder\n\t")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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".set reorder\n\t")
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#endif
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/*
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* mtc0->mfc0 hazard
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* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
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* It is a MIPS32R2 processor so ehb will clear the hazard.
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*/
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#ifdef CONFIG_CPU_MIPSR2
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/*
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* Use a macro for ehb unless explicit support for MIPSR2 is enabled
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*/
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__asm__(
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" .macro\tirq_enable_hazard \n\t"
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" _ehb \n\t"
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" .endm \n\t"
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" \n\t"
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" .macro\tirq_disable_hazard \n\t"
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" _ehb \n\t"
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" .endm");
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#define irq_enable_hazard() \
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__asm__ __volatile__( \
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"_ehb\t\t\t\t# irq_enable_hazard")
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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"_ehb\t\t\t\t# irq_disable_hazard")
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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__asm__(
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" .macro\tirq_enable_hazard \n\t"
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" .endm \n\t"
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" \n\t"
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" .macro\tirq_disable_hazard \n\t"
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" .endm");
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#define irq_enable_hazard() do { } while (0)
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#define irq_disable_hazard() do { } while (0)
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#else
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/*
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* Default for classic MIPS processors. Assume worst case hazards but don't
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* care about the irq_enable_hazard - sooner or later the hardware will
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* enable it and we don't care when exactly.
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*/
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__asm__(
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" # \n\t"
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" # There is a hazard but we do not care \n\t"
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" # \n\t"
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" .macro\tirq_enable_hazard \n\t"
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" .endm \n\t"
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" \n\t"
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" .macro\tirq_disable_hazard \n\t"
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" _ssnop; _ssnop; _ssnop \n\t"
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" .endm");
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#define irq_enable_hazard() do { } while (0)
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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"_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_HAZARDS_H */
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