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Linux-2.6.12-rc2

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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
commit 1da177e4c3
17291 changed files with 6718755 additions and 0 deletions
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12
drivers/net/ibm_emac/Makefile Normal file
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#
# Makefile for the IBM PPC4xx EMAC controllers
#
obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o
# Only need this if you want to see additional debug messages
ifeq ($(CONFIG_IBM_EMAC_ERRMSG), y)
ibm_emac-objs += ibm_emac_debug.o
endif

267
drivers/net/ibm_emac/ibm_emac.h Normal file
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/*
* ibm_emac.h
*
*
* Armin Kuster akuster@mvista.com
* June, 2002
*
* Copyright 2002 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IBM_EMAC_H_
#define _IBM_EMAC_H_
/* General defines needed for the driver */
/* Emac */
typedef struct emac_regs {
u32 em0mr0;
u32 em0mr1;
u32 em0tmr0;
u32 em0tmr1;
u32 em0rmr;
u32 em0isr;
u32 em0iser;
u32 em0iahr;
u32 em0ialr;
u32 em0vtpid;
u32 em0vtci;
u32 em0ptr;
u32 em0iaht1;
u32 em0iaht2;
u32 em0iaht3;
u32 em0iaht4;
u32 em0gaht1;
u32 em0gaht2;
u32 em0gaht3;
u32 em0gaht4;
u32 em0lsah;
u32 em0lsal;
u32 em0ipgvr;
u32 em0stacr;
u32 em0trtr;
u32 em0rwmr;
} emac_t;
/* MODE REG 0 */
#define EMAC_M0_RXI 0x80000000
#define EMAC_M0_TXI 0x40000000
#define EMAC_M0_SRST 0x20000000
#define EMAC_M0_TXE 0x10000000
#define EMAC_M0_RXE 0x08000000
#define EMAC_M0_WKE 0x04000000
/* MODE Reg 1 */
#define EMAC_M1_FDE 0x80000000
#define EMAC_M1_ILE 0x40000000
#define EMAC_M1_VLE 0x20000000
#define EMAC_M1_EIFC 0x10000000
#define EMAC_M1_APP 0x08000000
#define EMAC_M1_AEMI 0x02000000
#define EMAC_M1_IST 0x01000000
#define EMAC_M1_MF_1000GPCS 0x00c00000 /* Internal GPCS */
#define EMAC_M1_MF_1000MBPS 0x00800000 /* External GPCS */
#define EMAC_M1_MF_100MBPS 0x00400000
#define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */
#define EMAC_M1_TR 0x00008000
#ifdef CONFIG_IBM_EMAC4
#define EMAC_M1_RFS_8K 0x00200000
#define EMAC_M1_RFS_4K 0x00180000
#define EMAC_M1_RFS_2K 0x00100000
#define EMAC_M1_RFS_1K 0x00080000
#define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */
#define EMAC_M1_TX_FIFO_8K 0x00040000
#define EMAC_M1_TX_FIFO_4K 0x00030000
#define EMAC_M1_TX_FIFO_2K 0x00020000
#define EMAC_M1_TX_FIFO_1K 0x00010000
#define EMAC_M1_TX_TR 0x00008000
#define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */
#define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */
#define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */
#define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */
#define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */
#define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */
#else /* CONFIG_IBM_EMAC4 */
#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
#define EMAC_M1_RFS_2K 0x00200000
#define EMAC_M1_RFS_1K 0x00100000
#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
#define EMAC_M1_TX_FIFO_1K 0x00040000
#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
#define EMAC_M1_TR1_DEPEND 0x00004000
#define EMAC_M1_TR1_MULTI 0x00002000
#define EMAC_M1_JUMBO_ENABLE 0x00001000
#endif /* CONFIG_IBM_EMAC4 */
#define EMAC_M1_BASE (EMAC_M1_TX_FIFO_2K | \
EMAC_M1_APP | \
EMAC_M1_TR | EMAC_M1_VLE)
/* Transmit Mode Register 0 */
#define EMAC_TMR0_GNP0 0x80000000
#define EMAC_TMR0_GNP1 0x40000000
#define EMAC_TMR0_GNPD 0x20000000
#define EMAC_TMR0_FC 0x10000000
#define EMAC_TMR0_TFAE_2_32 0x00000001
#define EMAC_TMR0_TFAE_4_64 0x00000002
#define EMAC_TMR0_TFAE_8_128 0x00000003
#define EMAC_TMR0_TFAE_16_256 0x00000004
#define EMAC_TMR0_TFAE_32_512 0x00000005
#define EMAC_TMR0_TFAE_64_1024 0x00000006
#define EMAC_TMR0_TFAE_128_2048 0x00000007
/* Receive Mode Register */
#define EMAC_RMR_SP 0x80000000
#define EMAC_RMR_SFCS 0x40000000
#define EMAC_RMR_ARRP 0x20000000
#define EMAC_RMR_ARP 0x10000000
#define EMAC_RMR_AROP 0x08000000
#define EMAC_RMR_ARPI 0x04000000
#define EMAC_RMR_PPP 0x02000000
#define EMAC_RMR_PME 0x01000000
#define EMAC_RMR_PMME 0x00800000
#define EMAC_RMR_IAE 0x00400000
#define EMAC_RMR_MIAE 0x00200000
#define EMAC_RMR_BAE 0x00100000
#define EMAC_RMR_MAE 0x00080000
#define EMAC_RMR_RFAF_2_32 0x00000001
#define EMAC_RMR_RFAF_4_64 0x00000002
#define EMAC_RMR_RFAF_8_128 0x00000003
#define EMAC_RMR_RFAF_16_256 0x00000004
#define EMAC_RMR_RFAF_32_512 0x00000005
#define EMAC_RMR_RFAF_64_1024 0x00000006
#define EMAC_RMR_RFAF_128_2048 0x00000007
#define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE)
/* Interrupt Status & enable Regs */
#define EMAC_ISR_OVR 0x02000000
#define EMAC_ISR_PP 0x01000000
#define EMAC_ISR_BP 0x00800000
#define EMAC_ISR_RP 0x00400000
#define EMAC_ISR_SE 0x00200000
#define EMAC_ISR_ALE 0x00100000
#define EMAC_ISR_BFCS 0x00080000
#define EMAC_ISR_PTLE 0x00040000
#define EMAC_ISR_ORE 0x00020000
#define EMAC_ISR_IRE 0x00010000
#define EMAC_ISR_DBDM 0x00000200
#define EMAC_ISR_DB0 0x00000100
#define EMAC_ISR_SE0 0x00000080
#define EMAC_ISR_TE0 0x00000040
#define EMAC_ISR_DB1 0x00000020
#define EMAC_ISR_SE1 0x00000010
#define EMAC_ISR_TE1 0x00000008
#define EMAC_ISR_MOS 0x00000002
#define EMAC_ISR_MOF 0x00000001
/* STA CONTROL REG */
#define EMAC_STACR_OC 0x00008000
#define EMAC_STACR_PHYE 0x00004000
#define EMAC_STACR_WRITE 0x00002000
#define EMAC_STACR_READ 0x00001000
#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
#define EMAC_STACR_CLK_66MHZ 0x00000400
#define EMAC_STACR_CLK_100MHZ 0x00000C00
/* Transmit Request Threshold Register */
#define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */
#define EMAC_TRTR_1024 0x0f000000
#define EMAC_TRTR_512 0x07000000
#define EMAC_TRTR_256 0x03000000
#define EMAC_TRTR_192 0x10000000
#define EMAC_TRTR_128 0x01000000
#define EMAC_TX_CTRL_GFCS 0x0200
#define EMAC_TX_CTRL_GP 0x0100
#define EMAC_TX_CTRL_ISA 0x0080
#define EMAC_TX_CTRL_RSA 0x0040
#define EMAC_TX_CTRL_IVT 0x0020
#define EMAC_TX_CTRL_RVT 0x0010
#define EMAC_TX_CTRL_TAH_CSUM 0x000e /* TAH only */
#define EMAC_TX_CTRL_TAH_SEG4 0x000a /* TAH only */
#define EMAC_TX_CTRL_TAH_SEG3 0x0008 /* TAH only */
#define EMAC_TX_CTRL_TAH_SEG2 0x0006 /* TAH only */
#define EMAC_TX_CTRL_TAH_SEG1 0x0004 /* TAH only */
#define EMAC_TX_CTRL_TAH_SEG0 0x0002 /* TAH only */
#define EMAC_TX_CTRL_TAH_DIS 0x0000 /* TAH only */
#define EMAC_TX_CTRL_DFLT ( \
MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )
/* madmal transmit status / Control bits */
#define EMAC_TX_ST_BFCS 0x0200
#define EMAC_TX_ST_BPP 0x0100
#define EMAC_TX_ST_LCS 0x0080
#define EMAC_TX_ST_ED 0x0040
#define EMAC_TX_ST_EC 0x0020
#define EMAC_TX_ST_LC 0x0010
#define EMAC_TX_ST_MC 0x0008
#define EMAC_TX_ST_SC 0x0004
#define EMAC_TX_ST_UR 0x0002
#define EMAC_TX_ST_SQE 0x0001
/* madmal receive status / Control bits */
#define EMAC_RX_ST_OE 0x0200
#define EMAC_RX_ST_PP 0x0100
#define EMAC_RX_ST_BP 0x0080
#define EMAC_RX_ST_RP 0x0040
#define EMAC_RX_ST_SE 0x0020
#define EMAC_RX_ST_AE 0x0010
#define EMAC_RX_ST_BFCS 0x0008
#define EMAC_RX_ST_PTL 0x0004
#define EMAC_RX_ST_ORE 0x0002
#define EMAC_RX_ST_IRE 0x0001
#define EMAC_BAD_RX_PACKET 0x02ff
#define EMAC_CSUM_VER_ERROR 0x0003
/* identify a bad rx packet dependent on emac features */
#ifdef CONFIG_IBM_EMAC4
#define EMAC_IS_BAD_RX_PACKET(desc) \
(((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \
((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \
((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))
#else
#define EMAC_IS_BAD_RX_PACKET(desc) \
(desc & EMAC_BAD_RX_PACKET)
#endif
/* SoC implementation specific EMAC register defaults */
#if defined(CONFIG_440GP)
#define EMAC_RWMR_DEFAULT 0x80009000
#define EMAC_TMR0_DEFAULT 0x00000000
#define EMAC_TMR1_DEFAULT 0xf8640000
#elif defined(CONFIG_440GX)
#define EMAC_RWMR_DEFAULT 0x1000a200
#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
#define EMAC_TMR1_DEFAULT 0xa00f0000
#elif defined(CONFIG_440SP)
#define EMAC_RWMR_DEFAULT 0x08002000
#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048
#define EMAC_TMR1_DEFAULT 0xf8200000
#else
#define EMAC_RWMR_DEFAULT 0x0f002000
#define EMAC_TMR0_DEFAULT 0x00000000
#define EMAC_TMR1_DEFAULT 0x380f0000
#endif /* CONFIG_440GP */
/* Revision specific EMAC register defaults */
#ifdef CONFIG_IBM_EMAC4
#define EMAC_M1_DEFAULT (EMAC_M1_BASE | \
EMAC_M1_OPB_CLK_83 | \
EMAC_M1_TX_MWSW)
#define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \
EMAC_RMR_RFAF_128_2048)
#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \
EMAC_TMR0_DEFAULT)
#define EMAC_TRTR_DEFAULT EMAC_TRTR_1024
#else /* !CONFIG_IBM_EMAC4 */
#define EMAC_M1_DEFAULT EMAC_M1_BASE
#define EMAC_RMR_DEFAULT EMAC_RMR_BASE
#define EMAC_TMR0_XMIT EMAC_TMR0_GNP0
#define EMAC_TRTR_DEFAULT EMAC_TRTR_1600
#endif /* CONFIG_IBM_EMAC4 */
#endif

2012
drivers/net/ibm_emac/ibm_emac_core.c Normal file
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146
drivers/net/ibm_emac/ibm_emac_core.h Normal file
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/*
* ibm_emac_core.h
*
* Ethernet driver for the built in ethernet on the IBM 405 PowerPC
* processor.
*
* Armin Kuster akuster@mvista.com
* Sept, 2001
*
* Orignial driver
* Johnnie Peters
* jpeters@mvista.com
*
* Copyright 2000 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IBM_EMAC_CORE_H_
#define _IBM_EMAC_CORE_H_
#include <linux/netdevice.h>
#include <asm/ocp.h>
#include <asm/mmu.h> /* For phys_addr_t */
#include "ibm_emac.h"
#include "ibm_emac_phy.h"
#include "ibm_emac_rgmii.h"
#include "ibm_emac_zmii.h"
#include "ibm_emac_mal.h"
#include "ibm_emac_tah.h"
#ifndef CONFIG_IBM_EMAC_TXB
#define NUM_TX_BUFF 64
#define NUM_RX_BUFF 64
#else
#define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
#define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
#endif
/* This does 16 byte alignment, exactly what we need.
* The packet length includes FCS, but we don't want to
* include that when passing upstream as it messes up
* bridging applications.
*/
#ifndef CONFIG_IBM_EMAC_SKBRES
#define SKB_RES 2
#else
#define SKB_RES CONFIG_IBM_EMAC_SKBRES
#endif
/* Note about alignement. alloc_skb() returns a cache line
* aligned buffer. However, dev_alloc_skb() will add 16 more
* bytes and "reserve" them, so our buffer will actually end
* on a half cache line. What we do is to use directly
* alloc_skb, allocate 16 more bytes to match the total amount
* allocated by dev_alloc_skb(), but we don't reserve.
*/
#define MAX_NUM_BUF_DESC 255
#define DESC_BUF_SIZE 4080 /* max 4096-16 */
#define DESC_BUF_SIZE_REG (DESC_BUF_SIZE / 16)
/* Transmitter timeout. */
#define TX_TIMEOUT (2*HZ)
/* MDIO latency delay */
#define MDIO_DELAY 250
/* Power managment shift registers */
#define IBM_CPM_EMMII 0 /* Shift value for MII */
#define IBM_CPM_EMRX 1 /* Shift value for recv */
#define IBM_CPM_EMTX 2 /* Shift value for MAC */
#define IBM_CPM_EMAC(x) (((x)>>IBM_CPM_EMMII) | ((x)>>IBM_CPM_EMRX) | ((x)>>IBM_CPM_EMTX))
#define ENET_HEADER_SIZE 14
#define ENET_FCS_SIZE 4
#define ENET_DEF_MTU_SIZE 1500
#define ENET_DEF_BUF_SIZE (ENET_DEF_MTU_SIZE + ENET_HEADER_SIZE + ENET_FCS_SIZE)
#define EMAC_MIN_FRAME 64
#define EMAC_MAX_FRAME 9018
#define EMAC_MIN_MTU (EMAC_MIN_FRAME - ENET_HEADER_SIZE - ENET_FCS_SIZE)
#define EMAC_MAX_MTU (EMAC_MAX_FRAME - ENET_HEADER_SIZE - ENET_FCS_SIZE)
#ifdef CONFIG_IBM_EMAC_ERRMSG
void emac_serr_dump_0(struct net_device *dev);
void emac_serr_dump_1(struct net_device *dev);
void emac_err_dump(struct net_device *dev, int em0isr);
void emac_phy_dump(struct net_device *);
void emac_desc_dump(struct net_device *);
void emac_mac_dump(struct net_device *);
void emac_mal_dump(struct net_device *);
#else
#define emac_serr_dump_0(dev) do { } while (0)
#define emac_serr_dump_1(dev) do { } while (0)
#define emac_err_dump(dev,x) do { } while (0)
#define emac_phy_dump(dev) do { } while (0)
#define emac_desc_dump(dev) do { } while (0)
#define emac_mac_dump(dev) do { } while (0)
#define emac_mal_dump(dev) do { } while (0)
#endif
struct ocp_enet_private {
struct sk_buff *tx_skb[NUM_TX_BUFF];
struct sk_buff *rx_skb[NUM_RX_BUFF];
struct mal_descriptor *tx_desc;
struct mal_descriptor *rx_desc;
struct mal_descriptor *rx_dirty;
struct net_device_stats stats;
int tx_cnt;
int rx_slot;
int dirty_rx;
int tx_slot;
int ack_slot;
int rx_buffer_size;
struct mii_phy phy_mii;
int mii_phy_addr;
int want_autoneg;
int timer_ticks;
struct timer_list link_timer;
struct net_device *mdio_dev;
struct ocp_device *rgmii_dev;
int rgmii_input;
struct ocp_device *zmii_dev;
int zmii_input;
struct ibm_ocp_mal *mal;
int mal_tx_chan, mal_rx_chan;
struct mal_commac commac;
struct ocp_device *tah_dev;
int opened;
int going_away;
int wol_irq;
emac_t *emacp;
struct ocp_device *ocpdev;
struct net_device *ndev;
spinlock_t lock;
};
#endif /* _IBM_EMAC_CORE_H_ */

224
drivers/net/ibm_emac/ibm_emac_debug.c Normal file
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/*
* ibm_ocp_debug.c
*
* This has all the debug routines that where in *_enet.c
*
* Armin Kuster akuster@mvista.com
* April , 2002
*
* Copyright 2002 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <asm/io.h>
#include "ibm_ocp_mal.h"
#include "ibm_ocp_zmii.h"
#include "ibm_ocp_enet.h"
extern int emac_phy_read(struct net_device *dev, int mii_id, int reg);
void emac_phy_dump(struct net_device *dev)
{
struct ocp_enet_private *fep = dev->priv;
unsigned long i;
uint data;
printk(KERN_DEBUG " Prepare for Phy dump....\n");
for (i = 0; i < 0x1A; i++) {
data = emac_phy_read(dev, fep->mii_phy_addr, i);
printk(KERN_DEBUG "Phy reg 0x%lx ==> %4x\n", i, data);
if (i == 0x07)
i = 0x0f;
}
}
void emac_desc_dump(struct net_device *dev)
{
struct ocp_enet_private *fep = dev->priv;
int curr_slot;
printk(KERN_DEBUG
"dumping the receive descriptors: current slot is %d\n",
fep->rx_slot);
for (curr_slot = 0; curr_slot < NUM_RX_BUFF; curr_slot++) {
printk(KERN_DEBUG
"Desc %02d: status 0x%04x, length %3d, addr 0x%x\n",
curr_slot, fep->rx_desc[curr_slot].ctrl,
fep->rx_desc[curr_slot].data_len,
(unsigned int)fep->rx_desc[curr_slot].data_ptr);
}
}
void emac_mac_dump(struct net_device *dev)
{
struct ocp_enet_private *fep = dev->priv;
volatile emac_t *emacp = fep->emacp;
printk(KERN_DEBUG "EMAC DEBUG ********** \n");
printk(KERN_DEBUG "EMAC_M0 ==> 0x%x\n", in_be32(&emacp->em0mr0));
printk(KERN_DEBUG "EMAC_M1 ==> 0x%x\n", in_be32(&emacp->em0mr1));
printk(KERN_DEBUG "EMAC_TXM0==> 0x%x\n", in_be32(&emacp->em0tmr0));
printk(KERN_DEBUG "EMAC_TXM1==> 0x%x\n", in_be32(&emacp->em0tmr1));
printk(KERN_DEBUG "EMAC_RXM ==> 0x%x\n", in_be32(&emacp->em0rmr));
printk(KERN_DEBUG "EMAC_ISR ==> 0x%x\n", in_be32(&emacp->em0isr));
printk(KERN_DEBUG "EMAC_IER ==> 0x%x\n", in_be32(&emacp->em0iser));
printk(KERN_DEBUG "EMAC_IAH ==> 0x%x\n", in_be32(&emacp->em0iahr));
printk(KERN_DEBUG "EMAC_IAL ==> 0x%x\n", in_be32(&emacp->em0ialr));
printk(KERN_DEBUG "EMAC_VLAN_TPID_REG ==> 0x%x\n",
in_be32(&emacp->em0vtpid));
}
void emac_mal_dump(struct net_device *dev)
{
struct ibm_ocp_mal *mal = ((struct ocp_enet_private *)dev->priv)->mal;
printk(KERN_DEBUG " MAL DEBUG ********** \n");
printk(KERN_DEBUG " MCR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALCR));
printk(KERN_DEBUG " ESR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALESR));
printk(KERN_DEBUG " IER ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALIER));
#ifdef CONFIG_40x
printk(KERN_DEBUG " DBR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALDBR));
#endif /* CONFIG_40x */
printk(KERN_DEBUG " TXCASR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCASR));
printk(KERN_DEBUG " TXCARR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCARR));
printk(KERN_DEBUG " TXEOBISR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXEOBISR));
printk(KERN_DEBUG " TXDEIR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXDEIR));
printk(KERN_DEBUG " RXCASR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXCASR));
printk(KERN_DEBUG " RXCARR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXCARR));
printk(KERN_DEBUG " RXEOBISR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXEOBISR));
printk(KERN_DEBUG " RXDEIR ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXDEIR));
printk(KERN_DEBUG " TXCTP0R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCTP0R));
printk(KERN_DEBUG " TXCTP1R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCTP1R));
printk(KERN_DEBUG " TXCTP2R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCTP2R));
printk(KERN_DEBUG " TXCTP3R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALTXCTP3R));
printk(KERN_DEBUG " RXCTP0R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXCTP0R));
printk(KERN_DEBUG " RXCTP1R ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRXCTP1R));
printk(KERN_DEBUG " RCBS0 ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRCBS0));
printk(KERN_DEBUG " RCBS1 ==> 0x%x\n",
(unsigned int)get_mal_dcrn(mal, DCRN_MALRCBS1));
}
void emac_serr_dump_0(struct net_device *dev)
{
struct ibm_ocp_mal *mal = ((struct ocp_enet_private *)dev->priv)->mal;
unsigned long int mal_error, plb_error, plb_addr;
mal_error = get_mal_dcrn(mal, DCRN_MALESR);
printk(KERN_DEBUG "ppc405_eth_serr: %s channel %ld \n",
(mal_error & 0x40000000) ? "Receive" :
"Transmit", (mal_error & 0x3e000000) >> 25);
printk(KERN_DEBUG " ----- latched error -----\n");
if (mal_error & MALESR_DE)
printk(KERN_DEBUG " DE: descriptor error\n");
if (mal_error & MALESR_OEN)
printk(KERN_DEBUG " ONE: OPB non-fullword error\n");
if (mal_error & MALESR_OTE)
printk(KERN_DEBUG " OTE: OPB timeout error\n");
if (mal_error & MALESR_OSE)
printk(KERN_DEBUG " OSE: OPB slave error\n");
if (mal_error & MALESR_PEIN) {
plb_error = mfdcr(DCRN_PLB0_BESR);
printk(KERN_DEBUG
" PEIN: PLB error, PLB0_BESR is 0x%x\n",
(unsigned int)plb_error);
plb_addr = mfdcr(DCRN_PLB0_BEAR);
printk(KERN_DEBUG
" PEIN: PLB error, PLB0_BEAR is 0x%x\n",
(unsigned int)plb_addr);
}
}
void emac_serr_dump_1(struct net_device *dev)
{
struct ibm_ocp_mal *mal = ((struct ocp_enet_private *)dev->priv)->mal;
int mal_error = get_mal_dcrn(mal, DCRN_MALESR);
printk(KERN_DEBUG " ----- cumulative errors -----\n");
if (mal_error & MALESR_DEI)
printk(KERN_DEBUG " DEI: descriptor error interrupt\n");
if (mal_error & MALESR_ONEI)
printk(KERN_DEBUG " OPB non-fullword error interrupt\n");
if (mal_error & MALESR_OTEI)
printk(KERN_DEBUG " OTEI: timeout error interrupt\n");
if (mal_error & MALESR_OSEI)
printk(KERN_DEBUG " OSEI: slave error interrupt\n");
if (mal_error & MALESR_PBEI)
printk(KERN_DEBUG " PBEI: PLB bus error interrupt\n");
}
void emac_err_dump(struct net_device *dev, int em0isr)
{
printk(KERN_DEBUG "%s: on-chip ethernet error:\n", dev->name);
if (em0isr & EMAC_ISR_OVR)
printk(KERN_DEBUG " OVR: overrun\n");
if (em0isr & EMAC_ISR_PP)
printk(KERN_DEBUG " PP: control pause packet\n");
if (em0isr & EMAC_ISR_BP)
printk(KERN_DEBUG " BP: packet error\n");
if (em0isr & EMAC_ISR_RP)
printk(KERN_DEBUG " RP: runt packet\n");
if (em0isr & EMAC_ISR_SE)
printk(KERN_DEBUG " SE: short event\n");
if (em0isr & EMAC_ISR_ALE)
printk(KERN_DEBUG " ALE: odd number of nibbles in packet\n");
if (em0isr & EMAC_ISR_BFCS)
printk(KERN_DEBUG " BFCS: bad FCS\n");
if (em0isr & EMAC_ISR_PTLE)
printk(KERN_DEBUG " PTLE: oversized packet\n");
if (em0isr & EMAC_ISR_ORE)
printk(KERN_DEBUG
" ORE: packet length field > max allowed LLC\n");
if (em0isr & EMAC_ISR_IRE)
printk(KERN_DEBUG " IRE: In Range error\n");
if (em0isr & EMAC_ISR_DBDM)
printk(KERN_DEBUG " DBDM: xmit error or SQE\n");
if (em0isr & EMAC_ISR_DB0)
printk(KERN_DEBUG " DB0: xmit error or SQE on TX channel 0\n");
if (em0isr & EMAC_ISR_SE0)
printk(KERN_DEBUG
" SE0: Signal Quality Error test failure from TX channel 0\n");
if (em0isr & EMAC_ISR_TE0)
printk(KERN_DEBUG " TE0: xmit channel 0 aborted\n");
if (em0isr & EMAC_ISR_DB1)
printk(KERN_DEBUG " DB1: xmit error or SQE on TX channel \n");
if (em0isr & EMAC_ISR_SE1)
printk(KERN_DEBUG
" SE1: Signal Quality Error test failure from TX channel 1\n");
if (em0isr & EMAC_ISR_TE1)
printk(KERN_DEBUG " TE1: xmit channel 1 aborted\n");
if (em0isr & EMAC_ISR_MOS)
printk(KERN_DEBUG " MOS\n");
if (em0isr & EMAC_ISR_MOF)
printk(KERN_DEBUG " MOF\n");
emac_mac_dump(dev);
emac_mal_dump(dev);
}

463
drivers/net/ibm_emac/ibm_emac_mal.c Normal file
View File

@@ -0,0 +1,463 @@
/*
* ibm_ocp_mal.c
*
* Armin Kuster akuster@mvista.com
* Juen, 2002
*
* Copyright 2002 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/ocp.h>
#include "ibm_emac_mal.h"
// Locking: Should we share a lock with the client ? The client could provide
// a lock pointer (optionally) in the commac structure... I don't think this is
// really necessary though
/* This lock protects the commac list. On today UP implementations, it's
* really only used as IRQ protection in mal_{register,unregister}_commac()
*/
static DEFINE_RWLOCK(mal_list_lock);
int mal_register_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
{
unsigned long flags;
write_lock_irqsave(&mal_list_lock, flags);
/* Don't let multiple commacs claim the same channel */
if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
(mal->rx_chan_mask & commac->rx_chan_mask)) {
write_unlock_irqrestore(&mal_list_lock, flags);
return -EBUSY;
}
mal->tx_chan_mask |= commac->tx_chan_mask;
mal->rx_chan_mask |= commac->rx_chan_mask;
list_add(&commac->list, &mal->commac);
write_unlock_irqrestore(&mal_list_lock, flags);
return 0;
}
int mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
{
unsigned long flags;
write_lock_irqsave(&mal_list_lock, flags);
mal->tx_chan_mask &= ~commac->tx_chan_mask;
mal->rx_chan_mask &= ~commac->rx_chan_mask;
list_del_init(&commac->list);
write_unlock_irqrestore(&mal_list_lock, flags);
return 0;
}
int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
{
switch (channel) {
case 0:
set_mal_dcrn(mal, DCRN_MALRCBS0, size);
break;
#ifdef DCRN_MALRCBS1
case 1:
set_mal_dcrn(mal, DCRN_MALRCBS1, size);
break;
#endif
#ifdef DCRN_MALRCBS2
case 2:
set_mal_dcrn(mal, DCRN_MALRCBS2, size);
break;
#endif
#ifdef DCRN_MALRCBS3
case 3:
set_mal_dcrn(mal, DCRN_MALRCBS3, size);
break;
#endif
default:
return -EINVAL;
}
return 0;
}
static irqreturn_t mal_serr(int irq, void *dev_instance, struct pt_regs *regs)
{
struct ibm_ocp_mal *mal = dev_instance;
unsigned long mal_error;
/*
* This SERR applies to one of the devices on the MAL, here we charge
* it against the first EMAC registered for the MAL.
*/
mal_error = get_mal_dcrn(mal, DCRN_MALESR);
printk(KERN_ERR "%s: System Error (MALESR=%lx)\n",
"MAL" /* FIXME: get the name right */ , mal_error);
/* FIXME: decipher error */
/* DIXME: distribute to commacs, if possible */
/* Clear the error status register */
set_mal_dcrn(mal, DCRN_MALESR, mal_error);
return IRQ_HANDLED;
}
static irqreturn_t mal_txeob(int irq, void *dev_instance, struct pt_regs *regs)
{
struct ibm_ocp_mal *mal = dev_instance;
struct list_head *l;
unsigned long isr;
isr = get_mal_dcrn(mal, DCRN_MALTXEOBISR);
set_mal_dcrn(mal, DCRN_MALTXEOBISR, isr);
read_lock(&mal_list_lock);
list_for_each(l, &mal->commac) {
struct mal_commac *mc = list_entry(l, struct mal_commac, list);
if (isr & mc->tx_chan_mask) {
mc->ops->txeob(mc->dev, isr & mc->tx_chan_mask);
}
}
read_unlock(&mal_list_lock);
return IRQ_HANDLED;
}
static irqreturn_t mal_rxeob(int irq, void *dev_instance, struct pt_regs *regs)
{
struct ibm_ocp_mal *mal = dev_instance;
struct list_head *l;
unsigned long isr;
isr = get_mal_dcrn(mal, DCRN_MALRXEOBISR);
set_mal_dcrn(mal, DCRN_MALRXEOBISR, isr);
read_lock(&mal_list_lock);
list_for_each(l, &mal->commac) {
struct mal_commac *mc = list_entry(l, struct mal_commac, list);
if (isr & mc->rx_chan_mask) {
mc->ops->rxeob(mc->dev, isr & mc->rx_chan_mask);
}
}
read_unlock(&mal_list_lock);
return IRQ_HANDLED;
}
static irqreturn_t mal_txde(int irq, void *dev_instance, struct pt_regs *regs)
{
struct ibm_ocp_mal *mal = dev_instance;
struct list_head *l;
unsigned long deir;
deir = get_mal_dcrn(mal, DCRN_MALTXDEIR);
/* FIXME: print which MAL correctly */
printk(KERN_WARNING "%s: Tx descriptor error (MALTXDEIR=%lx)\n",
"MAL", deir);
read_lock(&mal_list_lock);
list_for_each(l, &mal->commac) {
struct mal_commac *mc = list_entry(l, struct mal_commac, list);
if (deir & mc->tx_chan_mask) {
mc->ops->txde(mc->dev, deir & mc->tx_chan_mask);
}
}
read_unlock(&mal_list_lock);
return IRQ_HANDLED;
}
/*
* This interrupt should be very rare at best. This occurs when
* the hardware has a problem with the receive descriptors. The manual
* states that it occurs when the hardware cannot the receive descriptor
* empty bit is not set. The recovery mechanism will be to
* traverse through the descriptors, handle any that are marked to be
* handled and reinitialize each along the way. At that point the driver
* will be restarted.
*/
static irqreturn_t mal_rxde(int irq, void *dev_instance, struct pt_regs *regs)
{
struct ibm_ocp_mal *mal = dev_instance;
struct list_head *l;
unsigned long deir;
deir = get_mal_dcrn(mal, DCRN_MALRXDEIR);
/*
* This really is needed. This case encountered in stress testing.
*/
if (deir == 0)
return IRQ_HANDLED;
/* FIXME: print which MAL correctly */
printk(KERN_WARNING "%s: Rx descriptor error (MALRXDEIR=%lx)\n",
"MAL", deir);
read_lock(&mal_list_lock);
list_for_each(l, &mal->commac) {
struct mal_commac *mc = list_entry(l, struct mal_commac, list);
if (deir & mc->rx_chan_mask) {
mc->ops->rxde(mc->dev, deir & mc->rx_chan_mask);
}
}
read_unlock(&mal_list_lock);
return IRQ_HANDLED;
}
static int __init mal_probe(struct ocp_device *ocpdev)
{
struct ibm_ocp_mal *mal = NULL;
struct ocp_func_mal_data *maldata;
int err = 0;
maldata = (struct ocp_func_mal_data *)ocpdev->def->additions;
if (maldata == NULL) {
printk(KERN_ERR "mal%d: Missing additional datas !\n",
ocpdev->def->index);
return -ENODEV;
}
mal = kmalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
if (mal == NULL) {
printk(KERN_ERR
"mal%d: Out of memory allocating MAL structure !\n",
ocpdev->def->index);
return -ENOMEM;
}
memset(mal, 0, sizeof(*mal));
switch (ocpdev->def->index) {
case 0:
mal->dcrbase = DCRN_MAL_BASE;
break;
#ifdef DCRN_MAL1_BASE
case 1:
mal->dcrbase = DCRN_MAL1_BASE;
break;
#endif
default:
BUG();
}
/**************************/
INIT_LIST_HEAD(&mal->commac);
set_mal_dcrn(mal, DCRN_MALRXCARR, 0xFFFFFFFF);
set_mal_dcrn(mal, DCRN_MALTXCARR, 0xFFFFFFFF);
set_mal_dcrn(mal, DCRN_MALCR, MALCR_MMSR); /* 384 */
/* FIXME: Add delay */
/* Set the MAL configuration register */
set_mal_dcrn(mal, DCRN_MALCR,
MALCR_PLBB | MALCR_OPBBL | MALCR_LEA |
MALCR_PLBLT_DEFAULT);
/* It would be nice to allocate buffers separately for each
* channel, but we can't because the channels share the upper
* 13 bits of address lines. Each channels buffer must also
* be 4k aligned, so we allocate 4k for each channel. This is
* inefficient FIXME: do better, if possible */
mal->tx_virt_addr = dma_alloc_coherent(&ocpdev->dev,
MAL_DT_ALIGN *
maldata->num_tx_chans,
&mal->tx_phys_addr, GFP_KERNEL);
if (mal->tx_virt_addr == NULL) {
printk(KERN_ERR
"mal%d: Out of memory allocating MAL descriptors !\n",
ocpdev->def->index);
err = -ENOMEM;
goto fail;
}
/* God, oh, god, I hate DCRs */
set_mal_dcrn(mal, DCRN_MALTXCTP0R, mal->tx_phys_addr);
#ifdef DCRN_MALTXCTP1R
if (maldata->num_tx_chans > 1)
set_mal_dcrn(mal, DCRN_MALTXCTP1R,
mal->tx_phys_addr + MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP1R */
#ifdef DCRN_MALTXCTP2R
if (maldata->num_tx_chans > 2)
set_mal_dcrn(mal, DCRN_MALTXCTP2R,
mal->tx_phys_addr + 2 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP2R */
#ifdef DCRN_MALTXCTP3R
if (maldata->num_tx_chans > 3)
set_mal_dcrn(mal, DCRN_MALTXCTP3R,
mal->tx_phys_addr + 3 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP3R */
#ifdef DCRN_MALTXCTP4R
if (maldata->num_tx_chans > 4)
set_mal_dcrn(mal, DCRN_MALTXCTP4R,
mal->tx_phys_addr + 4 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP4R */
#ifdef DCRN_MALTXCTP5R
if (maldata->num_tx_chans > 5)
set_mal_dcrn(mal, DCRN_MALTXCTP5R,
mal->tx_phys_addr + 5 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP5R */
#ifdef DCRN_MALTXCTP6R
if (maldata->num_tx_chans > 6)
set_mal_dcrn(mal, DCRN_MALTXCTP6R,
mal->tx_phys_addr + 6 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP6R */
#ifdef DCRN_MALTXCTP7R
if (maldata->num_tx_chans > 7)
set_mal_dcrn(mal, DCRN_MALTXCTP7R,
mal->tx_phys_addr + 7 * MAL_DT_ALIGN);
#endif /* DCRN_MALTXCTP7R */
mal->rx_virt_addr = dma_alloc_coherent(&ocpdev->dev,
MAL_DT_ALIGN *
maldata->num_rx_chans,
&mal->rx_phys_addr, GFP_KERNEL);
set_mal_dcrn(mal, DCRN_MALRXCTP0R, mal->rx_phys_addr);
#ifdef DCRN_MALRXCTP1R
if (maldata->num_rx_chans > 1)
set_mal_dcrn(mal, DCRN_MALRXCTP1R,
mal->rx_phys_addr + MAL_DT_ALIGN);
#endif /* DCRN_MALRXCTP1R */
#ifdef DCRN_MALRXCTP2R
if (maldata->num_rx_chans > 2)
set_mal_dcrn(mal, DCRN_MALRXCTP2R,
mal->rx_phys_addr + 2 * MAL_DT_ALIGN);
#endif /* DCRN_MALRXCTP2R */
#ifdef DCRN_MALRXCTP3R
if (maldata->num_rx_chans > 3)
set_mal_dcrn(mal, DCRN_MALRXCTP3R,
mal->rx_phys_addr + 3 * MAL_DT_ALIGN);
#endif /* DCRN_MALRXCTP3R */
err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
if (err)
goto fail;
err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE ", mal);
if (err)
goto fail;
err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
if (err)
goto fail;
err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
if (err)
goto fail;
err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
if (err)
goto fail;
set_mal_dcrn(mal, DCRN_MALIER,
MALIER_DE | MALIER_NE | MALIER_TE |
MALIER_OPBE | MALIER_PLBE);
/* Advertise me to the rest of the world */
ocp_set_drvdata(ocpdev, mal);
printk(KERN_INFO "mal%d: Initialized, %d tx channels, %d rx channels\n",
ocpdev->def->index, maldata->num_tx_chans,
maldata->num_rx_chans);
return 0;
fail:
/* FIXME: dispose requested IRQs ! */
if (err && mal)
kfree(mal);
return err;
}
static void __exit mal_remove(struct ocp_device *ocpdev)
{
struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
struct ocp_func_mal_data *maldata = ocpdev->def->additions;
BUG_ON(!maldata);
ocp_set_drvdata(ocpdev, NULL);
/* FIXME: shut down the MAL, deal with dependency with emac */
free_irq(maldata->serr_irq, mal);
free_irq(maldata->txde_irq, mal);
free_irq(maldata->txeob_irq, mal);
free_irq(maldata->rxde_irq, mal);
free_irq(maldata->rxeob_irq, mal);
if (mal->tx_virt_addr)
dma_free_coherent(&ocpdev->dev,
MAL_DT_ALIGN * maldata->num_tx_chans,
mal->tx_virt_addr, mal->tx_phys_addr);
if (mal->rx_virt_addr)
dma_free_coherent(&ocpdev->dev,
MAL_DT_ALIGN * maldata->num_rx_chans,
mal->rx_virt_addr, mal->rx_phys_addr);
kfree(mal);
}
/* Structure for a device driver */
static struct ocp_device_id mal_ids[] = {
{.vendor = OCP_ANY_ID,.function = OCP_FUNC_MAL},
{.vendor = OCP_VENDOR_INVALID}
};
static struct ocp_driver mal_driver = {
.name = "mal",
.id_table = mal_ids,
.probe = mal_probe,
.remove = mal_remove,
};
static int __init init_mals(void)
{
int rc;
rc = ocp_register_driver(&mal_driver);
if (rc < 0) {
ocp_unregister_driver(&mal_driver);
return -ENODEV;
}
return 0;
}
static void __exit exit_mals(void)
{
ocp_unregister_driver(&mal_driver);
}
module_init(init_mals);
module_exit(exit_mals);

131
drivers/net/ibm_emac/ibm_emac_mal.h Normal file
View File

@@ -0,0 +1,131 @@
#ifndef _IBM_EMAC_MAL_H
#define _IBM_EMAC_MAL_H
#include <linux/list.h>
#define MAL_DT_ALIGN (4096) /* Alignment for each channel's descriptor table */
#define MAL_CHAN_MASK(chan) (0x80000000 >> (chan))
/* MAL Buffer Descriptor structure */
struct mal_descriptor {
unsigned short ctrl; /* MAL / Commac status control bits */
short data_len; /* Max length is 4K-1 (12 bits) */
unsigned char *data_ptr; /* pointer to actual data buffer */
} __attribute__ ((packed));
/* the following defines are for the MadMAL status and control registers. */
/* MADMAL transmit and receive status/control bits */
#define MAL_RX_CTRL_EMPTY 0x8000
#define MAL_RX_CTRL_WRAP 0x4000
#define MAL_RX_CTRL_CM 0x2000
#define MAL_RX_CTRL_LAST 0x1000
#define MAL_RX_CTRL_FIRST 0x0800
#define MAL_RX_CTRL_INTR 0x0400
#define MAL_TX_CTRL_READY 0x8000
#define MAL_TX_CTRL_WRAP 0x4000
#define MAL_TX_CTRL_CM 0x2000
#define MAL_TX_CTRL_LAST 0x1000
#define MAL_TX_CTRL_INTR 0x0400
struct mal_commac_ops {
void (*txeob) (void *dev, u32 chanmask);
void (*txde) (void *dev, u32 chanmask);
void (*rxeob) (void *dev, u32 chanmask);
void (*rxde) (void *dev, u32 chanmask);
};
struct mal_commac {
struct mal_commac_ops *ops;
void *dev;
u32 tx_chan_mask, rx_chan_mask;
struct list_head list;
};
struct ibm_ocp_mal {
int dcrbase;
struct list_head commac;
u32 tx_chan_mask, rx_chan_mask;
dma_addr_t tx_phys_addr;
struct mal_descriptor *tx_virt_addr;
dma_addr_t rx_phys_addr;
struct mal_descriptor *rx_virt_addr;
};
#define GET_MAL_STANZA(base,dcrn) \
case base: \
x = mfdcr(dcrn(base)); \
break;
#define SET_MAL_STANZA(base,dcrn, val) \
case base: \
mtdcr(dcrn(base), (val)); \
break;
#define GET_MAL0_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL_BASE,dcrn)
#define SET_MAL0_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL_BASE,dcrn,val)
#ifdef DCRN_MAL1_BASE
#define GET_MAL1_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL1_BASE,dcrn)
#define SET_MAL1_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL1_BASE,dcrn,val)
#else /* ! DCRN_MAL1_BASE */
#define GET_MAL1_STANZA(dcrn)
#define SET_MAL1_STANZA(dcrn,val)
#endif
#define get_mal_dcrn(mal, dcrn) ({ \
u32 x; \
switch ((mal)->dcrbase) { \
GET_MAL0_STANZA(dcrn) \
GET_MAL1_STANZA(dcrn) \
default: \
x = 0; \
BUG(); \
} \
x; })
#define set_mal_dcrn(mal, dcrn, val) do { \
switch ((mal)->dcrbase) { \
SET_MAL0_STANZA(dcrn,val) \
SET_MAL1_STANZA(dcrn,val) \
default: \
BUG(); \
} } while (0)
static inline void mal_enable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
{
set_mal_dcrn(mal, DCRN_MALTXCASR,
get_mal_dcrn(mal, DCRN_MALTXCASR) | chanmask);
}
static inline void mal_disable_tx_channels(struct ibm_ocp_mal *mal,
u32 chanmask)
{
set_mal_dcrn(mal, DCRN_MALTXCARR, chanmask);
}
static inline void mal_enable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
{
set_mal_dcrn(mal, DCRN_MALRXCASR,
get_mal_dcrn(mal, DCRN_MALRXCASR) | chanmask);
}
static inline void mal_disable_rx_channels(struct ibm_ocp_mal *mal,
u32 chanmask)
{
set_mal_dcrn(mal, DCRN_MALRXCARR, chanmask);
}
extern int mal_register_commac(struct ibm_ocp_mal *mal,
struct mal_commac *commac);
extern int mal_unregister_commac(struct ibm_ocp_mal *mal,
struct mal_commac *commac);
extern int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel,
unsigned long size);
#endif /* _IBM_EMAC_MAL_H */

298
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/*
* ibm_ocp_phy.c
*
* PHY drivers for the ibm ocp ethernet driver. Borrowed
* from sungem_phy.c, though I only kept the generic MII
* driver for now.
*
* This file should be shared with other drivers or eventually
* merged as the "low level" part of miilib
*
* (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
#include "ibm_emac_phy.h"
static int reset_one_mii_phy(struct mii_phy *phy, int phy_id)
{
u16 val;
int limit = 10000;
val = __phy_read(phy, phy_id, MII_BMCR);
val &= ~BMCR_ISOLATE;
val |= BMCR_RESET;
__phy_write(phy, phy_id, MII_BMCR, val);
udelay(100);
while (limit--) {
val = __phy_read(phy, phy_id, MII_BMCR);
if ((val & BMCR_RESET) == 0)
break;
udelay(10);
}
if ((val & BMCR_ISOLATE) && limit > 0)
__phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
return (limit <= 0);
}
static int cis8201_init(struct mii_phy *phy)
{
u16 epcr;
epcr = phy_read(phy, MII_CIS8201_EPCR);
epcr &= ~EPCR_MODE_MASK;
switch (phy->mode) {
case PHY_MODE_TBI:
epcr |= EPCR_TBI_MODE;
break;
case PHY_MODE_RTBI:
epcr |= EPCR_RTBI_MODE;
break;
case PHY_MODE_GMII:
epcr |= EPCR_GMII_MODE;
break;
case PHY_MODE_RGMII:
default:
epcr |= EPCR_RGMII_MODE;
}
phy_write(phy, MII_CIS8201_EPCR, epcr);
return 0;
}
static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
phy->autoneg = 1;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = 0;
phy->advertising = advertise;
/* Setup standard advertise */
adv = phy_read(phy, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
phy_write(phy, MII_ADVERTISE, adv);
/* Start/Restart aneg */
ctl = phy_read(phy, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl;
phy->autoneg = 0;
phy->speed = speed;
phy->duplex = fd;
phy->pause = 0;
ctl = phy_read(phy, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
/* First reset the PHY */
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
/* Select speed & duplex */
switch (speed) {
case SPEED_10:
break;
case SPEED_100:
ctl |= BMCR_SPEED100;
break;
case SPEED_1000:
default:
return -EINVAL;
}
if (fd == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_poll_link(struct mii_phy *phy)
{
u16 status;
(void)phy_read(phy, MII_BMSR);
status = phy_read(phy, MII_BMSR);
if ((status & BMSR_LSTATUS) == 0)
return 0;
if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
return 0;
return 1;
}
#define MII_CIS8201_ACSR 0x1c
#define ACSR_DUPLEX_STATUS 0x0020
#define ACSR_SPEED_1000BASET 0x0010
#define ACSR_SPEED_100BASET 0x0008
static int cis8201_read_link(struct mii_phy *phy)
{
u16 acsr;
if (phy->autoneg) {
acsr = phy_read(phy, MII_CIS8201_ACSR);
if (acsr & ACSR_DUPLEX_STATUS)
phy->duplex = DUPLEX_FULL;
else
phy->duplex = DUPLEX_HALF;
if (acsr & ACSR_SPEED_1000BASET) {
phy->speed = SPEED_1000;
} else if (acsr & ACSR_SPEED_100BASET)
phy->speed = SPEED_100;
else
phy->speed = SPEED_10;
phy->pause = 0;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
static int genmii_read_link(struct mii_phy *phy)
{
u16 lpa;
if (phy->autoneg) {
lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = 0;
if (lpa & (LPA_100FULL | LPA_100HALF)) {
phy->speed = SPEED_100;
if (lpa & LPA_100FULL)
phy->duplex = DUPLEX_FULL;
} else if (lpa & LPA_10FULL)
phy->duplex = DUPLEX_FULL;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
/* CIS8201 phy ops */
static struct mii_phy_ops cis8201_phy_ops = {
init:cis8201_init,
setup_aneg:genmii_setup_aneg,
setup_forced:genmii_setup_forced,
poll_link:genmii_poll_link,
read_link:cis8201_read_link
};
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
setup_aneg:genmii_setup_aneg,
setup_forced:genmii_setup_forced,
poll_link:genmii_poll_link,
read_link:genmii_read_link
};
static struct mii_phy_def cis8201_phy_def = {
phy_id:0x000fc410,
phy_id_mask:0x000ffff0,
name:"CIS8201 Gigabit Ethernet",
features:MII_GBIT_FEATURES,
magic_aneg:0,
ops:&cis8201_phy_ops
};
static struct mii_phy_def genmii_phy_def = {
phy_id:0x00000000,
phy_id_mask:0x00000000,
name:"Generic MII",
features:MII_BASIC_FEATURES,
magic_aneg:0,
ops:&generic_phy_ops
};
static struct mii_phy_def *mii_phy_table[] = {
&cis8201_phy_def,
&genmii_phy_def,
NULL
};
int mii_phy_probe(struct mii_phy *phy, int mii_id)
{
int rc;
u32 id;
struct mii_phy_def *def;
int i;
phy->autoneg = 0;
phy->advertising = 0;
phy->mii_id = mii_id;
phy->speed = 0;
phy->duplex = 0;
phy->pause = 0;
/* Take PHY out of isloate mode and reset it. */
rc = reset_one_mii_phy(phy, mii_id);
if (rc)
return -ENODEV;
/* Read ID and find matching entry */
id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2))
& 0xfffffff0;
for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
if ((id & def->phy_id_mask) == def->phy_id)
break;
/* Should never be NULL (we have a generic entry), but... */
if (def == NULL)
return -ENODEV;
phy->def = def;
/* Setup default advertising */
phy->advertising = def->features;
return 0;
}
MODULE_LICENSE("GPL");

137
drivers/net/ibm_emac/ibm_emac_phy.h Normal file
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/*
* ibm_emac_phy.h
*
*
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
* February 2003
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* This file basically duplicates sungem_phy.{c,h} with different PHYs
* supported. I'm looking into merging that in a single mii layer more
* flexible than mii.c
*/
#ifndef _IBM_EMAC_PHY_H_
#define _IBM_EMAC_PHY_H_
/*
* PHY mode settings
* Used for multi-mode capable PHYs
*/
#define PHY_MODE_NA 0
#define PHY_MODE_MII 1
#define PHY_MODE_RMII 2
#define PHY_MODE_SMII 3
#define PHY_MODE_RGMII 4
#define PHY_MODE_TBI 5
#define PHY_MODE_GMII 6
#define PHY_MODE_RTBI 7
#define PHY_MODE_SGMII 8
/*
* PHY specific registers/values
*/
/* CIS8201 */
#define MII_CIS8201_EPCR 0x17
#define EPCR_MODE_MASK 0x3000
#define EPCR_GMII_MODE 0x0000
#define EPCR_RGMII_MODE 0x1000
#define EPCR_TBI_MODE 0x2000
#define EPCR_RTBI_MODE 0x3000
struct mii_phy;
/* Operations supported by any kind of PHY */
struct mii_phy_ops {
int (*init) (struct mii_phy * phy);
int (*suspend) (struct mii_phy * phy, int wol_options);
int (*setup_aneg) (struct mii_phy * phy, u32 advertise);
int (*setup_forced) (struct mii_phy * phy, int speed, int fd);
int (*poll_link) (struct mii_phy * phy);
int (*read_link) (struct mii_phy * phy);
};
/* Structure used to statically define an mii/gii based PHY */
struct mii_phy_def {
u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
u32 phy_id_mask; /* Significant bits */
u32 features; /* Ethtool SUPPORTED_* defines */
int magic_aneg; /* Autoneg does all speed test for us */
const char *name;
const struct mii_phy_ops *ops;
};
/* An instance of a PHY, partially borrowed from mii_if_info */
struct mii_phy {
struct mii_phy_def *def;
int advertising;
int mii_id;
/* 1: autoneg enabled, 0: disabled */
int autoneg;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
int pause;
/* PHY mode - if needed */
int mode;
/* Provided by host chip */
struct net_device *dev;
int (*mdio_read) (struct net_device * dev, int mii_id, int reg);
void (*mdio_write) (struct net_device * dev, int mii_id, int reg,
int val);
};
/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
* filled, the remaining fields will be filled on return
*/
extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
static inline int __phy_read(struct mii_phy *phy, int id, int reg)
{
return phy->mdio_read(phy->dev, id, reg);
}
static inline void __phy_write(struct mii_phy *phy, int id, int reg, int val)
{
phy->mdio_write(phy->dev, id, reg, val);
}
static inline int phy_read(struct mii_phy *phy, int reg)
{
return phy->mdio_read(phy->dev, phy->mii_id, reg);
}
static inline void phy_write(struct mii_phy *phy, int reg, int val)
{
phy->mdio_write(phy->dev, phy->mii_id, reg, val);
}
#endif /* _IBM_EMAC_PHY_H_ */

65
drivers/net/ibm_emac/ibm_emac_rgmii.h Normal file
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/*
* Defines for the IBM RGMII bridge
*
* Based on ocp_zmii.h/ibm_emac_zmii.h
* Armin Kuster akuster@mvista.com
*
* Copyright 2004 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IBM_EMAC_RGMII_H_
#define _IBM_EMAC_RGMII_H_
#include <linux/config.h>
/* RGMII bridge */
typedef struct rgmii_regs {
u32 fer; /* Function enable register */
u32 ssr; /* Speed select register */
} rgmii_t;
#define RGMII_INPUTS 4
/* RGMII device */
struct ibm_ocp_rgmii {
struct rgmii_regs *base;
int mode[RGMII_INPUTS];
int users; /* number of EMACs using this RGMII bridge */
};
/* Fuctional Enable Reg */
#define RGMII_FER_MASK(x) (0x00000007 << (4*x))
#define RGMII_RTBI 0x00000004
#define RGMII_RGMII 0x00000005
#define RGMII_TBI 0x00000006
#define RGMII_GMII 0x00000007
/* Speed Selection reg */
#define RGMII_SP2_100 0x00000002
#define RGMII_SP2_1000 0x00000004
#define RGMII_SP3_100 0x00000200
#define RGMII_SP3_1000 0x00000400
#define RGMII_MII2_SPDMASK 0x00000007
#define RGMII_MII3_SPDMASK 0x00000700
#define RGMII_MII2_100MB RGMII_SP2_100 & ~RGMII_SP2_1000
#define RGMII_MII2_1000MB RGMII_SP2_1000 & ~RGMII_SP2_100
#define RGMII_MII2_10MB ~(RGMII_SP2_100 | RGMII_SP2_1000)
#define RGMII_MII3_100MB RGMII_SP3_100 & ~RGMII_SP3_1000
#define RGMII_MII3_1000MB RGMII_SP3_1000 & ~RGMII_SP3_100
#define RGMII_MII3_10MB ~(RGMII_SP3_100 | RGMII_SP3_1000)
#define RTBI 0
#define RGMII 1
#define TBI 2
#define GMII 3
#endif /* _IBM_EMAC_RGMII_H_ */

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drivers/net/ibm_emac/ibm_emac_tah.h Normal file
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/*
* Defines for the IBM TAH
*
* Copyright 2004 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IBM_EMAC_TAH_H
#define _IBM_EMAC_TAH_H
/* TAH */
typedef struct tah_regs {
u32 tah_revid;
u32 pad[3];
u32 tah_mr;
u32 tah_ssr0;
u32 tah_ssr1;
u32 tah_ssr2;
u32 tah_ssr3;
u32 tah_ssr4;
u32 tah_ssr5;
u32 tah_tsr;
} tah_t;
/* TAH engine */
#define TAH_MR_CVR 0x80000000
#define TAH_MR_SR 0x40000000
#define TAH_MR_ST_256 0x01000000
#define TAH_MR_ST_512 0x02000000
#define TAH_MR_ST_768 0x03000000
#define TAH_MR_ST_1024 0x04000000
#define TAH_MR_ST_1280 0x05000000
#define TAH_MR_ST_1536 0x06000000
#define TAH_MR_TFS_16KB 0x00000000
#define TAH_MR_TFS_2KB 0x00200000
#define TAH_MR_TFS_4KB 0x00400000
#define TAH_MR_TFS_6KB 0x00600000
#define TAH_MR_TFS_8KB 0x00800000
#define TAH_MR_TFS_10KB 0x00a00000
#define TAH_MR_DTFP 0x00100000
#define TAH_MR_DIG 0x00080000
#endif /* _IBM_EMAC_TAH_H */

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drivers/net/ibm_emac/ibm_emac_zmii.h Normal file
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/*
* ocp_zmii.h
*
* Defines for the IBM ZMII bridge
*
* Armin Kuster akuster@mvista.com
* Dec, 2001
*
* Copyright 2001 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _IBM_EMAC_ZMII_H_
#define _IBM_EMAC_ZMII_H_
#include <linux/config.h>
/* ZMII bridge registers */
struct zmii_regs {
u32 fer; /* Function enable reg */
u32 ssr; /* Speed select reg */
u32 smiirs; /* SMII status reg */
};
#define ZMII_INPUTS 4
/* ZMII device */
struct ibm_ocp_zmii {
struct zmii_regs *base;
int mode[ZMII_INPUTS];
int users; /* number of EMACs using this ZMII bridge */
};
/* Fuctional Enable Reg */
#define ZMII_FER_MASK(x) (0xf0000000 >> (4*x))
#define ZMII_MDI0 0x80000000
#define ZMII_SMII0 0x40000000
#define ZMII_RMII0 0x20000000
#define ZMII_MII0 0x10000000
#define ZMII_MDI1 0x08000000
#define ZMII_SMII1 0x04000000
#define ZMII_RMII1 0x02000000
#define ZMII_MII1 0x01000000
#define ZMII_MDI2 0x00800000
#define ZMII_SMII2 0x00400000
#define ZMII_RMII2 0x00200000
#define ZMII_MII2 0x00100000
#define ZMII_MDI3 0x00080000
#define ZMII_SMII3 0x00040000
#define ZMII_RMII3 0x00020000
#define ZMII_MII3 0x00010000
/* Speed Selection reg */
#define ZMII_SCI0 0x40000000
#define ZMII_FSS0 0x20000000
#define ZMII_SP0 0x10000000
#define ZMII_SCI1 0x04000000
#define ZMII_FSS1 0x02000000
#define ZMII_SP1 0x01000000
#define ZMII_SCI2 0x00400000
#define ZMII_FSS2 0x00200000
#define ZMII_SP2 0x00100000
#define ZMII_SCI3 0x00040000
#define ZMII_FSS3 0x00020000
#define ZMII_SP3 0x00010000
#define ZMII_MII0_100MB ZMII_SP0
#define ZMII_MII0_10MB ~ZMII_SP0
#define ZMII_MII1_100MB ZMII_SP1
#define ZMII_MII1_10MB ~ZMII_SP1
#define ZMII_MII2_100MB ZMII_SP2
#define ZMII_MII2_10MB ~ZMII_SP2
#define ZMII_MII3_100MB ZMII_SP3
#define ZMII_MII3_10MB ~ZMII_SP3
/* SMII Status reg */
#define ZMII_STS0 0xFF000000 /* EMAC0 smii status mask */
#define ZMII_STS1 0x00FF0000 /* EMAC1 smii status mask */
#define SMII 0
#define RMII 1
#define MII 2
#define MDI 3
#endif /* _IBM_EMAC_ZMII_H_ */