Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
304
arch/mips/pci/pci.c
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304
arch/mips/pci/pci.c
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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/*
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* Indicate whether we respect the PCI setup left by the firmware.
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*
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* Make this long-lived so that we know when shutting down
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* whether we probed only or not.
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*/
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int pci_probe_only;
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#define PCI_ASSIGN_ALL_BUSSES 1
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unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
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/*
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* The PCI controller list.
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*/
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struct pci_controller *hose_head, **hose_tail = &hose_head;
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struct pci_controller *pci_isa_hose;
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unsigned long PCIBIOS_MIN_IO = 0x0000;
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unsigned long PCIBIOS_MIN_MEM = 0;
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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void
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pcibios_align_resource(void *data, struct resource *res,
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unsigned long size, unsigned long align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = dev->sysdata;
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unsigned long start = res->start;
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if (res->flags & IORESOURCE_IO) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
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start = PCIBIOS_MIN_IO + hose->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
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start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
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}
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res->start = start;
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}
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struct pci_controller * __init alloc_pci_controller(void)
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{
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return alloc_bootmem(sizeof(struct pci_controller));
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}
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void __init register_pci_controller(struct pci_controller *hose)
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{
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*hose_tail = hose;
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hose_tail = &hose->next;
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}
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/* Most MIPS systems have straight-forward swizzling needs. */
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static inline u8 bridge_swizzle(u8 pin, u8 slot)
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{
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return (((pin - 1) + slot) % 4) + 1;
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}
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static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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u8 pin = *pinp;
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while (dev->bus->parent) {
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pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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}
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*pinp = pin;
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/* The slot is the slot of the last bridge. */
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return PCI_SLOT(dev->devfn);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose;
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struct pci_bus *bus;
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int next_busno;
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int need_domain_info = 0;
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/* Scan all of the recorded PCI controllers. */
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for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
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if (request_resource(&iomem_resource, hose->mem_resource) < 0)
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goto out;
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if (request_resource(&ioport_resource, hose->io_resource) < 0)
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goto out_free_mem_resource;
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if (!hose->iommu)
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PCI_DMA_BUS_IS_PHYS = 1;
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bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
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hose->bus = bus;
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hose->need_domain_info = need_domain_info;
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next_busno = bus->subordinate + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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continue;
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out_free_mem_resource:
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release_resource(hose->mem_resource);
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out:
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printk(KERN_WARNING
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"Skipping PCI bus scan due to resource conflict\n");
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}
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if (!pci_probe_only)
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pci_assign_unassigned_resources();
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pci_fixup_irqs(common_swizzle, pcibios_map_irq);
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return 0;
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}
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subsys_initcall(pcibios_init);
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static int pcibios_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for(idx=0; idx<6; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (dev->resource[PCI_ROM_RESOURCE].start)
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cmd |= PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain crappy BIOSes forget to set it properly.
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*/
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unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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unsigned int pcibios_assign_all_busses(void)
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{
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return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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if ((err = pcibios_enable_resources(dev, mask)) < 0)
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return err;
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return pcibios_plat_dev_init(dev);
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}
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static void __init pcibios_fixup_device_resources(struct pci_dev *dev,
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struct pci_bus *bus)
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{
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/* Update device resources. */
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struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
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unsigned long offset = 0;
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!dev->resource[i].start)
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continue;
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if (dev->resource[i].flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (dev->resource[i].flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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dev->resource[i].start += offset;
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dev->resource[i].end += offset;
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}
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}
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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/* Propagate hose info into the subordinate devices. */
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struct pci_controller *hose = bus->sysdata;
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struct list_head *ln;
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struct pci_dev *dev = bus->self;
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if (!dev) {
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bus->resource[0] = hose->io_resource;
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bus->resource[1] = hose->mem_resource;
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} else if (pci_probe_only &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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pcibios_fixup_device_resources(dev, bus);
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}
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for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
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struct pci_dev *dev = pci_dev_b(ln);
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if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
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pcibios_fixup_device_resources(dev, bus);
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}
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}
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void __init
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pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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void __devinit
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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#endif
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char *pcibios_setup(char *str)
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{
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return str;
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}
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