Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
This commit is contained in:
Linus Torvalds
489
arch/mips/pci/pci-ip27.c
Normal file
489
arch/mips/pci/pci-ip27.c
Normal file
@@ -0,0 +1,489 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
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* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <asm/sn/arch.h>
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#include <asm/pci/bridge.h>
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#include <asm/paccess.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/sn0/hub.h>
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extern unsigned int allocate_irqno(void);
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/*
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* Max #PCI busses we can handle; ie, max #PCI bridges.
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*/
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#define MAX_PCI_BUSSES 40
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/*
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* Max #PCI devices (like scsi controllers) we handle on a bus.
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*/
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#define MAX_DEVICES_PER_PCIBUS 8
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/*
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* XXX: No kmalloc available when we do our crosstalk scan,
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* we should try to move it later in the boot process.
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*/
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static struct bridge_controller bridges[MAX_PCI_BUSSES];
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/*
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* Translate from irq to software PCI bus number and PCI slot.
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*/
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struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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/*
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* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
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* not really documented, so right now I can't write code which uses it.
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* Therefore we use type 0 accesses for now even though they won't work
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* correcly for PCI-to-PCI bridges.
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*
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* The function is complicated by the ultimate brokeness of the IOC3 chip
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* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
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* accesses and does only decode parts of it's address space.
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*/
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static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1)
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res = get_dbe(*value, (u8 *) addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *) addr);
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else
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res = get_dbe(*value, (u32 *) addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask;
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int res;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1)
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res = get_dbe(*value, (u8 *) addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *) addr);
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else
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res = get_dbe(*value, (u32 *) addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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if (bus->number > 0)
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return pci_conf1_read_config(bus, devfn, where, size, value);
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return pci_conf0_read_config(bus, devfn, where, size, value);
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}
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static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask, smask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1) {
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res = put_dbe(value, (u8 *) addr);
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} else if (size == 2) {
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res = put_dbe(value, (u16 *) addr);
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} else {
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res = put_dbe(value, (u32 *) addr);
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}
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to touch the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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smask = mask << shift;
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cf = (cf & ~smask) | ((value & mask) << shift);
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if (put_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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int busno = bus->number;
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volatile void *addr;
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u32 cf, shift, mask, smask;
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int res;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1) {
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res = put_dbe(value, (u8 *) addr);
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} else if (size == 2) {
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res = put_dbe(value, (u16 *) addr);
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} else {
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res = put_dbe(value, (u32 *) addr);
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}
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
|
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return PCIBIOS_SUCCESSFUL;
|
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|
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oh_my_gawd:
|
||||
|
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/*
|
||||
* IOC3 is fucked fucked beyond believe ... Don't even give the
|
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* generic PCI code a chance to touch the wrong register.
|
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
|
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|
||||
/*
|
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* IOC3 is fucked fucked beyond believe ... Don't try to access
|
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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|
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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||||
mask = (0xffffffffU >> ((4 - size) << 3));
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||||
smask = mask << shift;
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|
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cf = (cf & ~smask) | ((value & mask) << shift);
|
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if (put_dbe(cf, (u32 *) addr))
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||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
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return PCIBIOS_SUCCESSFUL;
|
||||
}
|
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static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
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int where, int size, u32 value)
|
||||
{
|
||||
if (bus->number > 0)
|
||||
return pci_conf1_write_config(bus, devfn, where, size, value);
|
||||
|
||||
return pci_conf0_write_config(bus, devfn, where, size, value);
|
||||
}
|
||||
|
||||
static struct pci_ops bridge_pci_ops = {
|
||||
.read = pci_read_config,
|
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.write = pci_write_config,
|
||||
};
|
||||
|
||||
int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
|
||||
{
|
||||
unsigned long offset = NODE_OFFSET(nasid);
|
||||
struct bridge_controller *bc;
|
||||
static int num_bridges = 0;
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||||
bridge_t *bridge;
|
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int slot;
|
||||
|
||||
printk("a bridge\n");
|
||||
|
||||
/* XXX: kludge alert.. */
|
||||
if (!num_bridges)
|
||||
ioport_resource.end = ~0UL;
|
||||
|
||||
bc = &bridges[num_bridges];
|
||||
|
||||
bc->pc.pci_ops = &bridge_pci_ops;
|
||||
bc->pc.mem_resource = &bc->mem;
|
||||
bc->pc.io_resource = &bc->io;
|
||||
|
||||
bc->pc.index = num_bridges;
|
||||
|
||||
bc->mem.name = "Bridge PCI MEM";
|
||||
bc->pc.mem_offset = offset;
|
||||
bc->mem.start = 0;
|
||||
bc->mem.end = ~0UL;
|
||||
bc->mem.flags = IORESOURCE_MEM;
|
||||
|
||||
bc->io.name = "Bridge IO MEM";
|
||||
bc->pc.io_offset = offset;
|
||||
bc->io.start = 0UL;
|
||||
bc->io.end = ~0UL;
|
||||
bc->io.flags = IORESOURCE_IO;
|
||||
|
||||
bc->irq_cpu = smp_processor_id();
|
||||
bc->widget_id = widget_id;
|
||||
bc->nasid = nasid;
|
||||
|
||||
bc->baddr = (u64)masterwid << 60;
|
||||
bc->baddr |= (1UL << 56); /* Barrier set */
|
||||
|
||||
/*
|
||||
* point to this bridge
|
||||
*/
|
||||
bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
|
||||
|
||||
/*
|
||||
* Clear all pending interrupts.
|
||||
*/
|
||||
bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
|
||||
|
||||
/*
|
||||
* Until otherwise set up, assume all interrupts are from slot 0
|
||||
*/
|
||||
bridge->b_int_device = 0x0;
|
||||
|
||||
/*
|
||||
* swap pio's to pci mem and io space (big windows)
|
||||
*/
|
||||
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
|
||||
BRIDGE_CTRL_MEM_SWAP;
|
||||
|
||||
/*
|
||||
* Hmm... IRIX sets additional bits in the address which
|
||||
* are documented as reserved in the bridge docs.
|
||||
*/
|
||||
bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
|
||||
bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/
|
||||
bridge->b_dir_map = (masterwid << 20); /* DMA */
|
||||
bridge->b_int_enable = 0;
|
||||
|
||||
for (slot = 0; slot < 8; slot ++) {
|
||||
bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
|
||||
bc->pci_int[slot] = -1;
|
||||
}
|
||||
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
|
||||
|
||||
bc->base = bridge;
|
||||
|
||||
register_pci_controller(&bc->pc);
|
||||
|
||||
num_bridges++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* All observed requests have pin == 1. We could have a global here, that
|
||||
* gets incremented and returned every time - unfortunately, pci_map_irq
|
||||
* may be called on the same device over and over, and need to return the
|
||||
* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
|
||||
*
|
||||
* A given PCI device, in general, should be able to intr any of the cpus
|
||||
* on any one of the hubs connected to its xbow.
|
||||
*/
|
||||
int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
|
||||
int irq = bc->pci_int[slot];
|
||||
|
||||
if (irq == -1) {
|
||||
irq = bc->pci_int[slot] = request_bridge_irq(bc);
|
||||
if (irq < 0)
|
||||
panic("Can't allocate interrupt for PCI device %s\n",
|
||||
pci_name(dev));
|
||||
}
|
||||
|
||||
irq_to_bridge[irq] = bc;
|
||||
irq_to_slot[irq] = slot;
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
|
||||
* to find the slot number in sense of the bridge device register.
|
||||
* XXX This also means multiple devices might rely on conflicting bridge
|
||||
* settings.
|
||||
*/
|
||||
|
||||
static inline void pci_disable_swapping(struct pci_dev *dev)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
|
||||
bridge_t *bridge = bc->base;
|
||||
int slot = PCI_SLOT(dev->devfn);
|
||||
|
||||
/* Turn off byte swapping */
|
||||
bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
|
||||
bridge->b_widget.w_tflush; /* Flush */
|
||||
}
|
||||
|
||||
static inline void pci_enable_swapping(struct pci_dev *dev)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
|
||||
bridge_t *bridge = bc->base;
|
||||
int slot = PCI_SLOT(dev->devfn);
|
||||
|
||||
/* Turn on byte swapping */
|
||||
bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
|
||||
bridge->b_widget.w_tflush; /* Flush */
|
||||
}
|
||||
|
||||
static void __init pci_fixup_ioc3(struct pci_dev *d)
|
||||
{
|
||||
pci_disable_swapping(d);
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
|
||||
pci_fixup_ioc3);
|
||||
Reference in New Issue
Block a user