Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
这个提交包含在：
Linus Torvalds
@@ -0,0 +1,6 @@
|
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#
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# Makefile for common code of gt64120-based boards.
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#
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obj-y += time.o
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obj-$(CONFIG_PCI) += pci.o
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147
arch/mips/gt64120/common/pci.c
普通文件
147
arch/mips/gt64120/common/pci.c
普通文件
@@ -0,0 +1,147 @@
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/*
|
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* BRIEF MODULE DESCRIPTION
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* Galileo Evaluation Boards PCI support.
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*
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* The general-purpose functions to read/write and configure the GT64120A's
|
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* PCI registers (function names start with pci0 or pci1) are either direct
|
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* copies of functions written by Galileo Technology, or are modifications
|
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* of their functions to work with Linux 2.4 vs Linux 2.2. These functions
|
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* are Copyright - Galileo Technology.
|
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*
|
||||
* Other functions are derived from other MIPS PCI implementations, or were
|
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* written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/gt64120.h>
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#define SELF 0
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/*
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* pciXReadConfigReg - Read from a PCI configuration register
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* - Make sure the GT is configured as a master before
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* reading from another device on the PCI.
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* - The function takes care of Big/Little endian conversion.
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* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
|
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* spec)
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* pciDevNum: The device number needs to be addressed.
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* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
|
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* cause register to make sure the data is valid
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*
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* Configuration Address 0xCF8:
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*
|
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
|
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* |congif|Reserved| Bus |Device|Function|Register|00|
|
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* |Enable| |Number|Number| Number | Number | | <=field Name
|
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*
|
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*/
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static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
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{
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unsigned int DataForRegCf8;
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unsigned int data;
|
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|
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DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
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(PCI_FUNC(device->devfn) << 8) |
|
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(offset & ~0x3)) | 0x80000000;
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GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
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|
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/*
|
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* The casual observer might wonder why the READ is duplicated here,
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* rather than immediately following the WRITE, and just have the swap
|
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* in the "if". That's because there is a latency problem with trying
|
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* to read immediately after setting up the address register. The "if"
|
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* check gives enough time for the address to stabilize, so the READ
|
||||
* can work.
|
||||
*/
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if (PCI_SLOT(device->devfn) == SELF) /* This board */
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return GT_READ(GT_PCI0_CFGDATA_OFS);
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else /* PCI is little endian so swap the Data. */
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return __GT_READ(GT_PCI0_CFGDATA_OFS);
|
||||
}
|
||||
|
||||
/*
|
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* pciXWriteConfigReg - Write to a PCI configuration register
|
||||
* - Make sure the GT is configured as a master before
|
||||
* writingto another device on the PCI.
|
||||
* - The function takes care of Big/Little endian conversion.
|
||||
* Inputs: unsigned int regOffset: The register offset as it apears in the
|
||||
* GT spec
|
||||
* (or any other PCI device spec)
|
||||
* pciDevNum: The device number needs to be addressed.
|
||||
*
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||||
* Configuration Address 0xCF8:
|
||||
*
|
||||
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
|
||||
* |congif|Reserved| Bus |Device|Function|Register|00|
|
||||
* |Enable| |Number|Number| Number | Number | | <=field Name
|
||||
*
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||||
*/
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||||
static void pci0WriteConfigReg(unsigned int offset,
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||||
struct pci_dev *device, unsigned int data)
|
||||
{
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||||
unsigned int DataForRegCf8;
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||||
|
||||
DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
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||||
(PCI_FUNC(device->devfn) << 8) |
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||||
(offset & ~0x3)) | 0x80000000;
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GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
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||||
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if (PCI_SLOT(device->devfn) == SELF) /* This board */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
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||||
else /* configuration Transaction over the pci. */
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__GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
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}
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||||
|
||||
extern struct pci_ops gt64120_pci_ops;
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||||
void __init pcibios_init(void)
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{
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||||
u32 tmp;
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struct pci_dev controller;
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controller.devfn = SELF;
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||||
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tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
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tmp = GT_READ(GT_PCI0_BARE_OFS);
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/*
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* You have to enable bus mastering to configure any other
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* card on the bus.
|
||||
*/
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||||
tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
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tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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||||
pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
|
||||
|
||||
/*
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||||
* Reset PCI I/O and PCI MEM values to ones supported by EVM.
|
||||
*/
|
||||
ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
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iomem_resource.start = GT_PCI_MEM_BASE;
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||||
iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1;
|
||||
|
||||
pci_scan_bus(0, >64120_pci_ops, NULL);
|
||||
}
|
||||
100
arch/mips/gt64120/common/time.c
普通文件
100
arch/mips/gt64120/common/time.c
普通文件
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Galileo Technology chip interrupt handler
|
||||
*/
|
||||
#include <linux/interrupt.h>
|
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#include <linux/kernel.h>
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#include <linux/config.h>
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||||
#include <linux/sched.h>
|
||||
#include <linux/kernel_stat.h>
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||||
#include <asm/ptrace.h>
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||||
#include <asm/gt64120.h>
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||||
|
||||
/*
|
||||
* These are interrupt handlers for the GT on-chip interrupts. They all come
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||||
* in to the MIPS on a single interrupt line, and have to be handled and ack'ed
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* differently than other MIPS interrupts.
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||||
*/
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||||
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||||
static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
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||||
unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
|
||||
int handled = 0;
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||||
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||||
irq_src = GT_READ(GT_INTRCAUSE_OFS);
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irq_src_mask = GT_READ(GT_INTRMASK_OFS);
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int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
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||||
int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
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||||
irq_src = irq_src & irq_src_mask;
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int_high_src = int_high_src & int_high_src_mask;
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||||
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if (irq_src & 0x00000800) { /* Check for timer interrupt */
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handled = 1;
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irq_src &= ~0x00000800;
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do_timer(regs);
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||||
#ifndef CONFIG_SMP
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update_process_times(user_mode(regs));
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||||
#endif
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||||
}
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||||
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||||
GT_WRITE(GT_INTRCAUSE_OFS, 0);
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||||
GT_WRITE(GT_HINTRCAUSE_OFS, 0);
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||||
}
|
||||
|
||||
/*
|
||||
* Initializes timer using galileo's built in timer.
|
||||
*/
|
||||
#ifdef CONFIG_SYSCLK_100
|
||||
#define Sys_clock (100 * 1000000) // 100 MHz
|
||||
#endif
|
||||
#ifdef CONFIG_SYSCLK_83
|
||||
#define Sys_clock (83.333 * 1000000) // 83.333 MHz
|
||||
#endif
|
||||
#ifdef CONFIG_SYSCLK_75
|
||||
#define Sys_clock (75 * 1000000) // 75 MHz
|
||||
#endif
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||||
|
||||
/*
|
||||
* This will ignore the standard MIPS timer interrupt handler that is passed in
|
||||
* as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
|
||||
* handling.
|
||||
*/
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||||
void gt64120_time_init(void)
|
||||
{
|
||||
static struct irqaction timer;
|
||||
|
||||
/* Disable timer first */
|
||||
GT_WRITE(GT_TC_CONTROL_OFS, 0);
|
||||
/* Load timer value for 100 Hz */
|
||||
GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
|
||||
|
||||
/*
|
||||
* Create the IRQ structure entry for the timer. Since we're too early
|
||||
* in the boot process to use the "request_irq()" call, we'll hard-code
|
||||
* the values to the correct interrupt line.
|
||||
*/
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||||
timer.handler = gt64120_irq;
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||||
timer.flags = SA_SHIRQ | SA_INTERRUPT;
|
||||
timer.name = "timer";
|
||||
timer.dev_id = NULL;
|
||||
timer.next = NULL;
|
||||
timer.mask = CPU_MASK_NONE;
|
||||
irq_desc[GT_TIMER].action = &timer;
|
||||
|
||||
enable_irq(GT_TIMER);
|
||||
|
||||
/* Enable timer ints */
|
||||
GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
|
||||
/* clear Cause register first */
|
||||
GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
|
||||
/* Unmask timer int */
|
||||
GT_WRITE(GT_INTRMASK_OFS, 0x800);
|
||||
/* Clear High int register */
|
||||
GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
|
||||
/* Mask All interrupts at High cause interrupt */
|
||||
GT_WRITE(GT_HINTRMASK_OFS, 0x0);
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
#
|
||||
# Copyright 2000 RidgeRun, Inc.
|
||||
# Author: RidgeRun, Inc.
|
||||
# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
#
|
||||
# Makefile for the Galileo EV64120 board.
|
||||
#
|
||||
|
||||
obj-y += int-handler.o irq.o promcon.o reset.o serialGT.o setup.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* int-handler.S
|
||||
*
|
||||
* Based on the cobalt handler.
|
||||
*/
|
||||
#include <asm/asm.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
||||
/*
|
||||
* galileo_handle_int -
|
||||
* We check for the timer first, then check PCI ints A and D.
|
||||
* Then check for serial IRQ and fall through.
|
||||
*/
|
||||
.align 5
|
||||
.set reorder
|
||||
.set noat
|
||||
NESTED(galileo_handle_int, PT_SIZE, sp)
|
||||
SAVE_ALL
|
||||
CLI
|
||||
.set at
|
||||
mfc0 t0,CP0_CAUSE
|
||||
mfc0 t2,CP0_STATUS
|
||||
|
||||
and t0,t2
|
||||
|
||||
andi t1,t0,STATUSF_IP4 /* int2 hardware line (timer) */
|
||||
bnez t1,ll_gt64120_irq
|
||||
andi t1,t0,STATUSF_IP2 /* int0 hardware line */
|
||||
bnez t1,ll_pci_intA
|
||||
andi t1,t0,STATUSF_IP5 /* int3 hardware line */
|
||||
bnez t1,ll_pci_intD
|
||||
andi t1,t0,STATUSF_IP6 /* int4 hardware line */
|
||||
bnez t1,ll_serial_irq
|
||||
andi t1,t0,STATUSF_IP7 /* compare int */
|
||||
bnez t1,ll_compare_irq
|
||||
nop
|
||||
|
||||
/* wrong alarm or masked ... */
|
||||
j spurious_interrupt
|
||||
nop
|
||||
END(galileo_handle_int)
|
||||
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_gt64120_irq:
|
||||
li a0,4
|
||||
move a1,sp
|
||||
jal do_IRQ
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_compare_irq:
|
||||
li a0,7
|
||||
move a1,sp
|
||||
jal do_IRQ
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_pci_intA:
|
||||
move a0,sp
|
||||
jal pci_intA
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
#if 0
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_pci_intB:
|
||||
move a0,sp
|
||||
jal pci_intB
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_pci_intC:
|
||||
move a0,sp
|
||||
jal pci_intC
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
#endif
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_pci_intD:
|
||||
move a0,sp
|
||||
jal pci_intD
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
.align 5
|
||||
.set reorder
|
||||
ll_serial_irq:
|
||||
li a0,6
|
||||
move a1,sp
|
||||
jal do_IRQ
|
||||
nop
|
||||
j ret_from_irq
|
||||
nop
|
||||
145
arch/mips/gt64120/ev64120/irq.c
普通文件
145
arch/mips/gt64120/ev64120/irq.c
普通文件
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Code to handle irqs on GT64120A boards
|
||||
* Derived from mips/orion and Cort <cort@fsmlabs.com>
|
||||
*
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
asmlinkage inline void pci_intA(struct pt_regs *regs)
|
||||
{
|
||||
do_IRQ(GT_INTA, regs);
|
||||
}
|
||||
|
||||
asmlinkage inline void pci_intD(struct pt_regs *regs)
|
||||
{
|
||||
do_IRQ(GT_INTD, regs);
|
||||
}
|
||||
|
||||
static void disable_ev64120_irq(unsigned int irq_nr)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
|
||||
clear_c0_status(9 << 10);
|
||||
} else {
|
||||
clear_c0_status(1 << (irq_nr + 8));
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void enable_ev64120_irq(unsigned int irq_nr)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
|
||||
set_c0_status(9 << 10);
|
||||
else
|
||||
set_c0_status(1 << (irq_nr + 8));
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static unsigned int startup_ev64120_irq(unsigned int irq)
|
||||
{
|
||||
enable_ev64120_irq(irq);
|
||||
return 0; /* Never anything pending */
|
||||
}
|
||||
|
||||
#define shutdown_ev64120_irq disable_ev64120_irq
|
||||
#define mask_and_ack_ev64120_irq disable_ev64120_irq
|
||||
|
||||
static void end_ev64120_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_ev64120_irq(irq);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type ev64120_irq_type = {
|
||||
.typename = "EV64120",
|
||||
.startup = startup_ev64120_irq,
|
||||
.shutdown = shutdown_ev64120_irq,
|
||||
.enable = enable_ev64120_irq,
|
||||
.disable = disable_ev64120_irq,
|
||||
.ack = mask_and_ack_ev64120_irq,
|
||||
.end = end_ev64120_irq,
|
||||
.set_affinity = NULL
|
||||
};
|
||||
|
||||
void gt64120_irq_setup(void)
|
||||
{
|
||||
extern asmlinkage void galileo_handle_int(void);
|
||||
|
||||
/*
|
||||
* Clear all of the interrupts while we change the able around a bit.
|
||||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
|
||||
/* Sets the exception_handler array. */
|
||||
set_except_vector(0, galileo_handle_int);
|
||||
|
||||
local_irq_disable();
|
||||
|
||||
/*
|
||||
* Enable timer. Other interrupts will be enabled as they are
|
||||
* registered.
|
||||
*/
|
||||
set_c0_status(IE_IRQ2);
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Let's initialize our IRQ descriptors */
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
irq_desc[i].status = 0;
|
||||
irq_desc[i].handler = &no_irq_type;
|
||||
irq_desc[i].action = NULL;
|
||||
irq_desc[i].depth = 0;
|
||||
spin_lock_init(&irq_desc[i].lock);
|
||||
}
|
||||
|
||||
gt64120_irq_setup();
|
||||
}
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Wrap-around code for a console using the
|
||||
* SGI PROM io-routines.
|
||||
*
|
||||
* Copyright (c) 1999 Ulf Carlsson
|
||||
*
|
||||
* Derived from DECstation promcon.c
|
||||
* Copyright (c) 1998 Harald Koerfgen
|
||||
*/
|
||||
#include <linux/tty.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
static void prom_console_write(struct console *co, const char *s,
|
||||
unsigned count)
|
||||
{
|
||||
extern int CONSOLE_CHANNEL; // The default serial port
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
if (*s == 10)
|
||||
serial_putc(CONSOLE_CHANNEL, 13);
|
||||
serial_putc(CONSOLE_CHANNEL, *s++);
|
||||
}
|
||||
}
|
||||
|
||||
int prom_getchar(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct console sercons = {
|
||||
.name = "ttyS",
|
||||
.write = prom_console_write,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Register console.
|
||||
*/
|
||||
|
||||
static int gal_serial_console_init(void)
|
||||
{
|
||||
// serial_init();
|
||||
//serial_set(115200);
|
||||
|
||||
register_console(&sercons);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(gal_serial_console_init);
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1997 Ralf Baechle
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
void galileo_machine_restart(char *command)
|
||||
{
|
||||
*(volatile char *) 0xbc000000 = 0x0f;
|
||||
/*
|
||||
* Ouch, we're still alive ... This time we take the silver bullet ...
|
||||
* ... and find that we leave the hardware in a state in which the
|
||||
* kernel in the flush locks up somewhen during of after the PCI
|
||||
* detection stuff.
|
||||
*/
|
||||
set_c0_status(ST0_BEV | ST0_ERL);
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
|
||||
flush_cache_all();
|
||||
write_c0_wired(0);
|
||||
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
||||
}
|
||||
|
||||
void galileo_machine_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
|
||||
}
|
||||
|
||||
void galileo_machine_power_off(void)
|
||||
{
|
||||
galileo_machine_halt();
|
||||
}
|
||||
212
arch/mips/gt64120/ev64120/serialGT.c
普通文件
212
arch/mips/gt64120/ev64120/serialGT.c
普通文件
@@ -0,0 +1,212 @@
|
||||
/*
|
||||
* serialGT.c
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Low Level Serial Port control for use
|
||||
* with the Galileo EVB64120A MIPS eval board and
|
||||
* its on board two channel 16552 Uart.
|
||||
*
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
// Note:
|
||||
// Serial CHANNELS - 0 is the bottom connector of evb64120A.
|
||||
// (The one that maps to the "B" channel of the
|
||||
// board's uart)
|
||||
// 1 is the top connector of evb64120A.
|
||||
// (The one that maps to the "A" channel of the
|
||||
// board's uart)
|
||||
int DEBUG_CHANNEL = 0; // See Note Above
|
||||
int CONSOLE_CHANNEL = 1; // See Note Above
|
||||
|
||||
#define DUART 0xBD000000 /* Base address of Uart. */
|
||||
#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA
|
||||
register set of the 16552 Uart device.
|
||||
DUART+0 gets you to the ChanB register set.
|
||||
*/
|
||||
#define DUART_DELTA 0x4
|
||||
#define FIFO_ENABLE 0x07
|
||||
#define INT_ENABLE 0x04 /* default interrupt mask */
|
||||
|
||||
#define RBR 0x00
|
||||
#define THR 0x00
|
||||
#define DLL 0x00
|
||||
#define IER 0x01
|
||||
#define DLM 0x01
|
||||
#define IIR 0x02
|
||||
#define FCR 0x02
|
||||
#define LCR 0x03
|
||||
#define MCR 0x04
|
||||
#define LSR 0x05
|
||||
#define MSR 0x06
|
||||
#define SCR 0x07
|
||||
|
||||
#define LCR_DLAB 0x80
|
||||
#define XTAL 1843200
|
||||
#define LSR_THRE 0x20
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_DR 0x01
|
||||
#define MCR_LOOP 0x10
|
||||
#define ACCESS_DELAY 0x10000
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
int inreg(int channel, int reg)
|
||||
{
|
||||
int val;
|
||||
val =
|
||||
*((volatile unsigned char *) DUART +
|
||||
(channel * CHANNELOFFSET) + (reg * DUART_DELTA));
|
||||
return val;
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
void outreg(int channel, int reg, unsigned char val)
|
||||
{
|
||||
*((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
|
||||
+ (reg * DUART_DELTA)) = val;
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Initialize the device driver.
|
||||
******************************/
|
||||
void serial_init(int channel)
|
||||
{
|
||||
/*
|
||||
* Configure active port, (CHANNELOFFSET already set.)
|
||||
*
|
||||
* Set 8 bits, 1 stop bit, no parity.
|
||||
*
|
||||
* LCR<7> 0 divisor latch access bit
|
||||
* LCR<6> 0 break control (1=send break)
|
||||
* LCR<5> 0 stick parity (0=space, 1=mark)
|
||||
* LCR<4> 0 parity even (0=odd, 1=even)
|
||||
* LCR<3> 0 parity enable (1=enabled)
|
||||
* LCR<2> 0 # stop bits (0=1, 1=1.5)
|
||||
* LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
|
||||
*/
|
||||
outreg(channel, LCR, 0x3);
|
||||
|
||||
outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */
|
||||
|
||||
outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Set the baud rate.
|
||||
******************************/
|
||||
void serial_set(int channel, unsigned long baud)
|
||||
{
|
||||
unsigned char sav_lcr;
|
||||
|
||||
/*
|
||||
* Enable access to the divisor latches by setting DLAB in LCR.
|
||||
*
|
||||
*/
|
||||
sav_lcr = inreg(channel, LCR);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Set baud rate
|
||||
*/
|
||||
outreg(channel, LCR, LCR_DLAB | sav_lcr);
|
||||
// outreg(DLL,(XTAL/(16*2*(baud))-2));
|
||||
outreg(channel, DLL, XTAL / (16 * baud));
|
||||
// outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
|
||||
outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
|
||||
#else
|
||||
/*
|
||||
* Note: Set baud rate, hardcoded here for rate of 115200
|
||||
* since became unsure of above "buad rate" algorithm (??).
|
||||
*/
|
||||
outreg(channel, LCR, 0x83);
|
||||
outreg(channel, DLM, 0x00); // See note above
|
||||
outreg(channel, DLL, 0x02); // See note above.
|
||||
outreg(channel, LCR, 0x03);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Restore line control register
|
||||
*/
|
||||
outreg(channel, LCR, sav_lcr);
|
||||
}
|
||||
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Transmit a character.
|
||||
******************************/
|
||||
void serial_putc(int channel, int c)
|
||||
{
|
||||
while ((inreg(channel, LSR) & LSR_THRE) == 0);
|
||||
outreg(channel, THR, c);
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Read a received character if one is
|
||||
available. Return -1 otherwise.
|
||||
******************************/
|
||||
int serial_getc(int channel)
|
||||
{
|
||||
if (inreg(channel, LSR) & LSR_DR) {
|
||||
return inreg(channel, RBR);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Used by embedded gdb client. (example; gdb-stub.c)
|
||||
******************************/
|
||||
char getDebugChar()
|
||||
{
|
||||
int val;
|
||||
while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in.
|
||||
return (char) val;
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
Used by embedded gdb target. (example; gdb-stub.c)
|
||||
******************************/
|
||||
void putDebugChar(char c)
|
||||
{
|
||||
serial_putc(DEBUG_CHANNEL, (int) c);
|
||||
}
|
||||
103
arch/mips/gt64120/ev64120/setup.c
普通文件
103
arch/mips/gt64120/ev64120/setup.c
普通文件
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/timex.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
unsigned long gt64120_base = KSEG1ADDR(0x14000000);
|
||||
|
||||
/* These functions are used for rebooting or halting the machine*/
|
||||
extern void galileo_machine_restart(char *command);
|
||||
extern void galileo_machine_halt(void);
|
||||
extern void galileo_machine_power_off(void);
|
||||
/*
|
||||
*This structure holds pointers to the pci configuration space accesses
|
||||
*and interrupts allocating routine for device over the PCI
|
||||
*/
|
||||
extern struct pci_ops galileo_pci_ops;
|
||||
|
||||
unsigned long __init prom_free_prom_memory(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes basic routines and structures pointers, memory size (as
|
||||
* given by the bios and saves the command line.
|
||||
*/
|
||||
extern void gt64120_time_init(void);
|
||||
|
||||
static void __init ev64120_setup(void)
|
||||
{
|
||||
_machine_restart = galileo_machine_restart;
|
||||
_machine_halt = galileo_machine_halt;
|
||||
_machine_power_off = galileo_machine_power_off;
|
||||
|
||||
board_time_init = gt64120_time_init;
|
||||
set_io_port_base(KSEG1);
|
||||
}
|
||||
|
||||
early_initcall(ev64120_setup);
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Galileo EV64120A";
|
||||
}
|
||||
|
||||
/*
|
||||
* Kernel arguments passed by the firmware
|
||||
*
|
||||
* $a0 - nothing
|
||||
* $a1 - holds a pointer to the eprom parameters
|
||||
* $a2 - nothing
|
||||
*/
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
mips_machgroup = MACH_GROUP_GALILEO;
|
||||
mips_machtype = MACH_EV64120A;
|
||||
|
||||
add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# Makefile for Momentum's Ocelot board.
|
||||
#
|
||||
|
||||
obj-y += int-handler.o irq.o prom.o reset.o setup.o
|
||||
|
||||
obj-$(CONFIG_KGDB) += dbg_io.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
||||
@@ -0,0 +1,126 @@
|
||||
#include <linux/config.h>
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
|
||||
#include <asm/serial.h> /* For the serial port location and base baud */
|
||||
|
||||
/* --- CONFIG --- */
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned int uint32;
|
||||
|
||||
/* --- END OF CONFIG --- */
|
||||
|
||||
#define UART16550_BAUD_2400 2400
|
||||
#define UART16550_BAUD_4800 4800
|
||||
#define UART16550_BAUD_9600 9600
|
||||
#define UART16550_BAUD_19200 19200
|
||||
#define UART16550_BAUD_38400 38400
|
||||
#define UART16550_BAUD_57600 57600
|
||||
#define UART16550_BAUD_115200 115200
|
||||
|
||||
#define UART16550_PARITY_NONE 0
|
||||
#define UART16550_PARITY_ODD 0x08
|
||||
#define UART16550_PARITY_EVEN 0x18
|
||||
#define UART16550_PARITY_MARK 0x28
|
||||
#define UART16550_PARITY_SPACE 0x38
|
||||
|
||||
#define UART16550_DATA_5BIT 0x0
|
||||
#define UART16550_DATA_6BIT 0x1
|
||||
#define UART16550_DATA_7BIT 0x2
|
||||
#define UART16550_DATA_8BIT 0x3
|
||||
|
||||
#define UART16550_STOP_1BIT 0x0
|
||||
#define UART16550_STOP_2BIT 0x4
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
|
||||
/* === CONFIG === */
|
||||
|
||||
/* [jsun] we use the second serial port for kdb */
|
||||
#define BASE OCELOT_SERIAL1_BASE
|
||||
#define MAX_BAUD OCELOT_BASE_BAUD
|
||||
|
||||
/* === END OF CONFIG === */
|
||||
|
||||
#define REG_OFFSET 4
|
||||
|
||||
/* register offset */
|
||||
#define OFS_RCV_BUFFER 0
|
||||
#define OFS_TRANS_HOLD 0
|
||||
#define OFS_SEND_BUFFER 0
|
||||
#define OFS_INTR_ENABLE (1*REG_OFFSET)
|
||||
#define OFS_INTR_ID (2*REG_OFFSET)
|
||||
#define OFS_DATA_FORMAT (3*REG_OFFSET)
|
||||
#define OFS_LINE_CONTROL (3*REG_OFFSET)
|
||||
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
|
||||
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
|
||||
#define OFS_LINE_STATUS (5*REG_OFFSET)
|
||||
#define OFS_MODEM_STATUS (6*REG_OFFSET)
|
||||
#define OFS_RS232_INPUT (6*REG_OFFSET)
|
||||
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
|
||||
|
||||
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
|
||||
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
|
||||
|
||||
|
||||
/* memory-mapped read/write of the port */
|
||||
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
|
||||
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
|
||||
|
||||
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
|
||||
{
|
||||
/* disable interrupts */
|
||||
UART16550_WRITE(OFS_INTR_ENABLE, 0);
|
||||
|
||||
/* set up buad rate */
|
||||
{
|
||||
uint32 divisor;
|
||||
|
||||
/* set DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
|
||||
|
||||
/* set divisor */
|
||||
divisor = MAX_BAUD / baud;
|
||||
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
|
||||
|
||||
/* clear DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
|
||||
}
|
||||
|
||||
/* set data format */
|
||||
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
|
||||
}
|
||||
|
||||
static int remoteDebugInitialized = 0;
|
||||
|
||||
uint8 getDebugChar(void)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
|
||||
return UART16550_READ(OFS_RCV_BUFFER);
|
||||
}
|
||||
|
||||
|
||||
int putDebugChar(uint8 byte)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
|
||||
UART16550_WRITE(OFS_SEND_BUFFER, byte);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* First-level interrupt dispatcher for ocelot board.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#include <asm/asm.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
||||
/*
|
||||
* first level interrupt dispatcher for ocelot board -
|
||||
* We check for the timer first, then check PCI ints A and D.
|
||||
* Then check for serial IRQ and fall through.
|
||||
*/
|
||||
.align 5
|
||||
NESTED(ocelot_handle_int, PT_SIZE, sp)
|
||||
SAVE_ALL
|
||||
CLI
|
||||
.set at
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t2, CP0_STATUS
|
||||
|
||||
and t0, t2
|
||||
|
||||
andi t1, t0, STATUSF_IP2 /* int0 hardware line */
|
||||
bnez t1, ll_pri_enet_irq
|
||||
andi t1, t0, STATUSF_IP3 /* int1 hardware line */
|
||||
bnez t1, ll_sec_enet_irq
|
||||
andi t1, t0, STATUSF_IP4 /* int2 hardware line */
|
||||
bnez t1, ll_uart1_irq
|
||||
andi t1, t0, STATUSF_IP5 /* int3 hardware line */
|
||||
bnez t1, ll_cpci_irq
|
||||
andi t1, t0, STATUSF_IP6 /* int4 hardware line */
|
||||
bnez t1, ll_galileo_irq
|
||||
andi t1, t0, STATUSF_IP7 /* cpu timer */
|
||||
bnez t1, ll_cputimer_irq
|
||||
|
||||
/* now look at the extended interrupts */
|
||||
mfc0 t0, CP0_CAUSE
|
||||
cfc0 t1, CP0_S1_INTCONTROL
|
||||
|
||||
/* shift the mask 8 bits left to line up the bits */
|
||||
sll t2, t1, 8
|
||||
|
||||
and t0, t2
|
||||
srl t0, t0, 16
|
||||
|
||||
andi t1, t0, STATUSF_IP8 /* int6 hardware line */
|
||||
bnez t1, ll_pmc1_irq
|
||||
andi t1, t0, STATUSF_IP9 /* int7 hardware line */
|
||||
bnez t1, ll_pmc2_irq
|
||||
andi t1, t0, STATUSF_IP10 /* int8 hardware line */
|
||||
bnez t1, ll_cpci_abcd_irq
|
||||
andi t1, t0, STATUSF_IP11 /* int9 hardware line */
|
||||
bnez t1, ll_uart2_irq
|
||||
|
||||
.set reorder
|
||||
|
||||
/* wrong alarm or masked ... */
|
||||
j spurious_interrupt
|
||||
nop
|
||||
END(ocelot_handle_int)
|
||||
|
||||
.align 5
|
||||
ll_pri_enet_irq:
|
||||
li a0, 2
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_sec_enet_irq:
|
||||
li a0, 3
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_uart1_irq:
|
||||
li a0, 4
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_cpci_irq:
|
||||
li a0, 5
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_galileo_irq:
|
||||
li a0, 6
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_cputimer_irq:
|
||||
li a0, 7
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_pmc1_irq:
|
||||
li a0, 8
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_pmc2_irq:
|
||||
li a0, 9
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_cpci_abcd_irq:
|
||||
li a0, 10
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
ll_uart2_irq:
|
||||
li a0, 11
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
||||
* Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
extern asmlinkage void ocelot_handle_int(void);
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
/*
|
||||
* Clear all of the interrupts while we change the able around a bit.
|
||||
* int-handler is not on bootstrap
|
||||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
local_irq_disable();
|
||||
|
||||
/* Sets the first-level interrupt dispatcher. */
|
||||
set_except_vector(0, ocelot_handle_int);
|
||||
|
||||
mips_cpu_irq_init(0);
|
||||
rm7k_cpu_irq_init(8);
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Ocelot Board Register Definitions
|
||||
*
|
||||
* (C) 2001 Red Hat, Inc.
|
||||
*
|
||||
* GPL'd
|
||||
*/
|
||||
#ifndef __MOMENCO_OCELOT_PLD_H__
|
||||
#define __MOMENCO_OCELOT_PLD_H__
|
||||
|
||||
#define OCELOT_CS0_ADDR (0xe0020000)
|
||||
|
||||
#define OCELOT_REG_BOARDREV (0)
|
||||
#define OCELOT_REG_PLD1_ID (1)
|
||||
#define OCELOT_REG_PLD2_ID (2)
|
||||
#define OCELOT_REG_RESET_STATUS (3)
|
||||
#define OCELOT_REG_BOARD_STATUS (4)
|
||||
#define OCELOT_REG_CPCI_ID (5)
|
||||
#define OCELOT_REG_I2C_CTRL (8)
|
||||
#define OCELOT_REG_EEPROM_MODE (9)
|
||||
#define OCELOT_REG_INTMASK (10)
|
||||
#define OCELOT_REG_INTSTATUS (11)
|
||||
#define OCELOT_REG_INTSET (12)
|
||||
#define OCELOT_REG_INTCLR (13)
|
||||
|
||||
#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
|
||||
#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
|
||||
|
||||
|
||||
#endif /* __MOMENCO_OCELOT_PLD_H__ */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/pmon.h>
|
||||
|
||||
struct callvectors* debug_vectors;
|
||||
|
||||
extern unsigned long gt64120_base;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Momentum Ocelot";
|
||||
}
|
||||
|
||||
/* [jsun@junsun.net] PMON passes arguments in C main() style */
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
char **arg = (char **) fw_arg1;
|
||||
char **env = (char **) fw_arg2;
|
||||
struct callvectors *cv = (struct callvectors *) fw_arg3;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
||||
/* save the PROM vectors for debugging use */
|
||||
debug_vectors = cv;
|
||||
|
||||
/* arg[0] is "g", the rest is boot parameters */
|
||||
arcs_cmdline[0] = '\0';
|
||||
for (i = 1; i < argc; i++) {
|
||||
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
|
||||
>= sizeof(arcs_cmdline))
|
||||
break;
|
||||
strcat(arcs_cmdline, arg[i]);
|
||||
strcat(arcs_cmdline, " ");
|
||||
}
|
||||
|
||||
mips_machgroup = MACH_GROUP_MOMENCO;
|
||||
mips_machtype = MACH_MOMENCO_OCELOT;
|
||||
|
||||
while (*env) {
|
||||
if (strncmp("gtbase", *env, 6) == 0) {
|
||||
gt64120_base = simple_strtol(*env + strlen("gtbase="),
|
||||
NULL, 16);
|
||||
break;
|
||||
}
|
||||
*env++;
|
||||
}
|
||||
|
||||
debug_vectors->printf("Booting Linux kernel...\n");
|
||||
|
||||
/* All the boards have at least 64MiB. If there's more, we
|
||||
detect and register it later */
|
||||
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
|
||||
}
|
||||
|
||||
unsigned long __init prom_free_prom_memory(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Copyright (C) 1997, 2001 Ralf Baechle
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
void momenco_ocelot_restart(char *command)
|
||||
{
|
||||
void *nvram = ioremap_nocache(0x2c807000, 0x1000);
|
||||
|
||||
if (!nvram) {
|
||||
printk(KERN_NOTICE "ioremap of reset register failed\n");
|
||||
return;
|
||||
}
|
||||
writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
|
||||
assert reset in 1/16 second */
|
||||
mdelay(10+(1000/16));
|
||||
iounmap(nvram);
|
||||
printk(KERN_NOTICE "Watchdog reset failed\n");
|
||||
}
|
||||
|
||||
void momenco_ocelot_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
void momenco_ocelot_power_off(void)
|
||||
{
|
||||
momenco_ocelot_halt();
|
||||
}
|
||||
@@ -0,0 +1,369 @@
|
||||
/*
|
||||
* setup.c
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Momentum Computer Ocelot (CP7000) - board dependent boot routines
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Copyright (C) 2001 Red Hat, Inc.
|
||||
* Copyright (C) 2002 Momentum Computer
|
||||
*
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <asm/gt64120.h>
|
||||
#include "ocelot_pld.h"
|
||||
|
||||
unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
|
||||
|
||||
/* These functions are used for rebooting or halting the machine*/
|
||||
extern void momenco_ocelot_restart(char *command);
|
||||
extern void momenco_ocelot_halt(void);
|
||||
extern void momenco_ocelot_power_off(void);
|
||||
|
||||
extern void gt64120_time_init(void);
|
||||
extern void momenco_ocelot_irq_setup(void);
|
||||
|
||||
static char reset_reason;
|
||||
|
||||
#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
|
||||
|
||||
static void __init setup_l3cache(unsigned long size);
|
||||
|
||||
/* setup code for a handoff from a version 1 PMON 2000 PROM */
|
||||
void PMON_v1_setup()
|
||||
{
|
||||
/* A wired TLB entry for the GT64120A and the serial port. The
|
||||
GT64120A is going to be hit on every IRQ anyway - there's
|
||||
absolutely no point in letting it be a random TLB entry, as
|
||||
it'll just cause needless churning of the TLB. And we use
|
||||
the other half for the serial port, which is just a PITA
|
||||
otherwise :)
|
||||
|
||||
Device Physical Virtual
|
||||
GT64120 Internal Regs 0x24000000 0xe0000000
|
||||
UARTs (CS2) 0x2d000000 0xe0001000
|
||||
*/
|
||||
add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
|
||||
|
||||
/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
|
||||
in the CS[012] region. We can't use ioremap() yet. The NVRAM
|
||||
is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
|
||||
|
||||
Ocelot PLD (CS0) 0x2c000000 0xe0020000
|
||||
NVRAM 0x2c800000 0xe0030000
|
||||
*/
|
||||
|
||||
add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
|
||||
|
||||
/* Relocate the CS3/BootCS region */
|
||||
GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
|
||||
|
||||
/* Relocate CS[012] */
|
||||
GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
|
||||
|
||||
/* Relocate the GT64120A itself... */
|
||||
GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
|
||||
mb();
|
||||
gt64120_base = 0xe0000000;
|
||||
|
||||
/* ...and the PCI0 view of it. */
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
|
||||
}
|
||||
|
||||
/* setup code for a handoff from a version 2 PMON 2000 PROM */
|
||||
void PMON_v2_setup()
|
||||
{
|
||||
/* A wired TLB entry for the GT64120A and the serial port. The
|
||||
GT64120A is going to be hit on every IRQ anyway - there's
|
||||
absolutely no point in letting it be a random TLB entry, as
|
||||
it'll just cause needless churning of the TLB. And we use
|
||||
the other half for the serial port, which is just a PITA
|
||||
otherwise :)
|
||||
|
||||
Device Physical Virtual
|
||||
GT64120 Internal Regs 0xf4000000 0xe0000000
|
||||
UARTs (CS2) 0xfd000000 0xe0001000
|
||||
*/
|
||||
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
|
||||
|
||||
/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
|
||||
in the CS[012] region. We can't use ioremap() yet. The NVRAM
|
||||
is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
|
||||
|
||||
Ocelot PLD (CS0) 0xfc000000 0xe0020000
|
||||
NVRAM 0xfc800000 0xe0030000
|
||||
*/
|
||||
add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
|
||||
|
||||
gt64120_base = 0xe0000000;
|
||||
}
|
||||
|
||||
static void __init momenco_ocelot_setup(void)
|
||||
{
|
||||
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
|
||||
unsigned int tmpword;
|
||||
|
||||
board_time_init = gt64120_time_init;
|
||||
|
||||
_machine_restart = momenco_ocelot_restart;
|
||||
_machine_halt = momenco_ocelot_halt;
|
||||
_machine_power_off = momenco_ocelot_power_off;
|
||||
|
||||
/*
|
||||
* initrd_start = (ulong)ocelot_initrd_start;
|
||||
* initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
|
||||
* initrd_below_start_ok = 1;
|
||||
*/
|
||||
|
||||
/* do handoff reconfiguration */
|
||||
if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
|
||||
PMON_v1_setup();
|
||||
else
|
||||
PMON_v2_setup();
|
||||
|
||||
/* Turn off the Bit-Error LED */
|
||||
OCELOT_PLD_WRITE(0x80, INTCLR);
|
||||
|
||||
/* Relocate all the PCI1 stuff, not that we use it */
|
||||
GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
|
||||
GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
|
||||
GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
|
||||
|
||||
/* Relocate PCI0 I/O and Mem0 */
|
||||
GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
|
||||
GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
|
||||
|
||||
/* Relocate PCI0 Mem1 */
|
||||
GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
|
||||
|
||||
/* For the initial programming, we assume 512MB configuration */
|
||||
/* Relocate the CPU's view of the RAM... */
|
||||
GT_WRITE(GT_SCS10LD_OFS, 0);
|
||||
GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
|
||||
GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
|
||||
GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
|
||||
|
||||
GT_WRITE(GT_SCS1LD_OFS, 0xff);
|
||||
GT_WRITE(GT_SCS1HD_OFS, 0x00);
|
||||
GT_WRITE(GT_SCS0LD_OFS, 0);
|
||||
GT_WRITE(GT_SCS0HD_OFS, 0xff);
|
||||
GT_WRITE(GT_SCS3LD_OFS, 0xff);
|
||||
GT_WRITE(GT_SCS3HD_OFS, 0x00);
|
||||
GT_WRITE(GT_SCS2LD_OFS, 0);
|
||||
GT_WRITE(GT_SCS2HD_OFS, 0xff);
|
||||
|
||||
/* ...and the PCI0 view of it. */
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(BOARDREV);
|
||||
if (tmpword < 26)
|
||||
printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
|
||||
else
|
||||
printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(PLD1_ID);
|
||||
printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
|
||||
tmpword = OCELOT_PLD_READ(PLD2_ID);
|
||||
printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
|
||||
tmpword = OCELOT_PLD_READ(RESET_STATUS);
|
||||
printk("Reset reason: 0x%x\n", tmpword);
|
||||
reset_reason = tmpword;
|
||||
OCELOT_PLD_WRITE(0xff, RESET_STATUS);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(BOARD_STATUS);
|
||||
printk("Board Status register: 0x%02x\n", tmpword);
|
||||
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
|
||||
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
|
||||
printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
|
||||
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
|
||||
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
|
||||
|
||||
if (tmpword&12)
|
||||
l3func((1<<(((tmpword&12) >> 2)+20)));
|
||||
|
||||
switch(tmpword &3) {
|
||||
case 3:
|
||||
/* 512MiB */
|
||||
/* Decoders are allready set -- just add the
|
||||
* appropriate region */
|
||||
add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
|
||||
add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
case 2:
|
||||
/* 256MiB -- two banks of 128MiB */
|
||||
GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
|
||||
GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
|
||||
GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
|
||||
|
||||
GT_WRITE(GT_SCS0HD_OFS, 0x7f);
|
||||
GT_WRITE(GT_SCS2LD_OFS, 0x80);
|
||||
GT_WRITE(GT_SCS2HD_OFS, 0xff);
|
||||
|
||||
/* reconfigure the PCI0 interface view of memory */
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
|
||||
|
||||
add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
|
||||
add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
case 1:
|
||||
/* 128MiB -- 64MiB per bank */
|
||||
GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
|
||||
GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
|
||||
GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
|
||||
|
||||
GT_WRITE(GT_SCS0HD_OFS, 0x3f);
|
||||
GT_WRITE(GT_SCS2LD_OFS, 0x40);
|
||||
GT_WRITE(GT_SCS2HD_OFS, 0x7f);
|
||||
|
||||
/* reconfigure the PCI0 interface view of memory */
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
|
||||
|
||||
/* add the appropriate region */
|
||||
add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
case 0:
|
||||
/* 64MiB */
|
||||
GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
|
||||
GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
|
||||
GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
|
||||
|
||||
GT_WRITE(GT_SCS0HD_OFS, 0x1f);
|
||||
GT_WRITE(GT_SCS2LD_OFS, 0x20);
|
||||
GT_WRITE(GT_SCS2HD_OFS, 0x3f);
|
||||
|
||||
/* reconfigure the PCI0 interface view of memory */
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
|
||||
GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
|
||||
GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* Fix up the DiskOnChip mapping */
|
||||
GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
|
||||
}
|
||||
|
||||
early_initcall(momenco_ocelot_setup);
|
||||
|
||||
extern int rm7k_tcache_enabled;
|
||||
/*
|
||||
* This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
|
||||
*/
|
||||
#define Page_Invalidate_T 0x16
|
||||
static void __init setup_l3cache(unsigned long size)
|
||||
{
|
||||
int register i;
|
||||
unsigned long tmp;
|
||||
|
||||
printk("Enabling L3 cache...");
|
||||
|
||||
/* Enable the L3 cache in the GT64120A's CPU Configuration register */
|
||||
tmp = GT_READ(GT_CPU_OFS);
|
||||
GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
|
||||
|
||||
/* Enable the L3 cache in the CPU */
|
||||
set_c0_config(1<<12 /* CONF_TE */);
|
||||
|
||||
/* Clear the cache */
|
||||
write_c0_taglo(0);
|
||||
write_c0_taghi(0);
|
||||
|
||||
for (i=0; i < size; i+= 4096) {
|
||||
__asm__ __volatile__ (
|
||||
".set noreorder\n\t"
|
||||
".set mips3\n\t"
|
||||
"cache %1, (%0)\n\t"
|
||||
".set mips0\n\t"
|
||||
".set reorder"
|
||||
:
|
||||
: "r" (KSEG0ADDR(i)),
|
||||
"i" (Page_Invalidate_T));
|
||||
}
|
||||
|
||||
/* Let the RM7000 MM code know that the tertiary cache is enabled */
|
||||
rm7k_tcache_enabled = 1;
|
||||
|
||||
printk("Done\n");
|
||||
}
|
||||
|
||||
|
||||
/* This needs to be one of the first initcalls, because no I/O port access
|
||||
can work before this */
|
||||
|
||||
static int io_base_ioremap(void)
|
||||
{
|
||||
void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
|
||||
|
||||
if (!io_remap_range) {
|
||||
panic("Could not ioremap I/O port range");
|
||||
}
|
||||
set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_init(io_base_ioremap);
|
||||
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