Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
这个提交包含在：
Linus Torvalds
491
arch/arm/mm/proc-arm1026.S
普通文件
491
arch/arm/mm/proc-arm1026.S
普通文件
@@ -0,0 +1,491 @@
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/*
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* linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the ARM1026EJ-S.
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*/
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#include <linux/linkage.h>
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/constants.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* The number of data cache segments.
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*/
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#define CACHE_DSEGMENTS 16
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/*
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* The number of lines in a cache segment.
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*/
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#define CACHE_DENTRIES 64
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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* cache line maintainence instructions.
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*/
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#define CACHE_DLIMIT 32768
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.text
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/*
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* cpu_arm1026_proc_init()
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*/
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ENTRY(cpu_arm1026_proc_init)
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mov pc, lr
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/*
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* cpu_arm1026_proc_fin()
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*/
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ENTRY(cpu_arm1026_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl arm1026_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_arm1026_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_arm1026_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_arm1026_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm1026_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/* ================================= CACHE ================================ */
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.align 5
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(arm1026_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm1026_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
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bne 1b
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags for this space
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*/
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ENTRY(arm1026_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bhs __flush_whole_cache
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1026_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1026_coherent_user_range)
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mov ip, #0
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - page - page aligned address
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*/
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ENTRY(arm1026_flush_kern_dcache_page)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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ENTRY(arm1026_dma_inv_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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ENTRY(arm1026_dma_clean_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1026_dma_flush_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(arm1026_cache_fns)
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.long arm1026_flush_kern_cache_all
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.long arm1026_flush_user_cache_all
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.long arm1026_flush_user_cache_range
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.long arm1026_coherent_kern_range
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.long arm1026_coherent_user_range
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.long arm1026_flush_kern_dcache_page
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.long arm1026_dma_inv_range
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.long arm1026_dma_clean_range
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.long arm1026_dma_flush_range
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.align 5
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ENTRY(cpu_arm1026_dcache_clean_area)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mov ip, #0
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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#endif
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mov pc, lr
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/* =============================== PageTable ============================== */
|
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/*
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* cpu_arm1026_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
|
||||
*/
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.align 5
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ENTRY(cpu_arm1026_switch_mm)
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mov r1, #0
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||||
#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
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||||
bne 1b
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||||
#endif
|
||||
#ifndef CONFIG_CPU_ICACHE_DISABLE
|
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
|
||||
#endif
|
||||
mcr p15, 0, r1, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* cpu_arm1026_set_pte(ptep, pte)
|
||||
*
|
||||
* Set a PTE and flush it out
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm1026_set_pte)
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
|
||||
bic r2, r1, #PTE_SMALL_AP_MASK
|
||||
bic r2, r2, #PTE_TYPE_MASK
|
||||
orr r2, r2, #PTE_TYPE_SMALL
|
||||
|
||||
tst r1, #L_PTE_USER @ User?
|
||||
orrne r2, r2, #PTE_SMALL_AP_URO_SRW
|
||||
|
||||
tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
|
||||
orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
|
||||
|
||||
tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
|
||||
movne r2, #0
|
||||
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
eor r3, r1, #0x0a @ C & small page?
|
||||
tst r3, #0x0b
|
||||
biceq r2, r2, #4
|
||||
#endif
|
||||
str r2, [r0] @ hardware version
|
||||
mov r0, r0
|
||||
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
|
||||
__INIT
|
||||
|
||||
.type __arm1026_setup, #function
|
||||
__arm1026_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
mcr p15, 0, r4, c2, c0 @ load page table pointer
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mov r0, #4 @ explicitly disable writeback
|
||||
mcr p15, 7, r0, c15, c0, 0
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
ldr r5, arm1026_cr1_clear
|
||||
bic r0, r0, r5
|
||||
ldr r5, arm1026_cr1_set
|
||||
orr r0, r0, r5
|
||||
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
||||
orr r0, r0, #0x4000 @ .R.. .... .... ....
|
||||
#endif
|
||||
mov pc, lr
|
||||
.size __arm1026_setup, . - __arm1026_setup
|
||||
|
||||
/*
|
||||
* R
|
||||
* .RVI ZFRS BLDP WCAM
|
||||
* .011 1001 ..11 0101
|
||||
*
|
||||
*/
|
||||
.type arm1026_cr1_clear, #object
|
||||
.type arm1026_cr1_set, #object
|
||||
arm1026_cr1_clear:
|
||||
.word 0x7f3f
|
||||
arm1026_cr1_set:
|
||||
.word 0x3935
|
||||
|
||||
__INITDATA
|
||||
|
||||
/*
|
||||
* Purpose : Function pointers used to access above functions - all calls
|
||||
* come through these
|
||||
*/
|
||||
.type arm1026_processor_functions, #object
|
||||
arm1026_processor_functions:
|
||||
.word v5t_early_abort
|
||||
.word cpu_arm1026_proc_init
|
||||
.word cpu_arm1026_proc_fin
|
||||
.word cpu_arm1026_reset
|
||||
.word cpu_arm1026_do_idle
|
||||
.word cpu_arm1026_dcache_clean_area
|
||||
.word cpu_arm1026_switch_mm
|
||||
.word cpu_arm1026_set_pte
|
||||
.size arm1026_processor_functions, . - arm1026_processor_functions
|
||||
|
||||
.section .rodata
|
||||
|
||||
.type cpu_arch_name, #object
|
||||
cpu_arch_name:
|
||||
.asciz "armv5tej"
|
||||
.size cpu_arch_name, . - cpu_arch_name
|
||||
|
||||
.type cpu_elf_name, #object
|
||||
cpu_elf_name:
|
||||
.asciz "v5"
|
||||
.size cpu_elf_name, . - cpu_elf_name
|
||||
.align
|
||||
|
||||
.type cpu_arm1026_name, #object
|
||||
cpu_arm1026_name:
|
||||
.ascii "ARM1026EJ-S"
|
||||
#ifndef CONFIG_CPU_ICACHE_DISABLE
|
||||
.ascii "i"
|
||||
#endif
|
||||
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
||||
.ascii "d"
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
.ascii "(wt)"
|
||||
#else
|
||||
.ascii "(wb)"
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_CPU_BPREDICT_DISABLE
|
||||
.ascii "B"
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
||||
.ascii "RR"
|
||||
#endif
|
||||
.ascii "\0"
|
||||
.size cpu_arm1026_name, . - cpu_arm1026_name
|
||||
|
||||
.align
|
||||
|
||||
.section ".proc.info", #alloc, #execinstr
|
||||
|
||||
.type __arm1026_proc_info,#object
|
||||
__arm1026_proc_info:
|
||||
.long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
|
||||
.long 0xff0ffff0
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_BIT4 | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
b __arm1026_setup
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
|
||||
.long cpu_arm1026_name
|
||||
.long arm1026_processor_functions
|
||||
.long v4wbi_tlb_fns
|
||||
.long v4wb_user_fns
|
||||
.long arm1026_cache_fns
|
||||
.size __arm1026_proc_info, . - __arm1026_proc_info
|
||||
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