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ARM: Add platform support for LSI AXM55xx SoC

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The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.

This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.

Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Anders Berg
2014-05-23 11:08:35 +02:00
committed by Arnd Bergmann
parent a798c10faf
commit 1d22924e1c
8 changed files with 187 additions and 0 deletions
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36
include/dt-bindings/clock/lsi,axm5516-clks.h Normal file
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/*
* Copyright (c) 2014 LSI Corporation
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*/
#ifndef _DT_BINDINGS_CLK_AXM5516_H
#define _DT_BINDINGS_CLK_AXM5516_H
#define AXXIA_CLK_FAB_PLL 0
#define AXXIA_CLK_CPU_PLL 1
#define AXXIA_CLK_SYS_PLL 2
#define AXXIA_CLK_SM0_PLL 3
#define AXXIA_CLK_SM1_PLL 4
#define AXXIA_CLK_FAB_DIV 5
#define AXXIA_CLK_SYS_DIV 6
#define AXXIA_CLK_NRCP_DIV 7
#define AXXIA_CLK_CPU0_DIV 8
#define AXXIA_CLK_CPU1_DIV 9
#define AXXIA_CLK_CPU2_DIV 10
#define AXXIA_CLK_CPU3_DIV 11
#define AXXIA_CLK_PER_DIV 12
#define AXXIA_CLK_MMC_DIV 13
#define AXXIA_CLK_FAB 14
#define AXXIA_CLK_SYS 15
#define AXXIA_CLK_NRCP 16
#define AXXIA_CLK_CPU0 17
#define AXXIA_CLK_CPU1 18
#define AXXIA_CLK_CPU2 19
#define AXXIA_CLK_CPU3 20
#define AXXIA_CLK_PER 21
#define AXXIA_CLK_MMC 22
#endif