Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: "Various fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86-64, kcmp: The kcmp system call can be common arch/x86/kernel/kdebugfs.c: Ensure a consistent return value in error case x86/mce: Add quirk for instruction recovery on Sandy Bridge processors x86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h> x86/ioapic: Fix NULL pointer dereference on CPU hotplug after disabling irqs x86, nops: Missing break resulting in incorrect selection on Intel x86: CONFIG_CC_STACKPROTECTOR=y is no longer experimental
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@@ -55,13 +55,6 @@ static struct severity {
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#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
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#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
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#define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
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#define MCACOD 0xffff
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xfff0
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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MCESEV(
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NO, "Invalid",
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@@ -103,6 +103,8 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
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static DEFINE_PER_CPU(struct work_struct, mce_work);
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static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
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/*
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* CPU/chipset specific EDAC code can register a notifier call here to print
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* MCE errors in a human-readable form.
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@@ -650,14 +652,18 @@ EXPORT_SYMBOL_GPL(machine_check_poll);
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* Do a quick check if any of the events requires a panic.
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* This decides if we keep the events around or clear them.
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*/
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static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp)
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static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
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struct pt_regs *regs)
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{
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int i, ret = 0;
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for (i = 0; i < banks; i++) {
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m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
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if (m->status & MCI_STATUS_VAL)
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if (m->status & MCI_STATUS_VAL) {
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__set_bit(i, validp);
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if (quirk_no_way_out)
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quirk_no_way_out(i, m, regs);
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}
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if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
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ret = 1;
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}
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@@ -1040,7 +1046,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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*final = m;
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memset(valid_banks, 0, sizeof(valid_banks));
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no_way_out = mce_no_way_out(&m, &msg, valid_banks);
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no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
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barrier();
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@@ -1418,6 +1424,34 @@ static void __mcheck_cpu_init_generic(void)
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}
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}
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/*
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* During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
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* EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
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* Vol 3B Table 15-20). But this confuses both the code that determines
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* whether the machine check occurred in kernel or user mode, and also
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* the severity assessment code. Pretend that EIPV was set, and take the
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* ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
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*/
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static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
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{
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if (bank != 0)
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return;
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if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
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return;
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if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
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MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
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MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
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MCACOD)) !=
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(MCI_STATUS_UC|MCI_STATUS_EN|
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MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
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MCI_STATUS_AR|MCACOD_INSTR))
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return;
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m->mcgstatus |= MCG_STATUS_EIPV;
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m->ip = regs->ip;
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m->cs = regs->cs;
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}
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/* Add per CPU specific workarounds here */
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static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
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{
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@@ -1515,6 +1549,9 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
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*/
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if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
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mce_bootlog = 0;
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if (c->x86 == 6 && c->x86_model == 45)
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quirk_no_way_out = quirk_sandybridge_ifu;
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}
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if (monarch_timeout < 0)
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monarch_timeout = 0;
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