Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (53 commits) iommu/amd: Set IOTLB invalidation timeout iommu/amd: Init stats for iommu=pt iommu/amd: Remove unnecessary cache flushes in amd_iommu_resume iommu/amd: Add invalidate-context call-back iommu/amd: Add amd_iommu_device_info() function iommu/amd: Adapt IOMMU driver to PCI register name changes iommu/amd: Add invalid_ppr callback iommu/amd: Implement notifiers for IOMMUv2 iommu/amd: Implement IO page-fault handler iommu/amd: Add routines to bind/unbind a pasid iommu/amd: Implement device aquisition code for IOMMUv2 iommu/amd: Add driver stub for AMD IOMMUv2 support iommu/amd: Add stat counter for IOMMUv2 events iommu/amd: Add device errata handling iommu/amd: Add function to get IOMMUv2 domain for pdev iommu/amd: Implement function to send PPR completions iommu/amd: Implement functions to manage GCR3 table iommu/amd: Implement IOMMUv2 TLB flushing routines iommu/amd: Add support for IOMMUv2 domain mode iommu/amd: Add amd_iommu_domain_direct_map function ...
This commit is contained in:
Linus Torvalds
@@ -79,6 +79,24 @@
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#define LEVEL_STRIDE (9)
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#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
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/*
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* This bitmap is used to advertise the page sizes our hardware support
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* to the IOMMU core, which will then use this information to split
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* physically contiguous memory regions it is mapping into page sizes
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* that we support.
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*
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* Traditionally the IOMMU core just handed us the mappings directly,
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* after making sure the size is an order of a 4KiB page and that the
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* mapping has natural alignment.
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*
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* To retain this behavior, we currently advertise that we support
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* all page sizes that are an order of 4KiB.
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*
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* If at some point we'd like to utilize the IOMMU core's new behavior,
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* we could change this to advertise the real page sizes we support.
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*/
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#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
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static inline int agaw_to_level(int agaw)
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{
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return agaw + 2;
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@@ -3979,12 +3997,11 @@ static void intel_iommu_detach_device(struct iommu_domain *domain,
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static int intel_iommu_map(struct iommu_domain *domain,
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unsigned long iova, phys_addr_t hpa,
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int gfp_order, int iommu_prot)
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size_t size, int iommu_prot)
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{
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struct dmar_domain *dmar_domain = domain->priv;
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u64 max_addr;
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int prot = 0;
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size_t size;
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int ret;
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if (iommu_prot & IOMMU_READ)
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@@ -3994,7 +4011,6 @@ static int intel_iommu_map(struct iommu_domain *domain,
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if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
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prot |= DMA_PTE_SNP;
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size = PAGE_SIZE << gfp_order;
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max_addr = iova + size;
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if (dmar_domain->max_addr < max_addr) {
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u64 end;
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@@ -4017,11 +4033,10 @@ static int intel_iommu_map(struct iommu_domain *domain,
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return ret;
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}
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static int intel_iommu_unmap(struct iommu_domain *domain,
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unsigned long iova, int gfp_order)
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static size_t intel_iommu_unmap(struct iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct dmar_domain *dmar_domain = domain->priv;
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size_t size = PAGE_SIZE << gfp_order;
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int order;
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order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
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@@ -4030,7 +4045,7 @@ static int intel_iommu_unmap(struct iommu_domain *domain,
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if (dmar_domain->max_addr == iova + size)
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dmar_domain->max_addr = iova;
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return order;
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return PAGE_SIZE << order;
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}
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static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
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@@ -4060,6 +4075,54 @@ static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
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return 0;
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}
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/*
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* Group numbers are arbitrary. Device with the same group number
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* indicate the iommu cannot differentiate between them. To avoid
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* tracking used groups we just use the seg|bus|devfn of the lowest
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* level we're able to differentiate devices
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*/
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static int intel_iommu_device_group(struct device *dev, unsigned int *groupid)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct pci_dev *bridge;
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union {
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struct {
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u8 devfn;
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u8 bus;
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u16 segment;
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} pci;
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u32 group;
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} id;
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if (iommu_no_mapping(dev))
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return -ENODEV;
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id.pci.segment = pci_domain_nr(pdev->bus);
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id.pci.bus = pdev->bus->number;
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id.pci.devfn = pdev->devfn;
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if (!device_to_iommu(id.pci.segment, id.pci.bus, id.pci.devfn))
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return -ENODEV;
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bridge = pci_find_upstream_pcie_bridge(pdev);
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if (bridge) {
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if (pci_is_pcie(bridge)) {
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id.pci.bus = bridge->subordinate->number;
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id.pci.devfn = 0;
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} else {
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id.pci.bus = bridge->bus->number;
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id.pci.devfn = bridge->devfn;
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}
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}
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if (!pdev->is_virtfn && iommu_group_mf)
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id.pci.devfn = PCI_DEVFN(PCI_SLOT(id.pci.devfn), 0);
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*groupid = id.group;
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return 0;
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}
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static struct iommu_ops intel_iommu_ops = {
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.domain_init = intel_iommu_domain_init,
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.domain_destroy = intel_iommu_domain_destroy,
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@@ -4069,6 +4132,8 @@ static struct iommu_ops intel_iommu_ops = {
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.unmap = intel_iommu_unmap,
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.iova_to_phys = intel_iommu_iova_to_phys,
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.domain_has_cap = intel_iommu_domain_has_cap,
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.device_group = intel_iommu_device_group,
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.pgsize_bitmap = INTEL_IOMMU_PGSIZES,
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};
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static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
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